Beruflich Dokumente
Kultur Dokumente
1999-2000
MODEL RELEASE
MODEL CHASSIS
50CX29B AP-90
60CX29B AP-90
50GX49B AP-92
50UX57B AP-83R
60UX57B AP-83R
53SBX59B AP-93
61SBX59B AP-93
DIGITAL
61HDX98B DP-85
60SDX88B DP-86
53SDX89B DP-86
52LDX99B DL-1
36SDX88B MM-1
27MM30V PA-2
Page A1
Contents Page
AP-93 CHASSIS TABLE OF CONTENTS
Page A2
GENERAL
INFORMATION
SECTION 1
PTV MODEL TO CHASSIS CROSS REFERENCE CHART
PAGE 01-01
PTV CHASSIS TO MODEL CROSS REFERENCE CHART
PAGE 01-02
CTV MODEL TO CHASSIS CROSS REFERENCE CHART
PAGE 01-03
CTV CHASSIS TO MODEL CROSS REFERENCE CHART
PAGE 01-04
61SBX59B and the 53SBX59B Chassis AP-93
Page 01-05
Description Part Number Description Part Number
MAIN CHASSIS UE05433 POWER / DEFLECTION PWB JT09173
SIGNAL PWB JT09163 • BRIDGE RECTIFIER D901 (2338313)
• MICROPROCESSOR I001 (CP06614U) • VERTICAL OUTPUT (LA7838) I601 (2003541)
• MEMORY (Service Adjustments) I004 (CP05272U) • SIDE PIN CUSHION (Comparator) I602 (CP06351U)
• RESET IC for Microprocessor I007 (2000541) • SWITCHING REGULATOR (Driver IC) I901 (CZ00451)
• MICROPROCESSOR for OSD I102 (CP05243U) • SHUT DOWN (Photo Coupler) I902 (2000465)
• RESET IC for OSD Microprocessor I103 (2000541) • 120V REGULATOR (Photo Coupler) I903 (2000465)
• 5 Volt REGULATOR (Prescaler) I106 (CP05571) • 120V REGULATOR I905 (2381349)
• AUDIO OUTPUT IC (TA8200AH) I401 (2004751) • +12 REGULATOR I908 (CP05573)
• 5 Volt REGULATOR for Microprocessor Q026 (2312171) • –12 REGULATOR (M12V) I909 (1360891)
• X100 (32kH VCO Crystal) X100 (BP00771) • A12V REGULATOR I910 (CP03912F)
PinP TUNER U102 (2429691) • TV9V REGULATOR I912 (CP03923F)
PinP UNIT KC-021 U002 (HP00202) • TV5V REGULATOR I913 (CP03922F)
• +5V REGULATOR Dig. Conv. IK01 (CP05571)
3D/YC COMB FILTER PWB U301 (HP00703)
• +5V REGULATOR Dig. Conv. SRAM IK03 (CP05571)
TERMINAL PWB JT09473 • CONVERGENCE OUTPUT (RH, GH & GV) IK04 (CZ00431)
• A/V SELECT IC IY01 (2020452) • CONVERGENCE OUTPUT (RV, BH & BV) IK05 (CZ00431)
• +9V REGULATOR IY02 (2003423) • HORIZONTAL DRIVE TRANSFORMER T701 (2260291U)
SURROUND PWB JT09222 • FLYBACK TRANSFORMER (High Voltage) T702 (BW00632)
• FRONT GRAPHIC EQUALIZATION IG01 (CP02771U) • HIGH VOLTAGE DRIVER (2SC3116 S/T) Q701 (2326216)
• CENTER GRAPHIC EQUALIZATION IG10 (CP02771U) • HORIZONTAL OUTPUT (2SC2514F) Q777 (CF01541F)
• DOLBY PRO LOGIC DECODER IS01 (CP00801U) • 120V B+ CURRENT SENSING (2SA821S) Q903 (CF02281R)
• DOLBY PASSIVE DECODER IS03 (CP00791U) • SHUT DOWN SCR (03P2M TA) Q914 (2323782R)
• FRONT/PinP AUDIO CONTROL IS05 (2020001) • HORIZONTAL Vcc ON/OFF SW (2SC458) Q916 (2320591M)
• REAR/CENTER AUDIO CONTROL IS10 (2020001) • 220V (Screen Voltage) PROTECTOR E701 (AZ00107M)
• REAR AUDIO OUTPUT IC IS11 (2004751) • RAW 150V PROTECTOR E991 (AZ00109M)
• PERFECT VOLUME IS12 (CP02601) • B+ 120V (Main B+) PROTECTOR E994 (AZ00104M)
SIGNAL SUB PWB Part of Signal PWB JT09163 • +27V PROTECTOR E995 (AZ00109M)
• RAINFOREST IC (TA1222BN) I501 (CP03552U) • -23V PROTECTOR E996 (AZ00109M)
• COMPONENT SELECTOR IC I503 (CK08951R) • Audio +32V PROTECTOR E997 (AZ00109M)
• X502 (32fH VCO Crystal) X502 (2168771) • Audio +22V PROTECTOR E998 (AZ00109M)
• X501 (Crystal) X501 (2791501) • +31V PROTECTOR E999 (AZ00109M)
DIGITAL Convergence Unit (UKDG) CS00351
61SBX59B and the 53SBX59B Chassis AP-93
Page 01-06
Description Part Number Description Part Number
• INFRARED RECEIVER HM01 (CZ00523)
VELOCITY MODULATION PWB
Comes with CRT PWB’s JT09192
CRT PWB
Includes the Velocity Modulation PWB JT09192
• RED DRIVER Q861 (2312372F)
• GREEN DRIVER Q831 (2312372F)
• BLUE DRIVER Q801 (2312372F)
CRT Sockets
• RED CRT SOCKET E861 (EY00941)
• GREEN CRT SOCKET E831 (EY00941)
• BLUE CRT SOCKET E801 (EY00941)
REMOTE CONTROL CLU-615MP HL00715
Additional Parts Information
WARNING:
DO NOT FORCE OUT, DAMAGE TO WINGS WILL OCCUR !
Anode Button
"WINGS"
"WINGS" NOTE:
NOTE: Easy to bend!
Easy to bend!
Inserts into
Flyback
Page 01-07
MICROPROCESSOR
INFORMATION
SECTION 2
AP-93 CHASSIS MICROPROCESSOR DATA COMMUNICATIONS CIRCUIT DIAGRAM
A5V
1 I103 3
RO59 Reset
C128
IOO1 2 I102 IOO4
Micro Processor OSD uP EEPROM
R060 R161 Q107 Terminal PWB
OSD Reset 45 35 Reset
R160 IY01
PCB A/V Select
SDA1 /OSD R078 R1B2 R0G6 RY10
OSD Feed Back /
2 4 Port OB SDA3 5 6 20 SDA3
Feedback A5V
R0G5 RY09
RO37 R038 R147 SCL3 6 7 19 SCL3
SDA2 59 12 SDA2 / Port 01 I2SSD
A5V
RO35 R036 R146
SCL2 60 11 SCL2 / Port 02 I2SSC
PSU1
R040
SDA3 57 5 SDA3
R0R1
SCL3 58 4 SCL3
PSU2 See
Surroun
KeyOut 3 / DATA 36 13 DATA d
KeyOut 4 / CLOCK 37 12 CLOCK PWB
R041
LOAD 56 R0P1
14 LOAD
GEQ CLK 18 15 GEQ CLK
A5V
Hi = External
YUVSW 48 QA32 Lo = Internal YUVSW
PSI2
7 CTLC I503
R5E9
R0A8 Q119 17 2 CTLA Comp
KeyOut 1 / FE-CLK 28 4 Clock U101
YOUSW
12 CTLB Switch
R0A9 R128 Tuner 1
KeyOut 2 / FE-DATA 29 5 Data A5V
(MTS) PSI1
R0C1 R127 R572
FE-ENABLE 1 30 6 Enable Main D507
R571
R0P3 R114 1 28 SCL3 I501
Page 02-01
17 Data
DATA
RG09
GEQ
15 16 Clock
CLK GEQ CLK
AP-93 Series Chassis AUDIO and VIDEO MUTE Circuit
"HV PROTECT" (See also Terminal Mute Circuit)
Horizontal Sweep Loss A12V
Det. R0E3 D055
Vertical Sweep Loss Det.
AC Loss Det.
D041 PSI1Lum. Sub PWB I501
Q028 C545 Service
(From Deflection PWB) R0E4
R0M2 Q014 H.Blk 14
PSD2 C040
R569
6 V. Mute 2 R0T1 D513
FBP
R0E7 8 25
ROE5 D024 In
V. R0R8 V. Mute
Q015 R0E8
D040 Mute R0T1
Micro
Processor ROE6
I001 RO49
V MUTE 1 51 A+5V PCB
RO50 12 Terminal
11 PWB
Q013
MUTE 50
V.
R
MUTE 2
Mute
C019 R0E2
Signal PWB D401 D405 Mute = Lo
U101 R134 R411 I401
D404 R412 11 Mute
Q403 C411 FRONT
MUTE 24 PSU1
R413 C412 L&R
From IZ05 <F. Spk Off> Audio
16
pin 2 Output
C402 C405 R In R
TUNER 14 2 12
1 < Right Ft. Audio > Out
SRS PWB 15 4 L In L Out 7
Page02-03
RA49
RA53
AP-93 PICTURE BLANKING AND VELOCITY MODULATION MUTE CIRCUIT
5V
I105
Blank 27 13
PSI1 I501
I102 11 Q008
12 Rainforest IC
OSD Micro YS1/VM
Processor 7 36 YS2
OSD < 0.75V
YS Normal RGB signal
5V used.
= or > 2.25V
Picture Q030 OSD RGB used
P Blk 52
Blanking PBlk
PSI2
PIP
YS1/VM YS PinP
12 PinP module
U002 MV7
PSD1 5V
Digital Q007 D112 PVM1
Convergence 41 Busy
Module Busy Dig. circuit
Velocity
Busy 4
Modulation PWB
Page 02-05
YS1/VM
D005 D111
= or > 0.75V
Velocity Modulation Defeated
AP-93 AUTO LINK DETECTION CIRUCIT
Video 1 In
C 11 C2
19 SCL 3 6 58
12 S2
Video 1 SDA 3
7 V2 20 7 57
Video 2
13 V3
S-Video
S-2 In Y PCD
2 In
15 Y3 QA74 V Detection
C 17 C3
V Out 2 40 19 21 S/V Det
18 S3 DA15 V/Y Active
Y QA75 Det High
To I503 Y Out 2 43
Component Video DA16
6 S1 S Detection
5 C1 S-Video
3 In
3 Y1 IR Det.
1 V1 20
PFV
Front Control PWB
9 Video 3
V3 Y Y S-3 In
5 PFJ Q019 DA25
V3 C C
Page 02-06
3 HM01 2
S3 Det
1 IR Receiver QM01 Signal PWB 1of 4
AP-93 CHASSIS "On Screen Display, OSD" SIGNAL CIRCUIT DIAGRAM
Q108 ZB
Sync2 for Closed Caption
13
I102 24 5 I106 4
Q110
OSD 25 2 15 ZG
Q109 ZR
Up 26 12 14
Signal PWB I001 Data & Clock
I105
Main uP SDA2 / SCL2 Blank
27 13 D/H OSD Sel
11
12
HB HB OSD Blk. Q111 BTX
OSD B 42 10
1 B 8
HG 9
OSD G 43 H002 HG Dig OSD Q112
Q027 HR 4 GTX
32 OSD R 44 G 6
Bus 5
HR Dig OSD Q113
y 28 P Blk 52 1 RTX
OSD Blk R 3
2
OSD Blk 41 Dig OSD
Q008
A5V
PDG PSD1 P Blk OSD Blk.
IR
YS1/VM
HM01 2 13 2
6 Busy
QK07 OSD G Q007 D005
UKDG 12 4 A5V
Front QK06 OSD R PY1
HC2091 11 2
6 PVM1
Control Signal SUB PWB
Q517 YS1/VM
PWB Digital 4
I501 41 5 B
To CRTs
Q516
Convergenc
1 -5V Rain 42 4 G
e Q515 D111
2 forest 43 3 R
Unit
3 +5V D112 PINP
"DCU" (PInP) PSI2
4 +5V SRAM
Deflection PWB
OSD G 38 5
OSD B 37 6
Signal PWB
AP-93 MEMORY INITIALIZATION PROCEDURE (EEPROM RESET)
NOTE: All customers' Auto Programming and Set-Ups are returned to factory settings.
Jumper
1 2 P001
Connector
D058
R0C4 R0C5
32 29
KEY-IN1 FE-DATA
I001 KEYOUT2
MicroProcessor
Page 02-08
AP-93 Series Chassis Front Speaker Off Circuit
(See also Main and Terminal Mute Circuit)
Front/PinP
Audio Control
PSU2
IS05
F. Spk Off
Ft. Spk. Off 2 5 I401
Q403 R411
D404 R412 11 Mute
C411 FRONT
R413 C412 L&R
PSU1 Audio
Output
Right Ft. Audio C441
R1 Out 15 14 2 R In
Left Ft. Audio
L1 Out 18 15 4 L In
D402 Q401 C442
R402
C401 Q402
R404
I001
SCL 3
SCL 3 16 4 58 SCL 3
SDA 3
SDA 3 17 5 57 SDA 3
Miss-Labeled
On Schematic
Microprocessor
SRS PWB Signal PWB
Page 02-09
POWER SUPPLY
INFORMATION
SECTION 3
POWER SUPPLY ON AND OFF (STAND-BY) OPERATION EXPLANATION
T he power supply in the AP-93 chassis works very similar to the previous models, with
only a few exceptions. This power supply runs all the time when the AC is applied. The
use of the power supply creating the A12V supply eliminates the need for a Stand-By trans-
former. The following explanation will describe the Turning ON and OFF of the projection
television.
T he Microprocessor generates the ON-OFF control signal as before, with the exception
that there is no Relay Driver. The schematic shows a relay driver Q003, however it is in
parentheses. This means that the component doesn’t exist in the set.
This On/Off control will perform the following :
• Turns on the regulation control signal
• Turns on the A5V and A9V regulator
• Turns on the Shut Down “Power Shorted” detection circuit
• Turns on the Horizontal Vcc supply to the Rainforest IC, I501
The Microprocessor outputs the On/Off control from Pin 35, to the PSD3 connector Pin 4.
(See Figure 1) The active state is On = High and Off = Low. The high for Power On is then
routed to Q908 and Q907. Q908 is turned On, removing the base bias for Q907. Q907 turns
off and removes D948 from the circuit of Pin 2 of I905 which is the regulation error voltage
feedback line for the regulator IC, I901.
The purpose of D948 during Stand-By, is to create a false feedback that artificially compen-
sates for the reduction in output voltage when the power supply switches to a lower frequency.
However, due to another factor, this doesn’t cause the power supply frequency to rise to maxi-
mum which will be described next.
W hen the power supply goes into Stand-By mode, the Horizontal Drive signal for de-
flection is shut off. This is accomplished by Q916 and Q917. The Low out produced
from the Power On/Off pin 35 of the Microprocessor is detected by the base of Q916. This
allows the collector voltage to go high. This action turns off Q917 which removes the B+
from its collector. The Collector of Q917 is connected to the Deflection B+ pin 22 of the
Rainforest IC, I501 via pin 3 of the PSD2 connector and Pin 13 of the PSI1 connector. This
action stop I501 from producing a horizontal deflection drive signal.
(Continued on page 2)
PAGE 03-01
POWER SUPPLY ON AND OFF (STAND-BY) OPERATION EXPLANATION
Signal PWB
I501
I001 A12V PSD2 PSI1 Rainforest IC
PSD3 To Horz.Drive
Power Q916 Q917 11.78V Transistor Q701
W hen the Horizontal deflection is defeated, the power supply no longer has a deflection
load. This low current demand is detected by the three resistors connected to the
source of the internal Switch MOS FET inside I901 via pin 2. Pin 4 of I901 is the over cur-
rent detection pin, however it is also the current demand sensing pin. When the current de-
mand is low due to horizontal defeat, pin 4 will be less that 1.4V and the internal frequency
will switch to 20Khz. This is caused by the Quasi Resonant circuit operation which is covered
in a Hi-Lite article.
This reduction of power supply frequency will move the frequency below the Bell of the
power supply transformer and all secondary voltages will reduce to approximately 1/2 of their
normal voltage.
Due to the fact that the power supply is still operating at 1/2 voltage output, the Green LEDs
used for visual trouble sensing will reduce in intensity, however they will remain lit. With the
exception of the TV9V and TV5V regulator. Which are turned off in Stand By.
(Continued on page 3)
Deflection B+
Power Supply
60V 1 Cold Gnd. Hot Gnd. Driver & Output IC
Raw B+
I903 0.2V I901 1 150V
10.74V
2 2 Regulation 3 6 Freq. Control & R917
I905
Photocoupler Inhibit PC Line 2 R986
R987
4 0.1
3
each
D948
R909
D971
Normal Freq. 30 ~ 50Khz
R958
I001 Micro 10.18V Pin 4 > 1.4V = Normal
PSD3 0.59V Pin 4 < 1.4V = 20Khz.
Q908 Q907
Power 0.0V
35 4 R975
On/Off OFF = Lo
R960
Fig. 3
PAGE 03-02
POWER SUPPLY ON AND OFF (STAND-BY) OPERATION EXPLANATION
TV9V AND TV5V REGULATOR OPERATION IN STAND-BY:
(See Figure 4)
B oth of these ICs as well as the A12V regulator are DC to DC converters just like last
year. This is because of the wide range of input voltages from Stand-By to Normal op-
eration of the Power Supply.
The TV9V regulator (I912) and the TV5V regulator (I913) are shut off during Stand-By
mode. This is accomplished by Q906 and Q905. When the low for the power On/Off pin 35
of the Microprocessor is detected by Q906, it’s collector will go high. This action will turn
ON Q905 and its collector will go low. This will pull pin 5 of I912 and I913 low, turning off
the two DC to DC converters.
D uring Stand-By, all of the secondary voltages are reduced to approximately 50% of
their normal voltage. This could cause a potential problem with the Short Detection
circuits for shutdown. To avoid accidental shut down, Q906 also controls the activity of
Q905. During Stand-By, Q906 is turned off. This allows the Base of Q905 to be pulled up
which turns on Q905 and its collector voltage is low. Q918 is also turned off because its
base voltage is pulled low through D975. This prevents any pull-up voltage from appearing
on the emitter of Q913. The base of Q913 is connected to 6 Low Detection inputs, (See AP-
93 Power Supply Shut Down Circuit). When the power supply operates at 50%, the Short
Detection circuit could activate. By turning off Q913, no accidental shut down operation can
occur. For added protection, Q912 also prevents any Shut-Down voltage from reaching the
Gate of Q914, which is the Shut-Down SCR latch.
A9.65V
R937
7.29V Q905
I001 Micro D975
PSD3
Q906 7.29V Power/Deflection PWB
Power 0.0V R989 C965
35 4
On/Off R940 R990
OFF = Lo 0.52V
Q918 Q913 To Gate of
C945 R968 D956 Q914
0.22V
A5V
3.34V 0V Shutdown
R969
6 Shutdown Inputs,
2.6V SCR
Active Low C954
Q912
0V
0.1V
Fig. 5
PAGE 03-03
AP-93 SERIES "POWER ON & OFF" DIAGRAM
Signal PWB 31V
120V Def. B+
Raw B+
I001 R926 Cold Power Supply
150V
119.1V 1 Hot Gnd. Driver & Output IC
Microprocessor Gnd. from Primary
I903 0.2V I901 1
D971 D948
2 2 Regulation 3 6 Freq. Control & R917
VDD Power Photocoupler Inhibit PC Line 2
5V
Reset
On/Off Q907 I905 10.8V R986
R958 R987
11.1V 4
61 54 35 5.1V PSD3 3 Normal Freq. 30 ~ 50Khz 0.1
Regulator IC Pin 4 > 1.4V = Normal each
5.2V 5.2V Q908 0V Def. B+ Hi = pin 2 low
ON = Hi 0V Pin 4 < 1.4V = 20Khz. R909
0.7V Def. B+ Lo = pin 2 Hi
4 R957
OFF = Lo R960 I912
R034 31V 1 2 TV9V
C018 5 TV9V Reg IC 3
A7V
R937 2.5V 2.5V
3 Q905
0V
D975 5 I913 2 TV5V
I007
2 Q906 1 TV5V Reg IC 3
Reset 0V
0.7V R989 C965
1 R990
R940
3.1V
Power/Deflection PWB
Q918 Q913 R968
C945 2.6V D956 To Gate of Q914
A5V (Shutdown SCR)
4.6V 0V
I910 R969
6 Shutdown 2.6V
A12V Inputs,
C954
Q912 I501
1 Active Low 0V
L002 0.1V Rainforest IC
Q026 A12V Q917 PSD2 PSI1 Hoz. Out Def.B+
A5V
11.7V
1 To Horz.Drive 23 22
5.2V 11.8V Transistor Q701 1.5V 9V 9.1V
C064 R029 A12V R981 D974 R983
5.7V 11.1V 1 12
HVcc R566
D044 Q916 0V R982
R980
C065 D045 C544 C538
C962 3 13 D505
0.7V
9V
C964
Power/Deflection 0V t1 t2 t3 t4 t5
PWB
Page 03-04
Regulator
TV Singal Circuit TV+9V
TV9V : I912
Voltage Control
Switching Feedback +B : I905
Control I903 Regulator
Stand By : Q907 TV Singal Circuit TV+5V
I901 TV5V : I913
+B 120V
Protect
I902
D912: TV ON/OFF
Protect Red LED Mode Switch
AC Clock Q905, 6, Q908
I904
TV Main ON/OFF
Page 03-05
AC Clock ON = LO
60Hz OFF = Hi = RED L.E.D.
AP-93 (I901) POWER SUPPLY DRIVER
IC
STR-M6811A Internal Block Diagram
5 Vin Indicates Available only in STR-M5611A and STR-M6812A
D
FET
START
R1 1
REGULATOR DRIVE
Start Up
2
OVP R5
Over Voltage S
Protection Q1
Comp. 1
TSD 4
Thermal LATCH OCP 0.5 OCP-
Shutdown V INH
R2
3.1V
7 OSC INH 1.5
V
9.9V
Comp. 2
R4
Pin 7 SS Trigger C1
C4 C2
C3
R3
3 Gnd 6 Feed Back
Page 03-06
AP-93 POWER SUPPLY SHUTDOWN BLOCK DIAGRAM
22 SHUT DOWN INPUTS
Deflection B+ (120V) Deflection B+ (120V)
Excessive Current Det. Excessive Voltage Det.
I901
ShutDown Pin (7) I902 Q914
on Power Supply ShutDown ShutDown A12V
Driver & Photocoupler S.C.R. Loss Det.
Output IC
5V Short Det.
-M23V Shorted
AUDIO 22V Loss Det. I913 Det.
Short Det.
-M12V 12V Too
AUDIO 32V Loss Det. High Det.
Short Det.
Vert. 26V Shorted
TV9V Short Det. Too High (TV9V Reg.)
Det. I912 Det.
Signal PWB
TV12V PSD2
Short Det. X-RAY PROTECT "HV PROTECT"
From Deflection Trouble Mutes CRTs through
6
Detection Circuits MUTE Cirucit when
Q914's Gate is High
Excessive High Hi Volt Det.
Voltage Det. Loss Det.
12V Too
High Det.
Page 03-07
AP-93 POWER SUPPLY SHUTDOWN CIRCUIT
Deflection B+ (120V)
D929 R931 0.47 Excessive Current Det. Deflection B+
T901
15
120+
C929 119.1V 0.9V
R934 Deflection B+ (120V) To Flyback
5V R933 R932 Excessive Voltage Det.
Q903
R935 Osc. B+ & Run B+
R962 4.6V 118.5V D933
D931 I902 I901
11.5V Q909 11.9V 24.2V 24.2V
A12V 1 4 5 Osc B+
R963 D932 R916
0V 1.9V 1.9V
11.3V R948
A12V 2 3 7 Shut Down
D952
R950 0.1V 11.3V
A12V Loss "RED"
Det. Q914 D912
D957 R949 C943 RED LED
D959 Not On = Start Up B+ Missing R915 D960
HV Protect
A12V Too High Det. Normal Glow = Osc. B+ Present Mutes CRTs
BLINK= SHUTDOWN
Leaky Short Det. R971
Diode Det. D958
D956
D925 D942 D937
I909 (-M12V Reg) R968 D923 D921 D919
Q913
Shorted Det. R970 2.6V 0.1V D922 D936 D961
D963 D941 D924 D920
5V Short Det. Q912
2.6V R920 R921
R969
D976 R922 R923
Audio 22V
3.1V Vert.
Short Det.
A5V 27V -M23V 26V 12V -M12V 12V TV9V
D945
AUDIO 32V R989 I913 Vert. 26V
Short Det.
4.6V Q918 -M23V -M12V 12V Too I912 (TV9V Reg.) X-Ray
Shorted Too High
D944 Loss Det. Loss Det. High Det. Shorted Det. Protect
R990 Det. Det.
TV9V Short Det.
A5V X-RAY PROTECT FROM DEFLECTION CIRCUIT
D943
Page 03-08
R647
D709 R716
Q710 T702
D725 R737
Heater Voltage R715 D712 Flyback
Loss Detection. D709 H Heater
No Heater = Lose Hi Excessive High
Voltage Detection Voltage Detection D721 C731 10
R753
Page 03-09
0V D723
6.2V R750 R751
TV9V D724
Q710
4.7V R752
C740
D722 Deflection PWB
AP-93 CHASSIS L.E.D. (VISUAL TROUBLE DETECTION) DIODES
8 GREEN L.E.D.s and 1 RED L.E.D.
(9 Total L.E.Ds. for visual trouble sensing observation)
R945
R918 R919 R974 R943 R991 R972 R972
R944
8 GREEN L.E.D.s
SECTION 4
AP-93 CHASSIS VIDEO BLOCK DIAGRAM
Signal PWB Signal PWB PINP
Tuner (2) for PinP only. PinP White Balance Adj.
Tuner (2) uses Auto Programming info from Antenna 1 only. PinP R
PCB R0M4
TWO PinP R 5
PCC PinP G
Tuner 2 T u n e r
Luminance
16 IN1A PSI2 1 of 2
cR Y QY58~60 Out B 5 51 V/I In
5 11 IN1B
PinP R
cB QY61~63 IN2B 9 6 V/I Out 35 1
3 9 IN1C
IN2C 8 5 U/Q Out PinP G
QA80 2 7 12 Switch 34 2 To PinP
Q032 PinP B Adjust
PCD Control 33 3
13
I001 48 17 PinP YS1
(See Above)
33 Micro Processor YUVSW YS1 32 4
PSI2 2 of 2 Q509 Q505
Q009
Comp Det
SCL 3
1
28 60 1 28 Chroma 13 12
PCB SCL 3 Communications,
Controls the following: 59 2 SDA 3 27 SDA BPF Q512 Luminance
6 58 Brightness, Contrast,
PSI1 Luma 15 16
7 57 Auto Color,
To CRT PWB
PY1
SDA 3 Sharpness, Color, Tint, Q515
R Q504 Chroma
Shoot Balance, TCPE, 3 43
Page 04-01
To IY01
Selector IC emphisist, YNR, & Q516 CW 1 8
CNR. G 4 42
(See Above)
Q517
B 5 41 Signal Sub PWB Signal PWB
AP-93 SYNC CIRCUIT
Signal PWB 1 of 4
I001 H Sync Signal PWB 4 of 4 Terminal PWB
39 PCB
Main 55 V Sync Q005 Tuner 1 Q101
IY01
Micro 18 1 47
U101 Selector
40 SD TV
PCC IC
Q004 Q006 Q102
Tuner 2
I102 H Sync U102
23 8 33
28 EV
OSD TV-V2
V Sync Signal PWB 1 of 4
Micro 29
QY11 PinP Out
I008 PinP V
Q001 5 15 23 V-Out 3
3 Sync 2 Sync QY51
7 N/C 10 43 Y-Out
Signal Sub PWB
PSI2 Q002
Q513 QY54 QY10
I501 17 14
Sync Switch
15 11 9 PCD
Y Out
Rain- Sync In
forest Signal PWB 3 of 4
PSI1 3D- 9 Y/S-Y
IC V Drive I301 Signal PWB
31 10 Y Y/C V/S-Y
4 of 4
5 11
FBP In 3 V/S-Y
U301
25 14 7
Vertical Output I.C.
PSD2
U002 I601
Signal PWB 3 of 4 10 2 V Drive
V Drive
V
8 11 9 Pump Up
V.Blk
PinP
Signal PWB 3 of 4
Unit T702 Flyback
Q705 E701
H H.Blk 200
9 2
Page 04-02
Signal PWB 3 of 4
Deflection PWB
AP-93 HORIZONTAL & VERTICAL BLANKING CIRCUIT
I601
To Digital Vertical Blanking Creation Circuit
Convergence Circuit Drive Pump Up Vcc
PSD2
2 9 13
From PSI1 V.Drive
pin 10
10 C614
R649
V.Blk
To U002 11
PinP V.Blk V. Blk D611
R645
Vertical +26V
Blanking R633 0.68
24V P/P
R634 C612
H.Blk To Sweep
2 Loss Det.
12V
Horizontal Blanking Creation Circuit
Q712
R722
R723 D720 D778
Q705 R725
T702
Flyback
C771
11.6V P/P
C722 E701
R771 R772 D715 To Anode
200
High
Q711
R721
R770
D717 R728
4
As Brightness goes Up, ABL Voltage goes Down. (Inverse Proportional)
AP-93 HORIZONTAL & VERTICAL SWEEP LOSS DETECTION CIRCUIT
12V
RN05
Vertical RN03 RN04
Blanking
From DN01
Pin 9 I601 CN01 QN01 QN02
RN01
V. Blk. CN02 DN02
RN02 DN03
24V P/P
12V 12V
RN07
RN10 QN04
RN09
Horizontal
Blanking DN04
CN03 RN06
From DN05
Q705 Emitter QN03
RN08
CN04 QN05
DN06 Prevents
H. Blk.
RN11 CRT Burn
RN13 DN11
RN12 PSD2
6 H.V.
11.6V P/P
PROTECT
DN10 DN09
From the Power Supply
Shut Down Line going to R971 D960 To Signal 01/04
the gate of the Shut RN16 Grid F9
Down SCR Q914 Base Q015
0V "V MUTE"
QN06
8.57V
From I904 Pin 3 RN14 RN15 8.57V
AC Photo Coupler
10V P/
P
CN05
DN07
DN08 9.72V
ACK 5V
RN18
CN06 RN17
Page 04-05
DIGITAL
CONVERGENCE
INFORMATION
SECTION 5
AP-93 DIGITAL CONVERGENCE
"MAGIC FOCUS" SENSOR LOCATION
FRONT VIEW
Page 05-01
AP-93 CHASSIS "DIGITAL CONVERGENCE" INTERCONNECTION CIRCUIT DIAGRAM
D/H OSD Sel PY1
HB HB
I105 PSI1 I501
I102 OSD B 42 10 B 8 BTX
Q111
6 OSD B
Q517
I001 Dig OSD B BTX
37 Rainforest 41 5 B
9
1 HG
To CRTs
HG
OSD OSD G 43 4 G
Q112 Q516
Dig OSD G 6 GTX 5 OSD G 38 42 4 G
Up 32 Main Up 5 GTX
28 HR HR Q113 Q515
OSD R 44 1
Dig OSD R
R 3 RTX 4 OSD R 39 43 3 R
2 RTX
Q027 Dig OSD B
Dig OSD G
PDG
3 1 2 OSD R
3 2 6 7 9
VD RV
QM01
2 3
IR-In
8 + - PCR
IR
QK0 PDC 6 7
OSDG 7 2
Out 4 9 BV
1 8 4 CYV+
ADJ
+27P +33V
S0 S0
12 9
IK02 2 +27V
3
Deflection PWB Deflection PWB
AP-93 SERIES CHASSIS "CLU-615MP" REMOTE CONTROL
REMOTE PERSONALITY WHILE IN THE
DIGITAL CONVERGENCE ADJUSTMENT MODE "D.C.A.M.
Page 05-03
AUDIO
INFORMATION
SECTION 6
AP-93 SERIES CHASSIS AUDIO SIGNAL PATH (Main & Terminal)
L
R Monitor Out (Fixed)
Aux Inputs
1R 10 PinP 24 13 9
QA04 QA03 Terminal PWB
IA02 2L 14 Audio 22 R 12
PinP Right
8
10 (Switch Control) AVX 2
2R 16
QA79 QA09 FL Front Left
15
13 PL PinP Left PinP Left
Out L
14 6 17
PinP Right
7 18
Transmitter
Out 9 (Switch Control)
F L Out
4 15
Spk PR Front Left Main Audio F R Out
2 14
2 12 Front Right Q403 D404
Front Speaker Off
11 D405 Signal PWB
V Mute
AP-93 SERIES CHASSIS SURROUND AUDIO SIGNAL PATH
PSU2
Center Center
3
HiFi (R) L Rear Left to Transmitter Out Circuit HiFi (R) L
7
HiFi (R) R Rear Right to Transmitter Out Circuit HiFi (R) R
8
L-R Amp Rear & Center Audio Control
(Rear) Rear Rear
IS03 S Out 13 6 7 32 IS10 QS23
R Mix Out (Off/Matrix/Hall) R In R2 Out 13
15 IS04 SS M/HM/H L In Rear
L Mix Out (Off/Matrix/Hall) QS22
Passive L2 Out
16 1 20
Decoder (Rear) Rear
S In 10 35 IS01 34 24 9
S Out Center Out Center L R
23 10
See Audio Signal Path (Main & Terminal)
PSU1 L in 8 9 R in
Pro 5 R1 Out 15
Center
FL M/H Lin 1 32 FR M/H Rin
Center
Logic Rear R In 30
L
IS05
IS12 IS02 1 L 9 Decoder 37 L Out 18 28
11 1 3 3
L/R
3 24 Ft L Out
R Perfect R R Out See
5 Front/ 9 Ft R Out
Rear L In
12 10 Volume 8 5 Buffer 7 10 36
L1 Out
Graphic
PinP EQ
2 4
PinP Left PinP L In 23 Ft L In
9 28 Audio Circuit IS11
PinP Right PinP R In Ft R In
8 30 Control 10 IG01~15 Rear Audio
PinP Left L2 Out (PinP L Out) Front L Output
17 20 18 JS01
PinP Right R2 Out (PinP R Out) 12 7
18 Front R Rear R Out
13 15 2
PinP Audio, Right and Left
to Transmitter Out circuit Rear L Out
IS09 1
CS79
Sub Woofer Audio IS08 Rear Audio
16 7 1 7 3
Sub Woofer Output Jack
Front Right and Left to Volume Control
5 1 CS78
Transmitter Out circuit & Amp
Sub Woofer Buffer
HiFi Ft Right 3
2
HiFi Ft Left Control
1
Page 06-02
QS24
F L Out
15
QS25
F R Out
14
AP-93 Series Chassis Front Speaker Off Circuit
(See also Main and Terminal Mute Circuit)
Front/PinP
Audio Control
SCL 3
SCL 3 16 4 58 SCL 3
SDA 3
SDA 3 17 5 57 SDA 3
I001
Miss-Labeled
On Schematic
Microprocessor
SRS PWB Signal PWB
Page 06-03
AP-93 FRONT AUDIO RIGHT & LEFT
GRAPHIC EQUALIZER CIRCUIT
For continuation of Front Left and Right Audio signal flow, see AP-93 Series Chassis Surround
Audio Signal Path Diagram (Surround and Main/Terminal)
IS05
FR In 10
FL In 23
2 -
FL In 1
FL Out 24 3 + FL GEQ
IG09 Front Graphic Equalizer
FR In Buffer
FR Out 9 5 + FR GEQ
7
6 -
Determines the Frequency Characteristics
GEQ Clock Data controled by Customers OSD Menu.
"See Microprocessor Data Communication
17 18 Path" Diagram for more details.
IG01 10KHz
4 IG08
Front EQ 4.5KHz
5 IG07
2 IN1L 2KHz
6 IG06
IN2L 1KHz
3 7 IG05
Left Left EQ 400Hz
8 IG04
Front 150Hz
9 IG03
60Hz
10 IG02
60Hz
19
150Hz
20
Right Right EQ 400Hz
Front 21
IN2R 1KHz
26 22
2KHz
27 IN1R 23
4.5KHz
24
10KHz
25
Page 06-04
AP-93 SERIES CHASSIS CENTER GRAPHIC EQUALIZER CIRCUIT
AND REAR (SURROUND) AUDIO OUTPUT CIRCUIT
3
Center
IS01
2 C GEQ IS10
Pro-Logic Center -
1 5 Rear/Center
Decoder 34 3
+
IG10 4 10KHz
IG15
Center 5
4.5KHz
2 IN1L
EQ 2KHz IG14
6
Center 1KHz
3 7
IN2L
8 400Hz IG13
150Hz
9
10
60Hz IG12
Rear (Surround)
10
IS03
Dolby S (Rear) IS04 S IS10 R2 Out
QS23
Passive 13 6 Surround 7 32 Rear/Center 13
Decoder Buffer Audio Control (Rear)
S
2 of 2 QS22
1 20
L2 Out
JS01 Rear
Left IS11
1 7 4
To Rear
Rear Rear Audio
Speakers Right
2 12
Output IC 2
SECTION 7
AP93 DEFLECTION BLOCK DIAGRAM
V. Parabola
Distortion
H.D.
Control
QF10, QF11
30KV To Anode of CRTs
12KV To Focus Pack
Horz. Drive Horz. Out
Flyback
I701 Q777 2SC5124
T702
Bootstrap High Voltage
Dynamic Focus Out Stability
H. Parabola
H. Blk. QF06, QF07, ABL
(2SC4686A) QF08
120V
Focus 12KV
Pack ABL
VM Sensors
Focus 30KV
RGB
Screens R
Sensor
Digital Convergence Out G Distribution
Convergence IK04, IK05 PWB
Unit STK392-110
CY to B
Conv. Yokes
Page 07-01
AP-93 SIDE PINCUSHION CIRCUIT DIAGRAM
12V
R625 R627
QN05 Q607
A Size From DCU C606
Vertical Pulse
R626 Heater Pulse
Hi Voltage Fluctuations R606 R607
C603 R621
R602
12V Q602 R610
R603 R616
H.Size Q603
R612
R615
R618
R609 12V
ABL Fluctuations R617
C605
D604
120V B+
12V R614 R613 - 5
7
D603 Q604 + 6
Q606 12V 8 I602
L601 C609 R652 -
R622 2
R624 1 C601
+ 3
R620
R620 Q602 4
D603
C608
C602
Collector of
Horizontal Output
Q777
L705
Page 07-02
DC Changes Size
Waveform Corrects Pincushion
C729