A novel high energetic efficiency multilevel topology

with reduced impact on supply network

Youssef OUNEJJAR, Kamal AL-HADDAD (IEEE Fellow Member)

ÉCOL E D E T ECHNOLOG I E SUP ÉRIEURE

Canada Research chair in Electric Energy Conversion and Power Electronics
Département de génie électrique,
1100, rue Notre-Dame Ouest,
Montréal (Québec) H3C 1K3
E-mail : youssef.ounejjar.1@ens.etsmtl.ca
E-mail : Kamal.Al-Haddad@etsmtl.ca

Abstract- In this paper, authors propose a novel
competitive multilevel topology. It combines advantages
of the flying capacitor and the cascaded H-bridge
topologies. It presents several advantages which will be
thereafter detailed. The proposed topology is
characterized by a reduced impact on the utility supply,
a good energetic efficiency and a small number of
switches and passive components. It presents also the
possibility and the simplicity of changing the number of
voltage levels only by acting on-line on the ratio of the
desired output voltages. An average model of the
proposed topology is performed and the control strategy
is designed to draw a nearly sinusoidal current in order
to avoid the use of filters. The modeling and control
strategy of the proposed topology were verified by
simulation.
Index terms: multilevel converters, harmonics, unit power
factor operation, average model
I. INTRODUCTION
Due to their ability to synthesize waveforms with a better
harmonic spectrum and attain higher voltages, and to
overcome the limited semiconductor voltage and current
ratings, multi-level inverters are receiving an increasing
attention in the past few years[1].
By generating high voltage with low harmonics contents
and reducing the switches stress, multilevel converters
permit an effective high power exchange.
Traditional multilevel converters like neutral point
converters NPC proposed by Nabae, Takahashi and Akagi
[2] and flying capacitors converters FCC proposed by
Meynard and Foch [3] present many drawbacks if the
number of voltage levels grows. In fact, the number of
switches, diodes and capacitors grows excessively resulting
on an expensive cost and their implementation becomes
very complicated.
For inverter operation, when number of desired voltage
level exceeds three, cascaded H-bridge inverters topology
becomes the optimal solution. This is due to their small
number of switches and passive components. However, this
topology requires independent and isolated DC voltage
sources, which leads to the use of transformers.
In the last few years, many optimizations have been
presented to improve their efficiency [4-10]. In these
papers, authors propose multilevel inverters synthesizing a
large number of levels with improved output waveforms
characterized by a low distortion and smaller filter size.
In this paper, we propose a novel multilevel topology which
can be classified as a mid-point between the flying capacitor
and the cascaded H-bridge inverters topologies. Compared
to these topologies, the proposed one uses small number of
switches. Moreover, in inverter mode, it permits to reduce
the number of transformers. In rectifier mode, it gives
multiple output voltages which are independents, so we can
use the first as a DC bus and the other one as an auxiliary
output voltage. The impact of the proposed topology on the
utility supply is very limited. With this topology,
modulation frequency can be very low which improves the
energetic efficiency of the installation. The proposed
topology modeling is performed using an average approach.
The control strategy is designed to produce a nearly
sinusoidal current and to alleviate the harmonic content of
the output voltage. The filters can thus be smaller or even
eliminated.
II. THE PROPOSED TOPOLOGY
A topological optimization of the classic cascaded H-bridge
inverters results on a new competitive topology which use
small number of passive and active components and avoid
the use of transformers (figure1).

k,((( 
A comparison of seven levels classic converters topologies ⎧ 1 if Ti is ON
and the proposed one is given in table1. The seven levels Si = ⎨ (1)
neutral point converter NPC and the flying capacitors ⎩0 if Ti is OFF
converter FCC one, use a very high number of switches, From figure 4, we can write:
diodes, and capacitors, whereas the classic cascaded H-
bridge inverters topology use only eight switches. The ⎧V Aa1 = −(1 − S1).V 1
⎪
proposed topology, however, uses only six switches. ⎨V a1a 2 = (1 − S 2)(V 1 − V 2) (2)
⎪V
⎩ a2N = (1 − S 3).V 2
TABLE 1
Comparison of seven levels classic topologies and the proposed one We can write also:
NPC FCC Cascaded H- Proposed
⎧i1 = S1.is
⎪
bridge topology ⎨i 2 = S 2.is (3)
Capacitors 6 6 2 2 ⎪i3 = S 3.is
⎩
Clamping 30 0 0 0
diodes
Switches 12 12 8 6
Adding VAa1, Va1a2 and Va2N gives:
VAN =VAa1 +Va1a2 +Va2N = (S2 − S1).V1+ (S3− S2).V2 (4)
Moreover, the proposed topology presents other important
advantage: the switch which must support the highest Applying Kirchhoff’s Current Law (KCL) to the node a1
voltage operates at the lowest switching frequency, and gives:
vice-versa. This reduces the switches stress and improves i1 = i 2 + ic1 + I 1 (5)
the performance of the converter.
Where ic1 and I1 are the C1 capacitor current and the C1
capacitor load current respectively.
dV 1
ic1 = C1. = i1 − i 2 − I 1 (6)
dt
Thus, we can write:
dV 1 (S1 − S 2).is I1
= − (7)
dt C1 C1
By the same, applying Kirchhoff’s Current Law (KCL) to
the node a2 gives:
i 2 = i3 + ic 2 + I 2 (8)

So we can conclude:
dV 2 (S 2 − S 3).is I 2
= − (9)
dt C2 C2
Applying Kirchhoff’s Voltage Law to the converter input
loop gives:
dis
V AN = − R s .is − L s + es (10)
dt
Fig. 1: The classic cascaded H-bridge inverters and the proposed topology
By comparing (4) and (10), we can conclude:
III. MODELING AND CONTROL DESIGN OF THE PROPOSED
TOPOLOGY dis es − R.s is − (S 2 − S1).V 1 − (S 3 − S 2 ).V 2 (11)
=
dt Ls
Ti and Ti′ switches operate complementarily. Let S i be a
switching function of Ti switch where i={1, 2, 3}. S i is Let d1, d2 and d3 be duty cycles of switches T1, T2 and T3
defined by: respectively. Duty cycles are defined by:

k,((( 
 Fig. 2: Zoom on line current

1 Ts
Ts ∫0
d1 = S1dt Fig. 3: Average model of the proposed topology

1 Ts Thus, the average model of the proposed topology is shown

Ts ∫0
d2 = S 2dt ( 12)
in figure 3.
1 Ts
Ts ∫0
d3 = S 3dt By considering the duty cycles as inputs:

Ts is the switching period. u1=d1, u2=d2 and u3=d3

From figure 2 we can write: The model of the source-converter-load system can be
written by the following matrix equation:
1 Ts 1 1 ⎛ I −I ⎞
is.dt = (Ts .I1) + ⎜Ts . 2 1 ⎟
Ts ∫0
I= (13) dX
Ts Ts ⎝ 2 ⎠ = F ( X ) + G ( X ).U + C (16)
dt
If we consider the two following areas:
Where:
A1 = Ts .I1 is the blue shaded area ⎡ es ⎤
⎡ − R s x1 ⎤ ⎢L ⎥
I 2 − I1 ⎡ x1⎤ ⎢ L ⎥ ⎢ s ⎥ ⎡u1 ⎤
A2 = Ts . is the red shaded area ⎢ ⎥ ⎢ s ⎥ - I1 ⎥
2 X = ⎢ x 2⎥, F(X) = ⎢ 0 ⎥, C = ⎢ , U = ⎢⎢u 2 ⎥⎥
⎢ C1 ⎥
We can consider that A1>>A2. So we can assume the line ⎢⎣ x3⎥⎦ ⎢ 0 ⎥ ⎢- I ⎥ ⎢⎣u 3 ⎥⎦
current to be constant in a switching period. Thus, we can ⎢ ⎥ ⎢ 2⎥
conclude that: ⎣ ⎦ ⎢⎣ C2 ⎥⎦
Ts Ts
1 is
Ts ∫ S i .i s .dt = Ts ∫ S i .dt = i s .d i (14) ⎡ x2 x3 − x 2 − x3 ⎤
0 0 ⎢L Ls L s ⎥⎥
⎢ s
Let x1, x2 and x3 be the state variables of the source- x − x1
and G(X) = ⎢ 1 0 ⎥
converter-load system defined by: ⎢ C1 C1 ⎥
⎢ x1 − x1 ⎥
⎢ 0 ⎥
x1 = i s , x 2 = V1 and x 3 = V2 ⎢⎣ C2 C 2 ⎥⎦

Then, the system state equation is given by: The determinant of matrix G is null, then G is not invertible.
Noting that state variables x2 and x3 serve to generate x1
⎧ dx1 es − R.s x1 − (d 2 − d1).x2 − (d 3 − d 2).x3 reference, then we can exclude one of them, and with the
⎪ dt = Ls
⎪ following supposition, the problem is solved:
⎪ dx2 (d1 − d 2).x1 I1 (15)
⎨ = -
u1 + u 2 + u 3 = 1.5 (17)
⎪ dt C1 C1
⎪ dx3 = (d 2 − d 3).x1 - I 2
⎪ dt C2 C2 Inputs u1, u2 and u3 vary between 0 and 1, then we have
⎩
chosen to center them in their variation intervals. This
justifies our proposition in equation (17).

k,((( 
Applying a PI linear control method to each subsystem IV. SIMULATION RESULTS
gives:

⎛ K ⎞ The proposed control strategy offers the possibility of

( )
u11 = − x1ref − x1 ⎜⎜ K p11 + i11 ⎟⎟
s ⎠
changing the number of voltage levels simply by varying the
⎝ x3ref 1
⎛ K ⎞ ratio k = . If k = , then the number of voltage levels
( )
u 21 = − x 2 ref − x 2 ⎜⎜ K p 21 + i 21 ⎟⎟
s ⎠
(18) x 2 ref 2
⎝ 1
⎛ K ⎞ is 5, however, if k = , the number of voltage levels
(
u 31 = − x 3ref )
− x3 ⎜⎜ K p 31 + i 31 ⎟⎟
s ⎠
3
⎝ becomes 7.
The reference of the variable x2 is the desired DC link In order to reduce switching losses, we chose to simulate
voltage, whereas, x3 reference is the third of x2 reference. with a very low switching frequency which is just ten times
x1 reference is the sum of u21 and u31. source frequency. Simulation parameters are:
Finally, the input vector is given by: fs= 600Hz : switching frequency
Ls=3mH: line inductance
⎡ x 2 + x3 −1 1 ⎤ ⎡u + Rs x1 − es ⎤ e s = 120 2 sin (ωt ) : source voltage
⎢ 3x x ⎢ 11 Ls ⎥⎥
3x 2 3 ⎥⎥ ⎢
⎡ u1 ⎤ ⎢ 1 3
I
⎢u ⎥ = ⎢ x − 2x3 2 1 ⎥ ⎢ u31 + 2 ⎥ Simulation was performed in Matlab Simulink environment
⎢ 2 ⎥ ⎢ 3x x ⎢ C 2 ⎥
3⎥⎢
(19) using the Simpowersystem toolbox.
3x 2 ⎥
⎢⎣u3 ⎥⎦ ⎢ 1 2 ⎥
⎢ − 2 x 2 − x3 −1 1 ⎥⎢ ⎥ In order to verify the system dynamics, we change the DC
⎢ 1.5 ⎥
⎢ 3x x 3x 2 3⎦⎢⎥ link voltage reference at time 4s from 200V to 250V.
⎣ 1 2
⎣ ⎦⎥
The upper capacitor load is changed at time 2s from 25Ω to
15Ω, whereas the lower capacitor load is changed at time 6s
from 50Ω to 25Ω.
1
A. Five level rectifier operation ( k =
)
2
The auxiliary voltage reference is controlled to be the half
of the DC bus voltage.

Figure 5 shows a very good dynamic response of the output

voltages which are very smooth.

Figure 6 shows the rectifier input voltage which is

constituted from five levels. This reduces clearly the
harmonic contents compared to three level topologies.

Fig. 5. DC link and auxiliary output voltage

Fig. 4: Proposed control strategy

k,((( 
 Fig. 6. Rectifier input voltage

1
B. Seven level rectifier operation ( k = )
3
The proposed topology presents the possibility of changing
the number of voltage levels from five to seven, or vice-
x3ref
versa, only by acting on the ratio k = . This is obtained
x 2 ref
x 2 ref x 2ref
when decreasing the auxiliary voltage from . to
2 3
The auxiliary voltage reference is now controlled to be the
third of the DC bus voltage. Simulation was made with the
same parameters of section A. Fig. 9: source voltage and line current before and after load change

Figure 7 shows a very good dynamic response. Output

voltages ripples are very small.

Fig. 10: Zoom on the sum of duty cycles (condition of equation 17)

Fig. 7. DC link and auxiliary output voltage

Fig. 11a: Harmonic contents of line current before load change

Fig. 8. Rectifier input voltage

k,((( 

Fig. 11b: Harmonic contents of line current after load change
Figure 8 shows the rectifier input voltage which is now
constituted from seven levels. Thus, harmonic contents is
improved compared to section A.
Line current and source voltage are in phase even when load
and voltage reference change severely (see fig. 9). So the
proposed control strategy permits a unit power factor
operation.
The supposition of equation (17) is perfectly verified. In
fact, the sum of duty cycles always remains around 1.5 even
under severe output voltage and load variations (see fig. 10).
Figures 11.a and 11.b show very low line current harmonic
contents (as low as 1.53%). This shows that line current is
perfectly sinusoidal. Harmonics are centered on multiples of
the modulation frequency which is just ten times the utility
supply frequency.
V. CONCLUSION
The proposed topology associated to the proposed control
strategy permits a very high energetic efficiency. Even with
a very low modulation frequency, line current is perfectly
sinusoidal and output voltages are very smooth. Capacitors
loads are very independent and can change freely.
The proposed converter and its control strategy permit the
reduction or even the elimination of filters which are very
expensive and affect the energetic efficiency of the
installation.
The proposed topology is very competitive. It combines
advantages of flying capacitor and cascaded H-bridge
topologies. Controlled by the proposed strategy, it permits
the reduction of the impact on electrical network to almost
1% with a very high energetic efficiency through a very low
modulation frequency.
k,(((
The proposed topology offers:
1- Unit power factor operation
2- Sinusoidal line current due to very low harmonic
contents
3- Increase of energetic efficiency due to the
possibility of using very low modulation frequency
4- Possibility and simplicity of changing the number
of voltage level
5- Reduced passive and active components
6- Reduced stress and dimensioning of semi-
conductors
7- Very good dynamics of the output voltages even
under unbalanced loads
Reduction or even elimination of passive and active filters
which reduce the cost of the installation
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