Low Power Trends and

Methodology
Godwin Maben

Predictable Success
 Agenda

• Introduction
• Summary of Low Power Techniques
 Designer’s Arsenal

• Details on each Technique

 Technology Highlights
 Advantages/Trade-Offs
 Challenges

• Synopsys Low Power Flow Summary

© 2008 Synopsys, Inc. (2)

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 Reasons for Low Power Demand
Source: Intel

It’s all about

battery life
Leakage Power

Dynamic Power

250nm180nm130nm 90nm 65nm 45nm

© 2008 Synopsys, Inc. (3)
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 Reasons for Low Power Demand

60%

75%
Application Driven Technology Driven

40%
48%
50% 30%
41%
26%
21%
22% 20%
25%
13% 10% 10%

1% 1% 1%
0% 0%
Consumer Communications Computer/ Other >250nm 250nm 180nm 130nm 90nm 65nm 45nm 32nm
Peripherals

2004 2006 2007 Last Current Next

Source: SNUG 2007

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 Summary of Low Power Techniques
(Designer’s Arsenal)

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 Factors Governing Power
t


E  ( VDD I leak  CV 2 DD fc)dt
0

Total Power
Total Power
Dissipation
Dissipation

t t

 CV
Static Power DynamicPower
Power
 VDD I leak dt
Static Power Dynamic 2
DD f c dt
Dissipation
Dissipation Dissipation
Dissipation
0 0

Ileak Minimize Iswitch by:

Minimize Ileak by: Iswitch  Reducing operating voltage
 Reducing operating voltage  Less switching cap
 Fewer leaking transistors  Less switching activity

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 Basic Low Power Techniques
Summary
16 bit 64 bit
Clock Gating Ripple 90 366
D Q

FF CLA 100 405

EN
LT
Carry 108 437
Skip
CLK ICG
Carry 161 711
Select
Carry 218 1323
Save
a a
b c
c f Multi-Threshold
-

Leakage Current
b Low VTH
b c
Nominal VTH
d d High VTH

Delay

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 Advanced Low Power Techniques
Summary

SLEEP

Virtual VDD

1.0V

0.7V 0.8V Virtual VSS

nSLEEP

Multi-Voltage (MV) Power Gating

VDDB
A Z
A Z

VSSB

Non minimum size gate lengths VTCMOS Stack Effect

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 Details on each Technique

• Clock Gating
 Basic Understanding
 Advantages
 Concerns in the flow

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 Understanding Clock Gating

Q D Q
D
FF FF
EN FF EN
LT

CLK
CLK ICG

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 Clock Gating Flow Challenges

• Enable Timing
• Insertion delay increase
 Impact on OCV

• Peak Power during ON/OFF of clock

 IR drop as well

• Verification Impact

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 Managing Enable Timing

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 Clock Gating Impact on Verification

• RTL functional Simulation

 None

• Gate level Simulation

Reset
Q D
“0/1”
D
FF FF
EN “X”
LT

CLK ICG
“0/1”
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 Details on each Technique

• Multi-Threshold Leakage Optimization

 Basic Understanding
 Advantages
 Concerns in the flow

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 Understanding Multi Threshold

• Multiple Threshold Cells

Vdd 0.9v
Vdd 0.9v
Vth 0.22v
Vth 0.3v

16ps 10ps

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 Multi-Threshold Flow Challenges

• Looking at a different view of

the problem, optimizations
push towards zero-slack

• High-Vt cells tend to be

weaker and can be more
susceptible to variability

-ve slack +ve slack

Slack
Power critical
range

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 Multi-Threshold Flow Challenges
• Implant Spacing
Violations
• Min Width Violations
• Chip Finishing
requires Proper filler
Cell Insertion

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 Details on each Technique

• Power Gating
 Basic Understanding
 Advantages
 Concerns in the flow

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 Understanding Power Gating
VDDG

Switch Fabric

ISO
Switch Fabric

Gating Power Gated Always On

Control Block Block

Switch Fabric

VSS

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 Architectural Tradeoffs

• Amount of leakage power savings that is

possible
• Entry and exit time penalties incurred
• Energy dissipated entering and leaving such
leakage saving modes

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 Activity Profile for Power Gating

WAKE SLEEP WAKE SLEEP

SLEEP
Power

Dynamic Power Dynamic Power Dynamic Power

Activity “X” Activity “Y” Activity “Z”

Leakage Power
Leakage Power
Activity “X” Leakage Power
Activity “Y”
Leakage Power Leakage Power Activity “Z”
Power Gated Power Gated

TIME

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 Realistic Profile for Power Gating

WAKE SLEEP WAKE SLEEP

SLEEP
Power

Dynamic Power Dynamic Power Dynamic Power

Activity “X” Activity “Y” Activity “Z”

Leakage Power Leakage Power

Activity “X” Leakage Power
Activity “Y” Activity “Z”
Leakage Power Leakage Power
Power Gated Power Gated

TIME

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 Architectural Tradeoffs
• Gate VDD or
VSS?
• Retention
Mechanism

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Predictable Success
 Power Gating Flow Challenges
• Functional Verification Clock wiggling while
power-gated

Rail with Standby

Rail ramp-down value (0.6 volts)

Rail ramp-up

Restore

RETENTION Rail

Island Power-gated Save Registers RESTORED

© 2008 Synopsys, Inc. (24)
(Z)
Predictable Success
 Power Gating Sequence/Coverage

Voltage States: 8/8

Logical States: 2/3

Is the wakeup/shutdown
sequence correct ?

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 Power Gating Flow Challenges
• Logic Synthesis
VDD
OFF VDD on/off VDD_BACKUP

GATE X EN
ISO
Active
Logic
CP
VSS D
SI
RR Q
save SE
LD
Active RS

Logic restore
Shut
Down
Insert Isolation Cell Insert Retention Register
Hookup Retention Register

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Predictable Success
 Power Planning the Switches
# PWR
MAXIR Area SWITCHE X_INC Y_INC
(mV) (%) Resistance S R R LIB_CEL_NAME

37.2 0.4 650.0 328.0 26.3 3.6 SXXZZYX8L

42.7 0.3 1300.0 328.0 26.3 3.6 SXXZZYX4L

43.6 0.2 650.0 164.0 26.3 7.2 SXXZZYX8L

53.2 0.2 2600.0 328.0 26.3 3.6 SXXZZYX2L

55.3 0.2 1300.0 164.0 26.3 7.2 SXXZZYX4L

53.2
72.5 0.2 650.0 164.0 52.6 3.6 SXXZZYX8L

39.9

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Predictable Success
 IR-Drop Management
Turn On All Switches at Once
Limit the voltage
drop across the switch
NSLEEP
VDD
VDD

VVDD

VVDD
NSLEEP IN NOT_IN
Power-up Normal - Power-on

VSS Sequentially Turn On Switches

NSLEEP t0 t1 t2
Volts
VDD

Time Power-up Normal - Power-on

T VVDD
T- T+

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 Details on each Technique

• Multi-Voltage
 Basic Understanding
 Advantages
 Concerns in the flow

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 Multi-Voltage Design Style

• Static Voltage
• Multi-Level Voltage Scaling
• Dynamic Voltage and Frequency Scaling
• Adaptive Voltage Scaling

Voltage Island Voltage Island Voltage Island Voltage Island Voltage Island Voltage Island
A B A B Monitor A Monitor B
1.2 V, 350 MHz
Programmable

1.0 V, 250 MHz

Mode Voltage Mode Voltage
Voltage Island Control Regulators Control Regulators

C Voltage Island Voltage Island

1.5 V, 500 MHz C Monitor C

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 Understanding Multi-Voltage/Scaling

• Avoid completing tasks early – energy is wasted

• Use only enough energy required to complete task in time

Reduce Reduce Reduce

Voltage Voltage Voltage Voltage

Energy

Energy
Saved

Energy
Run Task in
Available Time
Run Task Slow
as Possible
Time
Task 1 Idle Task 2 Task 3
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Predictable Success
 CU requests
VCU to ramp
Voltage Scaling Facts down voltage
and reprograms
clock generator
• Voltage/Frequency are not changed at runtime to lower
Frequency
 Change of V/F is defined either through s/w or h/w
VCU Interrupts

0V

1.08V
Control CU when Target

Unit(CU) Voltage/Frequency changed in aReached
Voltage specific direction based on
the
to “amount of change”

0.76V
requests VCU
ramp up Voltage
 Wait till Voltage/Frequency are locked
CU programs clock
 Designs at run time will operate on locked
generator Frequency/Voltage
to maximum
Frequency

• Identify the various operating voltages under which

blocks will be operating at any point of time
• Do we have libraries characterized at these V points?

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Predictable Success
 Voltage Scaling Flow Challenges
• Accurately represent effects of dynamic change
in voltage values during simulation Vｄｓｔ
1.0V
Logic1
Vｓｒｃ VIH
0.6V
X

VIL
Logic0
0.0V

1.0v
Vsrc 0.6v
0.0v

SIM Hi Z
When Vsrc is between VIH X
And VIL propagate “X” Output

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Predictable Success
 Voltage Scaling Flow Challenges
• Synthesis
 Multi-Mode Optimization
 Optimal Voltage for Timing/Area/Power Optimization
 Level Shifter Optimization based on Mode

• Power Planning
 Optimal Power Grid
• Choose the appropriate Power Numbers

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 Voltage Scaling Flow Challenges

• Placement, CTS and Route

 Minimize Skew
 MCMM
 Placement of Level Shifters
 Temperature Inversion

Reduced Skew Across Large Skew Across

Domains Domains
3000 3000
# Flops

2000 VDDMax # Flops 2000

1000 VDDMin 1000
0 VDDMax 0
3.5 3.9 4.1 4.4 4.7 3.5 3.8 3.9 4 4.2 4.4 4.5

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Predictable Success
 Voltage Scaling Timing Challenges

• Functional or Performance Failures

Set-up Time Met
VDD=1.0 VDD=1.0 VDD=1.0 VDD=1.0

CLK CLK

D Q D Q
VDD=1.0 CLK
DFF DFF

CLK
Combinatorial
D Q
CLK
DFF
D Q
VDD=1.0
VDD=1.0 DFF

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Predictable Success
 Voltage Scaling Timing Challenges

• Functional or Performance Failures

VDD=1.2 VDD0.95 VDD=0.99 VDD=0.91

Set-up Time
Failure
D

CLK CLK

D Q D Q
VDD=1.0 CLK
DFF DFF

CLK
Combinatorial
D Q
CLK
DFF
D Q
VDD=0.99
VDD=0.98 DFF

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Predictable Success
 Details on each Technique

• Back Biasing
 Basic Understanding
 Advantages
 Concerns in the flow

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 Understanding Biasing

Shut-Down Wake-Up

Short Stop Long Stop

Body Bias (VTCMOS) MTCMOS
Reduced Leakage Zero Leakage
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 Reducing Leakage using Well Bias
FILLBIAS Gate
Source Drain
VDD
Connect
N-Well to
VDD n+ n+
VNW ID
p-well
Connect
P-Well to
VPW VSS – 0.3V VPW

VSS

• When VPW < Source Drain

 Vth increases Gate VPW I

D
 ID decreases
Source
 Leakage decreases

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Predictable Success
 Well Biasing Flow Challenges

• Impact on Area due to extra Pick-Up cells

• Multi-Corner Analysis required for Sign-Off
 VBB = 1V, VBB = 2V…etc

• Sleep to Transition Power Overhead

• LVS complexity
• Well RC extraction

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Predictable Success
 Power Savings Data
Technique Used Technology % Leakage % Total Power
Savings Savings

Clock gating 90nm NA 57%

Multi-Vt 90nm 31% NA

Power Gating 130nm 25X 13x

Power Gating 65nm 2x NA

DVFS 45nm 98% during NA

Standby

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Predictable Success
Thoughts on Efficient Leakage
Power Management

Predictable Success
 Efficient Leakage Power
Management

VDD VDD
VVSS

VSS
VDD
VSS VIRTUAL_VSS
Source:IBM

Gate Voltage
Gate Voltage

Source:IBM

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Predictable Success
 Multiple Power Mode Implementation
S0 S1 S2

1 0 0 Snore

VDD VDD 0 1 0 Dream

VVSS

VSS
VDD
0 0 1 Sleep

0 1 1 Active

VSS VIRTUAL_VSS

Gate Voltage

S0 S1 S2

Source:I
BM
Voltage Generator

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Predictable Success
 Activity Profile of Multiple Sleep Modes

Wake-Up
Shut-Down

Sleep Dream
Dream Snore
Active

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 Recycle Energy - Hybrid Car

Generator
Battery

Motor

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Predictable Success
 Recycle Energy - Hybrid Car

Generator
Battery

Motor

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 Recycle Energy - Hybrid Car

Generator
Battery

Motor

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 Recycle Energy - Hybrid Car

Generator
Battery

Motor

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 Recycle Leakage
VDD

Full Chip
Standard
Cell Area

GND

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 Recycle Leakage
VDD

Full Chip
Standard
Cell Area

TEMP_GND

Charge
Collector

GND

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Predictable Success
 Recycle Leakage
VDD

Full Chip
Standard VDD_SPARE

Cell Area

TEMP_GND

Charge
Collector

GND

© 2008 Synopsys, Inc. (53)

Predictable Success
 Where Best to Manage Power and How?
Architectural Changes
Re-architect
vectors
RTL

Simulation TB

Synthesis
VCD

Vector No
Vector
Re-architect Analysis Good?
Design

Power Yes
Analysis

No
Power Place Parasitic Sign-Off
Yes
and Extraction Analysis
Good Route
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Predictable Success
 Synopsys Low Power Flow Summary

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Predictable Success
 Predictable Success

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Predictable Success