ESSCIRC 2002

A Slew Rate Controlled Output Driver Using PLL as Compensation Circuit

Soon-Kyun Shin, Seok-Min Jung, Jin-Ho Seo, Myeong-Lyong Ko, and Jae-Whui Kim
System LSI Division, SAMSUNG Electronics, KOREA
jukjo@samsung.co.kr

Abstract the change from UDMA33 to UDMA66 the cable is

A slew rate controlled output driver adopting delay
compensation method is implemented using 0.18 ㎛
CMOS process for storage device interface. Phase-
Locked Loop is used to generate compensation current
and constant delay time. Compensation current reduces
the slew rate variation over process, voltage and
temperature variation in output driver. To generate
constant delay time, the replica of VCO in PLL is used in
output driver’s slew rate control block. That reduces the
slew rate variation over load capacitance variation.
That has less 25% variation at slew rate than that of
conventional output driver. The proposed output driver
can satisfy UDMA100 interface which specify load
capacitance as 15 ~ 40pF and slew rate as 0.4 ~
1.0[V/ns].
1. Introduction
The speed of modern storage interface has been
rapidly increasing up to 100MBps. With this increased
speed the weaknesses of the original ATA cabling
scheme has become apparent on desktop systems. System
manufactures, chipset designers, and disk drive
manufacturers must consider that signal integrity about
ringing due to improper termination, crosstalk between
signals and bus timing on the bus. UDMA100 is the
specification of ATA/ATAPI-6, which specifies the
interface between storage device and PC [1]. The ATA
specification has changed from UDMA33, UDMA66 to
UDMA100 using 16bit data lines. Each of the
specifications is shown at the table 1. With increasing
data rate and signal frequency, the crosstalk at
transmission line has been issued. This problem can be
solved using a new cable and lowering slew rate.
Lowering slew rate helps reducing noise but can not be
less than certain value because of timing margin. During
changed from 40 conductor to 80 conductor which have
additional ground lines. It reduces crosstalk and
increases signal integrity. UDMA100 slew rate
specification is tighter than UDMA66 over wide range
load condition. UDMA100 interface uses the same cable
of UDMA66, but the specification of load range is
changed from 40pF to 15 ~ 40pF and that of slew rate is
changed from maximum 1.25[V/ns] to 0.4 ~ 1.0[V/ns].
This means maximum load is 2.67 times larger than
its minimum and slew rate maximum is 2.5 times larger
than its minimum. Conventional output driver can not be
used because its characteristic of slew rate changes in
proportion to the load capacitance. To satisfy this
specification, two compensation circuits for load
capacitance and PVT (Process, Voltage, Temperature)
variation are needed.
Various compensation architectures have been
previously reported for PVT variation [2][3], and most of
them uses external resistor. Feedback architecture has
been reported for wide range load capacitance variation
[4], but it can’t be used in such a fast slew rate.
This paper proposes a slew rate controlled output
driver that has tolerant to PVT variation and load
variation.

Table 1. Slew rate specification of ATA interface.

Signal Slew rate
ATA mode Figure 1. Simplified waveforms of PAD and
frequency specification
UDMA33 8.25 MHz min tr,tf 5ns its gate voltage.
UDMA66 16.5 MHz max 1.25[V/ns] (a) When PAD is falling.
UDMA100 25 MHz 0.4 ~ 1.0[V/ns] (b) When PAD is rising.

207

Figure 2. Simplified block diagram of new output
driver.
(a) PLL.
(b)Output driver.
2. Circuit design
The important design point of UDMA100 I/O is the
slew rate control at output driver. An output driver that
does not adopt compensation circuit can not satisfy the
UDMA100 slew rate specification because of the large
variation of slew rate over the variation of PVT and load
capacitance.
A compensation circuit using PLL is adopted to
generate constant delay and to make compensation
current over the PVT variation. To compensate the slew
rate variation over the load variation, the method that
controls the gate voltage of output MOS driver through
increasing or decreasing the voltage level in two steps is
adopted. Fig. 1 shows detailed idea. If the load
capacitance is small, the transition of output driver is
already completed before the gate control voltage goes to
second step. So the second voltage step of gate does not
affect the slew rate. If the load capacitance is large, the
first voltage step of gate voltage level is too low to meet
the slew rate specification. For this reason, second
voltage step of gate can increase the slew rate after a
delay time from first voltage step of gate. This interval
time can be estimated through the transition time
simulation of first voltage step over PVT variation.
2.1. Compensation current and constant delay
generation using Phase-Locked Loop
The delay time of conventional delay circuit varies
too much over PVT corner to meet the UDMA100 slew
208
Figure 3. Voltage controlled oscillator
rate specification. So PLL is adopted to generate the
constant delay time over PVT corner. The characteristic
of PLL is the constant clock frequency over PVT corner
when PLL is locked. The fact that clock frequency is
constant means that the period of clock is constant. And
this means that delay time is constant at each inverter
stage of VCO. Fig. 3 shows the VCO. The VCON
control voltage of VCO generates the bias voltage in the
VCO block to make certain frequency. And this bias
voltage is used as compensation voltage of slew rate in
the output driver. Fig.2 shows that PLL supplies bias
voltage for compensation to output driver. The voltage of
VPBIAS and VNBIAS that come from VCO is supplied
to slew rate control block in the output driver.
The VCO’s oscillation frequency is shown in equation.
f osc = N ( t 11+ t 2 ) = N I d
C totV DD
Where t1 and t2 are the charge and
discharge time, respectively, N is the number of delay
stage, Ctot is the total capacitance of each stage, Id is the
bias current and VDD is the supply voltage [5]. If VDD
is constant and PLL is locked condition, Id is constant
current over PVT corner.
For all variation of the PVT, the PLL is locked after a
certain time and the frequency of the VCO’s output
signal is constant. So the delay stage of the VCO
produces the constant delay time. The output driver uses
the replica of VCO’s delay stage as shown in fig 4. After
the PLL is locked, the bias voltages of the VCO such as
VPBIAS and VNBIAS are produced. And the slew rate
control block of the output driver utilizes that voltage.
2.2. Slew rate control block in output driver
Fig. 2 shows the output driver that consists of control
logic block, slew rate control block, and output of pMOS
and nMOS with tolerant and fail-safe function. The
control logic block has the function that controls tri-state.
The slew rate control block controls the gate voltage of
MOS driver using the compensation voltage of VPBIAS
and VNBIAS that come from PLL. Fig. 4 shows the slew

Figure 5. Corner simulation results.
(a)Process fast, VDD:3.564V,temp -40℃,load 15pF.
(b)Process typical, VDD: 3.3V, temp 25℃,load 27pF.
(c)Process slow,VDD:3.036V,temp125℃,load 40pF.
Figure 4. Simplified schematic of slew rate
control block.
(a) PMOS driver gate voltage control block.
(b) Delay block (replica of VCO).
(c) NMOS driver gate voltage control block.
rate control block and MOS driver. In detail, the PC and
NC go same logic level when the output driver transmits
the data signal. If the output driver is in tri-state mode the
PC is high and NC is low state. The delay block
generates constant delay time over PVT corner when
PLL is in the locked condition because the MOS size and
structure is the replica of VCO. P1 and N1 have same
length and bias voltage of VCO’s bias MOS. The only
difference is just the width. Therefore, it is operated as
current mirror.
The current equation in the output driver when PLL is
locked is shown.
N CtotV DD
I control = K × I d = K f osc
Where K is ratio factor
of current mirror, N is number of inverter stage, Ctot is
total capacitance of an inverter stage, VDD is power
supply voltage, and fosc is frequency when PLL is
locked.
The dominant factor of Icontrol is VDD. The
variation of process and temperature does not change the
current because K and Ctot are physical factor, and fosc
is constant value when PLL is in locked condition. This
current makes the constant current source that generates
the waveforms, which are DELAY1 and DELAY2 at the
(a)
(b)
(c)
first step of NG and PG in fig. 5. The first voltage step
can satisfy the slew rate specification at 15pF load
condition and the second voltage step can satisfy the
40pF load condition. The starting time of second voltage
step can be determined through transition time simulation
over PVT corner at 15pF load condition.
When output PAD is falling condition both PC and
NC go to fall, and NG go to rise. At this time PG rises
rapidly to turn off pMOS driver, and P1 which is
connected by NC supply the constant current to NG. So
NG rises with constant slope. After NC goes to fall, P2 is
turned on in certain delay time by delay block. P2
determines the second rising slope.
When output PAD is rising, it can be explained
similarly. Both PC and NC go to rise, and PG goes to fall.
At this time NG falls rapidly to turn off nMOS driver,
and N1 that is connected by PC supply the constant
current to PG. So PG falls with constant slope. After PC
rises, N2 is turned on in certain delay time by delay
block. N2 determines the second falling slop. P3, P4, N3
and N4 are just used as switch.
3. Simulation and measurement results
HSPICE simulation is done using 0.18 ㎛ CMOS
SPICE model parameter. Fig. 5 shows the simulation
results of slew rate whose conditions are fast, typical and
slow in PVT corner. The delay time of DLEAY1 and
DLEAY2 are constant in spite of PVT variation. Fig. 6
is the simulation results of conventional output driver
and fig. 7 is that of proposed new output driver. With
comparing fig. 6 with fig. 7, the slew rate variation in
209
 (a) (b) (a) (b)

(c) (d) (c) (d)

Figure 6. Conventional output driver simulation
results.
(a),(b)Process slow~fast, VDD:3.564V
, temp –40~125℃,load 15pF.
(c),(d)Process slow,typical,fast, VDD:3.036V
, temp –40~125 ℃,load 40pF.
Figure 7. Proposed output driver simulation
results.
(a),(b)Process slow~fast, VDD:3.564V
, temp –40~125℃,load 15pF.
(c),(d)Process slow,typical,fast, VDD:3.036V
, temp –40~125 ℃,load 40pF.

variation at maximum slew rate than that of conventional

Table 2. Simulation results of slew rate. output driver.
Slew rate Simulation results [V/ns] The test chip was fabricated in a 0.18 ㎛ 1-poly,6-
metal CMOS technology. Silicon area is 70*401 [u ㎡]
UDMA100 in output driver and 421*317 [u ㎡] in PLL. Fig. 8 is
0.4 ~ 1.0
specification
measured waveforms at the load conditions of 15pF and
Conventional 40pF. The measured results over all PVT corners satisfy
0.305 ~ 1.216
output driver the UDMA100 specifications.
Proposed
0.403 ~ 0.986
output driver
4. Conclusions
In this paper, a slew rate controlled output driver was
implemented using PLL as bias voltage generation block
in 0.18 ㎛ CMOS technology. A constant delay and
compensation current over PVT corner was generated by
PLL and used in output driver to minimize the slew rate
variation. Its slew rate variation is less 25% than that of
conventional output driver. The proposed output driver
can satisfy the UDMA100 specification which specify
slew rate range as 0.4 ~ 1.0[V/ns] at load capacitance
range as 15 ~ 40pF.
15pF 40pF
5. References
[1] T13, "ATA/ATA-6 Specification," pp. 11-16, 2001.
[2] Dabral,Sanjay, "Basic ESD and I/O design," A
Wiley Interscience Publication, pp. 151- 162, 1998
[3] T.Shirotory and K. Nogamir ,"PLL Based Impedance
Figure 8. Measured results of test chip. Control Output Buffer," Symp. on VLSI Circuits, pp. 49-
50,1991
[4] F.Garcia, P.Coll, and D.Auvergne, "Design of a Slew
Rate Controlled Output Driver", ASIC Conference,
fig.7 is smaller than that in fig. 6. Table 2 shows the pp.147-150, 1998
compared results. That shows new output driver has less [5] R. Jacob Baker, Harry W.Li and David E. Boyce,
23% variation at minimum slew rate and less 25% "CMOS Circuit Design, Layout, and Simulation," IEEE
Press, pp. 383-387, 1998

210