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TNE027 Digital Communication Electronics, Lab2

CORDIC algorithm verification with Soft Devices in Altium Designer 6

Preparation before the lab: Study CORDIC algorithm with MATLAB simulation

1. Copy the MATLAB programs from


S:\TN\E\027_Digital_Kommunikationselektronik\CORDIC MATLAB code\ to
your own directory.
2. The MATLAB programs simulate the rotation mode of CORDIC algorithm with
floating-point computation and integer computation, respectively. Run the programs in
MATLAB with various input data and verify that correct results can be obtained.

Part 1: Testing a VHDL code for a pipelined implementation of CORDIC

1. Copy the VHDL files for CORDIC algorithm verification from


S:\TN\E\027_Digital_Kommunikationselektronik\CORDIC VHDL code\ to your
own directory.
2. Create a new FPGA project by clicking on File » New » Project » FPGA »
Project and rename the new project file by clicking on File » Save Project As.
3. Create a schematic source document.
4. Add the VHDL file Cordic.Vhd to the project.
5. Create a new sheet symbol from the VHDL file by selecting Design » Create
Sheet Symbol from Sheet Or HDL.
6. Place the following components on the schematic from FPGA EvalBoard Port-
Plugin.IntLib:
a. TEST_BUTTON
b. CLOCK_BOARD
c. NEXUS_JTAG_CONNECTOR

7. Place the following components on the schematic from FPGA Generic.IntLib:


a. NEXUS_JTAG_PORT
b. 4 units of JB (System BUS Joiner)
See the information on bus joiners in Chapter 4.5.3 of the file Training Module 5
FPGA Design.pdf in the directory
S:\TN\E\027_Digital_Kommunikationselektronik\Altium Manuals and Tutorials\.

8. Place the following components on the schematic from FPGA Instruments.IntLib:


a. IOB_1X8
b. 2 units of IOB_1X16
The components in FPGA Instruments.IntLib are embedded instruments for
debugging the hardware in FPGA. See a more detailed introduction in Chapter 8 of the
file Training Module 5 FPGA Design.pdf in the directory
S:\TN\E\027_Digital_Kommunikationselektronik\Altium Manuals and Tutorials\.

9. Connect the components as the schematic in Figure 1.

TNE027 Digital Communication Electronics, Lab2 1


Figure 1. Schematic for CORDIC algorithm verification

10. Click on Tools » Force Annotate All… .


11. Click on Devices to get a device view.
12. Compile, synthesize, build and program FPGA.
13. Double-click on each of the 3 symbols for 1-Ch x 8 Digital IO. See Figure 2.
14. Three embedded instruments are shown in Figure 3. Select suitable binary values for
the algorithm verification. Click on any bit of the binary output value will toggle the
bit. Any hex output value can be also changed by typing a new value.
15. Try various values in the MATLAB program which uses a look-up table and verify
whether the Cordic VHDL code can produce the same result. Notice that some
constants have been multiplied with the input values to obtain integers in the
MATLAB programs.

TNE027 Digital Communication Electronics, Lab2 2


Figure 2. Device View

Figure 3. Embedded instruments

Part 2: Adding an output signal z_n to the VHDL code

The Cordic VHDL code does not include the output signal for the final result of z. Add an
output signal z-n to the code. After changing the VHDL code, show the schematic and click
on Design » Synchronize Sheet Entries and Ports. If there is any unmatched sheet

TNE027 Digital Communication Electronics, Lab2 3


symbol, the window in Figure 4 will be shown. Select the added output signal and click on
Add Sheet Entries. Program the FPGA and test the VHDL code.

If you have time, you can add other output signals to observe the intermediate stages of the
pipelined implementation with embedded instruments.

Figure 4. Synchronize Ports To Sheet Entries

Part 3: Using a button input and a single pulse generator for hardware verification

1. Add the VHDL files Clock_divider.Vhd and Single_pulse.Vhd to the project.


2. Create new sheet symbols from the VHDL files by selecting Design » Create
Sheet Symbol from Sheet Or HDL.
3. Place the component USER_BOTTON0 on the schematic from FPGA EvalBoard
Port-Plugin.IntLib.
4. Change the schematic as in Figure 5.
5. Force annotate all and program FPGA.
6. Reset the registers by pushing TEST/RESET button.
7. Test the implementation by selecting suitable input values and pushing the button
SW1 at least 6 times.
8. Test the implementation by selecting a different input value after each push of the
button SW1 to observe the operation of the pipeline.
9. Study the VHDL files Clock_divider.Vhd and Single_pulse.Vhd . Draw a
waveform for the single pulse generator. Why should a clock divider be used? Test by
removing the clock divider.

TNE027 Digital Communication Electronics, Lab2 4


Figure 5. Schematic for using a button and a single pulse generator.

Part 4: Improve the implementation


Improve the accuracy of the CORDIC VHDL code by changing the VHDL code. You may
consider the following improvements:
1. Increase the accuracy of the angle values to be accumulated at each stage.
2. Increase the number of pipeline stages.
You should use the MATLAB simulation to help you determine the parameters and improve
the design.

Optional Part 1: Display the results with 7-segment display modules


Write a VHDL code for converting 4-bit binary values to 7-bit input values for 7-segment
display modules. The design should display the x and y results of the CORDIC
implementation on the 7-segment display modules.

Optional Part 2: Implement the CORDIC state machine


Implement the CORDIC state machine as given in Fig. 2.38 on page 99 of the text book.

Optional Part 3: Simulate the VHDL code by using a simulator


Read Chapter 11 of the file Training Module 5 FPGA Design.pdf in the directory
S:\TN\E\027_Digital_Kommunikationselektronik\Altium Manuals and Tutorials\. An
example for Simulation of the CORDIC VHDL code is given in the file

TNE027 Digital Communication Electronics, Lab2 5


Simulation_of_VHDL_code.pdf, which can be found in the homepage of the course. The link
to the file is http://staffwww.itn.liu.se/~qinye/tne027/Simulation%20of%20VHDL%20code.pdf .

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