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Mitsubishi Electric Corporation has used an op- measuring 38 × 140 × 190mm, the same as the
timized design for IGBT chips to develop 4.5kV 2.5kV/3.3kV, 1200A product.
(rated voltage) HVIGBT modules with a satura- When designing high-voltage IGBT chips, the
tion voltage between the collector and emitter n− base layer thickness must be increased to
lower than the 3.3kV of the corporation’s previ- suppress the hot leakage current (to prevent
ous products. Three new products of this types thermal runs); however, because this has a
have now been released, with rated currents of negative effect on the boundary between the
400A, 600A and 900A. switching loss and the collector-emitter
saturation voltage, the design used reduced the
Development Targets thickness of the n− base layer as far as possible.
Semiconductor devices able to withstand in- Fig. 2 shows the dependencies of the collec-
creasingly high voltages are needed in order to tor-emitter saturation voltage VCE(sat) and the hot
make power systems smaller and lighter in the
field of high-voltage applications. In response,
the corporation will release the new products in 5.0 30
the same package types as the 2.5kV/3.3kV 4.8 thermal run
HVIGBT modules previously released. One goal 4.6
25
(Jc=50A/cm2, Tj=125oC)
ICES(hot)
(VCES=4.5kV, Tj=125oC)
in the project was to reduce the saturation volt- 4.4
ICES(hot) [mA/cm2]
20
age between the collector and the emitter to a
VCE(sat) [V]
4.2 VCE(sat)
value lower than the 4.0V saturation voltage in 4.0 15
TJ=125°C). 3.4 5
3.2
0
Description of the Modules 3.0
400 450 500 550 600 650
Fig. 1 is a view of the 4.5kV HVIGBT module. tn-[µm]
On the left is a 400A/600A single HVIGBT mod-
ule, measuring 38 × 140 × 130mm (H × W × L), Fig. 2 Dependence of VCE(sat) and ICES(hot) on
the same as the 2.5kV/3.3kV, 800A product. On tn- in the 4.5kV-IGBT chip
the right is the 900A single HVIGBT module,
*Satoru Chikai is with Power Device Division and Koichi Mochizuki is with Fukuryo Semi-con Engineering Corporation.
(VCES=4.5kV, Tj=125oC)
(Jc=50A/cm2, Tj=125oC)
with Tn− = 500µm would cause VCE(sat) = 3.6V,
ICES(hot) [mA/cm2]
10.0 20.0
fulfilling the original target value of 4.0V, the
VCE(sat) [V]
15.0
results of other investigations made it clear that
I CES(hot) could be reduced by optimizing the 5.0 10.0
density in the p+ collector layer, so the develop-
5.0
ment target was changed to VCE(sat) = 3.3V, and
a thickness of tn− = 450µm was selected. Note 0.0 0.0
1.E-01 1.E+00 1.E+01 1.E+02 1.E+03
γ
Emitter Gate
Fig. 4 Dependence of VCE(sat) and ICES(hot) on γ in the
4.5kV-IGBT chip
n+ buffer layer
(VCES=4.5kV, Tj=125oC)
10.0 1.0
9.0 Iztc/IC 0.9
p+ collector layer 8.0 0.8 (Iztc/IC(rating))
ICES(hot) [mA]
7.0 0.7
6.0 0.6
5.0 0.5
4.0 0.4
Collector 3.0 0.3
2.0 ICES(hot) 0.2
1.0 0.1
Fig. 3 Cross-section of the high-voltage IGBT chip 0.0 0.0
0 10 20 30 40 50 60
Month Year · 19
TECHNICAL REPORTS
VCE : Rated
Collector cutoff Tj=25OC 8 12 18
ICES Voltage mA
current (max.)
VGE : 0V Tj=125OC 40 60 90
Gate-emitter IC : Rated Current/10000
VGE(th) threshold voltage VGE=10V , Tj=25OC 6.0 6.0 6.0 V
(typ.)
Gate leakage current
IGES VGE=VGES , VCE=0V 0.5 0.5 0.5 µA
(max.)
Collector- IC : Rated
Tj=25OC 3.0 3.0 3.0
VCE(sat) emitter saturation current V
voltage (typ.) O
VGE=15V Tj=125 C 3.3 3.3 3.3
IE : Rated
Tj=25OC 4.0 4.0 4.0
Emitter- current
VEC V
collector voltage (typ.)
O
VGE=0V Tj=125 C 3.6 3.6 3.6
Because the 4.5kV HVIGBT module was de- using these products. They will also contribute
signed, as described above, to minimize the heat to energy conservation when applied to the con-
generated from the semiconductor chips, this verters and inverters for use at increasingly
design promises to reduce power loss in systems higher voltages in the future. ❑