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 4 6

DUT GEII - Informatique des Systèmes Industriels

U
UE E 2 3 I
Matière
n f o r
Volume horaire
m a t i q u e I n d u s t r i e l l e
1
2 C 2 0 T D 2 8 T P

Référence
I I 2 A r c h i t e c t u
Module
r e d e s s y s t è m e s
Positionnement S

à p

r o c e s s e u r s

Objectifs :
Maîtriser l’implémentation des concepts de la programmation structurée et
$

démystifier le langage de haut niveau (exemple : traduction C / Assembleur),

Comprendre l’architecture d’un système à processeur,
$

Comprendre les mécanismes d'interruption.

$

Compétences minimales :
Ɯtre capable d’écrire un programme langage de haut niveau pour une cible à
$

microprocesseur ou microcontrôleur,
Savoir interfacer un périphérique, savoir gérer des entrées – sorties,
$

Ɯtre capable d’évaluer les contraintes de temps dans le cas d’une application
$

simple.
Pré-Requis :
$

Module II1 Algorithmique, Programmation

$

Module ENSL1 électronique numérique, synthèse logique

Contenu :
$

Terminologie : micro-ordinateur, microprocesseur, micro-contrôleur,

$

Organisation matérielle d’un micro-contrôleur. Étude de l’espace d’adressage sur

un exemple de composant, types de mémoires et leur rôle dans l’architecture,
$

Modèle de programmation d’un processeur, jeu d’instructions, exemples de

sources en langage assembleur,
$

La pile et ses utilisations,

$

Analyse du code assembleur généré par un compilateur,

$

Interfaces d’entrées-sorties parallèle et série,

$

Utilisations des ‘timers’,

$

Fonctionnement en régime d’interruption, procédures de traitement d’interruption.

Modalités de mise en œuvre :
$

Utiliser un environnement de développement en langage évolué,

$

Écrire des applications sur cible à processeur, mettant en œuvre des

périphériques d'entrée/sortie, programmée en langage évolué pouvant inclure des
fonctions simples en assembleur (utilisation des instructions de traitement des bits,
si elles existent),
$

Faire comprendre la part matérielle et la part logicielle dans le traitement des

interruptions,
$

S’appuyer sur des exemples de programmes de traitement du signal (mise en

œuvre de convertisseurs analogique-numérique et numérique-analogique ), de
dialogue via des interfaces série.
Prolongements :
$

Par modules complémentaires MC-II3, MC-II2.

Mots-clés :
$

Microcontrôleur, périphériques, architecture, variables, mémoires, registres, ports,

interruptions.

© Ministère de l'éducation nationale, de l'enseignement supérieur et de la recherche SEPTEMBRE 2005

 User Manual

3. Parts Location Diagram

Place Plan - Component Side

7
 MC9S12DP512 Device Guide V01.25

Figure 1-1 MC9S12DP512 Block Diagram

VRH VRH VRH
512K Byte Flash EEPROM ATD0 ATD1
VRL VRL VRL
VDDA VDDA VDDA
14K Byte RAM VSSA VSSA VSSA
AN00 PAD00 AN08 PAD08
4K Byte EEPROM AN01 PAD01 AN09 PAD09
AN02 PAD02 AN10 PAD10
VDDR

AD0

AD1
AN03 PAD03 AN11 PAD11
VSSR AN04 PAD04 AN12 PAD12
VREGEN Voltage Regulator AN05 PAD05 AN13 PAD13
VDD1,2 AN06 PAD06 AN14 PAD14
VSS1,2 AN07 PAD07 AN15 PAD15

Single-wire Background PIX0 PK0 XADDR14

BKGD Debug Module CPU12 PIX1 PK1 XADDR15
PPAGE
PIX2 PK2

DDRK
XADDR16

PTK
XFC
Clock and PIX3 PK3 XADDR17
VDDPLL
PLL Reset PIX4 PK4 XADDR18
VSSPLL Generation Periodic Interrupt
PIX5 PK5 XADDR19
EXTAL Module COP Watchdog
ECS PK7 ECS
XTAL Clock Monitor
RESET Breakpoints IOC0 PT0
IOC1 PT1
PE0 XIRQ
IOC2 PT2
PE1 IRQ

DDRT
Enhanced Capture

PTT
System IOC3 PT3
PE2 R/W
Integration Timer IOC4 PT4
DDRE
PTE

PE3 LSTRB
Module IOC5 PT5
PE4 ECLK (SIM) IOC6 PT6
PE5 MODA
IOC7 PT7
PE6 MODB
PE7 NOACC/XCLKS RXD PS0
SCI0
TXD PS1
TEST
RXD PS2
SCI1

DDRS
PTS
TXD PS3
MISO PS4
Multiplexed Address/Data Bus MOSI PS5
SPI0 SCK PS6
SS PS7
DDRA DDRB
BDLC RXB
PTA PTB (J1850) TXB PM0
Module to Port Routing

RXCAN PM1
CAN0
TXCAN PM2
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
DATA15 ADDR15 PA7
DATA14 ADDR14 PA6
DATA13 ADDR13 PA5
DATA12 ADDR12 PA4
DATA11 ADDR11 PA3
DATA10 ADDR10 PA2
ADDR9 PA1
ADDR8 PA0

DDRM
PTM
RXCAN PM3
CAN1
TXCAN PM4
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0

RXCAN PM5
CAN2
TXCAN PM6
RXCAN PM7
CAN3
TXCAN
DATA9
DATA8

DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0

Multiplexed RXCAN
Wide Bus CAN4
TXCAN
KWJ0 PJ0
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0

DDRJ

Multiplexed
PTJ

KWJ1 PJ1
Narrow Bus SDA KWJ6 PJ6
IIC
SCL KWJ7 PJ7
Internal Logic 2.5V I/O Driver 5V
PWM0 KWP0 PP0
VDD1,2 VDDX
PWM1 KWP1 PP1
VSS1,2 VSSX
PWM2 KWP2 PP2
DDRP
PTP

PWM3 KWP3 PP3

A/D Converter 5V & PWM
PWM4 KWP4 PP4
PLL 2.5V Voltage Regulator Reference PP5
PWM5 KWP5
VDDPLL VDDA PWM6 KWP6 PP6
VSSPLL VSSA PWM7 KWP7 PP7
MISO KWH0 PH0
MOSI KWH1 PH1
Voltage Regulator 5V & I/O SPI1
VDDR SCK KWH2 PH2
DDRH
PTH

VSSR SS KWH3 PH3

MISO KWH4 PH4
MOSI KWH5 PH5
SPI2
SCK KWH6 PH6
SS KWH7 PH7

23
MC9S12DP512 Device Guide V01.25 MC9S12DP512 Device Guide V01.25

1.5 Device Memory Map Table 1-1 Device Memory Map

Size
Address Module
Table 1-1 and Figure 1-2 show the device memory map of the MC9S12DP512 after reset. Note that after (Bytes)
reset the bottom 1k of the EEPROM ($0000 - $03FF) are hidden by the register space $8000 - $BFFF Flash EEPROM Page Window 16384
Fixed Flash EEPROM array
Table 1-1 Device Memory Map $C000 - $FFFF incl. 2K, 4K, 8K or 16K Protected Sector at end 16384
and 256 bytes of Vector Space at $FF80 - $FFFF
Address Module Size
(Bytes)
$0000 - $000F HCS12 Multiplexed External Bus Interface 16
$0010 - $0014 HCS12 Module Mapping Control 5
$0015 - $0016 HCS12 Interrupt 2
$0017 - $0019 Reserved 3
$001A - $001B Device ID register (PARTID) 2
$001C - $001D HCS12 Module Mapping Control 2
$001E HCS12 Multiplexed External Bus Interface 1
$001F HCS12 Interrupt 1
$0020 - $0027 Reserved 8
$0028 - $002F HCS12 Breakpoint 8
$0030 - $0031 HCS12 Module Mapping Control 2
$0032 - $0033 HCS12 Multiplexed External Bus Interface 2
$0034 - $003F Clock and Reset Generator (PLL, RTI, COP) 12
$0040 - $007F Enhanced Capture Timer 16-bit 8 channels 64
$0080 - $009F Analog to Digital Converter 10-bit 8 channels (ATD0) 32
$00A0 - $00C7 Pulse Width Modulator 8-bit 8 channels (PWM) 40
$00C8 - $00CF Serial Communications Interface 0 (SCI0) 8
$00D0 - $00D7 Serial Communications Interface 0 (SCI1) 8
$00D8 - $00DF Serial Peripheral Interface (SPI0) 8
$00E0 - $00E7 Inter IC Bus 8
$00E8 - $00EF Byte Data Link Controller (BDLC) 8
$00F0 - $00F7 Serial Peripheral Interface (SPI1) 8
$00F8 - $00FF Serial Peripheral Interface (SPI2) 8
$0100- $010F Flash Control Register 16
$0110 - $011B EEPROM Control Register 12
$011C - $011F Reserved 4
$0120 - $013F Analog to Digital Converter 10-bit 8 channels (ATD1) 32
$0140 - $017F Motorola Scalable Can (CAN0) 64
$0180 - $01BF Motorola Scalable Can (CAN1) 64
$01C0 - $01FF Motorola Scalable Can (CAN2) 64
$0200 - $023F Motorola Scalable Can (CAN3) 64
$0240 - $027F Port Integration Module (PIM) 64
$0280 - $02BF Motorola Scalable Can (CAN4) 64
$02C0 - $03FF Reserved 320
$0000 - $0FFF EEPROM array 4096
$0800 - $3FFF RAM array 14336
Fixed Flash EEPROM array
$4000 - $7FFF 16384
incl. 1K, 2K, 4K or 8K Protected Sector at start

24 25
MC9S12DP512 Device Guide V01.25

Addressing Modes

Figure 1-2 MC9S12DP512 Memory Map

Table 3-1. M68HC12 Addressing Mode Summary
$0000 $0000
Addressing Mode Source Format Abbreviation Description
REGISTERS
$0400 (Mappable to any 2k Block INST
within the first 32K)
$03FF Inherent (no externally INH Operands (if any) are in CPU registers
$0800 supplied operands)
$0000 4K Bytes EEPROM
(Mappable to any 4K Block) INST #opr8i
Operand is included in instruction stream
Immediate or IMM
8- or 16-bit size implied by context
$0FFF INST #opr16i
$0800 14K Bytes RAM Operand is the lower 8 bits of an address
Direct INST opr8a DIR
(Mappable to any 16K in the range $0000–$00FF
and alignable to top or
$4000 bottom) Extended INST opr16a EXT Operand is a 16-bit address
$3FFF
INST rel8
$4000 16K Fixed Flash An 8-bit or 16-bit relative offset from the current pc
Relative or REL
Page $3E = 62 is supplied in the instruction
INST rel16
(This is dependant on the
state of the ROMHM bit) Indexed 5-bit signed constant offset
INST oprx5,xysp IDX
(5-bit offset) from X, Y, SP, or PC
$7FFF
Indexed
INST oprx3,–xys IDX Auto pre-decrement x, y, or sp by 1 ~ 8
$8000 (pre-decrement)

$8000 Indexed
INST oprx3,+xys IDX Auto pre-increment x, y, or sp by 1 ~ 8
(pre-increment)
16K Page Window Indexed
EXTERN 32 x 16K Flash EEPROM INST oprx3,xys– IDX Auto post-decrement x, y, or sp by 1 ~ 8
pages (post-decrement)
Indexed
$BFFF INST oprx3,xys+ IDX Auto post-increment x, y, or sp by 1 ~ 8
(post-increment)

$C000 Indexed Indexed with 8-bit (A or B) or 16-bit (D)

INST abd,xysp IDX
(accumulator offset) accumulator offset from X, Y, SP, or PC
$C000
Indexed 9-bit signed constant offset from X, Y, SP, or PC
INST oprx9,xysp IDX1
(9-bit offset) (lower 8 bits of offset in one extension byte)
16K Fixed Flash
Page $3F = 63 Indexed 16-bit constant offset from X, Y, SP, or PC
INST oprx16,xysp IDX2
(16-bit offset) (16-bit offset in two extension bytes)
$FFFF Pointer to operand is found at...
Indexed-Indirect
$FF00 INST [oprx16,xysp] [IDX2] 16-bit constant offset from X, Y, SP, or PC
BDM (16-bit offset)
(16-bit offset in two extension bytes)
$FF00 (if active)
VECTORS VECTORS VECTORS $FFFF Indexed-Indirect Pointer to operand is found at...
$FFFF INST [D,xysp] [D,IDX]
(D accumulator offset) X, Y, SP, or PC plus the value in D
EXPANDED* NORMAL SPECIAL
SINGLE CHIP SINGLE CHIP
* Assuming that a ‘0’ was driven onto port K bit 7 during MCU is reset into normal expanded wide or narrow mode.

Reference Manual S12CPUV2

26
34 Addressing Modes MOTOROLA
 MC9S12DP512 Device Guide V01.25 MC9S12DP512 Device Guide V01.25

Section 5 Resets and Interrupts $FFCA, $FFCB Modulus Down Counter underflow I-Bit MCCTL (MCZI) $CA
$FFC8, $FFC9 Pulse Accumulator B Overflow I-Bit PBCTL (PBOVI) $C8
$FFC6, $FFC7 CRG PLL lock I-Bit CRGINT (LOCKIE) $C6
5.1 Overview $FFC4, $FFC5 CRG Self Clock Mode I-Bit CRGINT (SCMIE) $C4
$FFC2, $FFC3 BDLC I-Bit DLCBCR1 (IE) $C2
Consult the Exception Processing section of the CPU12 Reference Manual for information on resets and $FFC0, $FFC1 IIC Bus I-Bit IBCR (IBIE) $C0
interrupts. $FFBE, $FFBF SPI1 I-Bit SPICR1 (SPIE, SPTIE) $BE
$FFBC, $FFBD SPI2 I-Bit SPICR1 (SPIE, SPTIE) $BC
$FFBA, $FFBB EEPROM I-Bit ECNFG (CCIE, CBEIE) $BA
5.2 Vectors $FFB8, $FFB9 FLASH I-Bit FCNFG (CCIE, CBEIE) $B8
$FFB6, $FFB7 CAN0 wake-up I-Bit CANRIER (WUPIE) $B6
5.2.1 Vector Table $FFB4, $FFB5 CAN0 errors I-Bit CANRIER (CSCIE, OVRIE) $B4
$FFB2, $FFB3 CAN0 receive I-Bit CANRIER (RXFIE) $B2
Table 5-1 lists interrupt sources and vectors in default order of priority. $FFB0, $FFB1 CAN0 transmit I-Bit CANTIER (TXEIE2-TXEIE0) $B0
$FFAE, $FFAF CAN1 wake-up I-Bit CANRIER (WUPIE) $AE
Table 5-1 Interrupt Vector Locations
$FFAC, $FFAD CAN1 errors I-Bit CANRIER (CSCIE, OVRIE) $AC
Vector Address Interrupt Source CCR Local Enable HPRIO Value
Mask to Elevate $FFAA, $FFAB CAN1 receive I-Bit CANRIER (RXFIE) $AA
$FFFE, $FFFF Reset None None – $FFA8, $FFA9 CAN1 transmit I-Bit CANTIER (TXEIE2-TXEIE0) $A8
$FFFC, $FFFD Clock Monitor fail reset None PLLCTL (CME, SCME) – $FFA6, $FFA7 CAN2 wake-up I-Bit CANRIER (WUPIE) $A6
$FFFA, $FFFB COP failure reset None COP rate select – $FFA4, $FFA5 CAN2 errors I-Bit CANRIER (CSCIE, OVRIE) $A4
$FFF8, $FFF9 Unimplemented instruction trap None None – $FFA2, $FFA3 CAN2 receive I-Bit CANRIER (RXFIE) $A2
$FFF6, $FFF7 SWI None None – $FFA0, $FFA1 CAN2 transmit I-Bit CANTIER (TXEIE2-TXEIE0) $A0
$FFF4, $FFF5 XIRQ X-Bit None – $FF9E, $FF9F CAN3 wake-up I-Bit CANRIER (WUPIE) $9E
$FFF2, $FFF3 IRQ I-Bit IRQCR (IRQEN) $F2 $FF9C, $FF9D CAN3 errors I-Bit CANRIER (CSCIE, OVRIE) $9C
$FFF0, $FFF1 Real Time Interrupt I-Bit CRGINT (RTIE) $F0 $FF9A, $FF9B CAN3 receive I-Bit CANRIER (RXFIE) $9A
$FFEE, $FFEF Enhanced Capture Timer channel 0 I-Bit TIE (C0I) $EE $FF98, $FF99 CAN3 transmit I-Bit CANTIER (TXEIE2-TXEIE0) $98
$FFEC, $FFED Enhanced Capture Timer channel 1 I-Bit TIE (C1I) $EC $FF96, $FF97 CAN4 wake-up I-Bit CANRIER (WUPIE) $96
$FFEA, $FFEB Enhanced Capture Timer channel 2 I-Bit TIE (C2I) $EA $FF94, $FF95 CAN4 errors I-Bit CANRIER (CSCIE, OVRIE) $94
$FFE8, $FFE9 Enhanced Capture Timer channel 3 I-Bit TIE (C3I) $E8 $FF92, $FF93 CAN4 receive I-Bit CANRIER (RXFIE) $92
$FFE6, $FFE7 Enhanced Capture Timer channel 4 I-Bit TIE (C4I) $E6 $FF90, $FF91 CAN4 transmit I-Bit CANTIER (TXEIE2-TXEIE0) $90
$FFE4, $FFE5 Enhanced Capture Timer channel 5 I-Bit TIE (C5I) $E4 $FF8E, $FF8F Port P Interrupt I-Bit PIEP (PIEP7-0) $8E
$FFE2, $FFE3 Enhanced Capture Timer channel 6 I-Bit TIE (C6I) $E2 $FF8C, $FF8D PWM Emergency Shutdown I-Bit PWMSDN (PWMIE) $8C
$FFE0, $FFE1 Enhanced Capture Timer channel 7 I-Bit TIE (C7I) $E0 $FF80 to
Reserved
$FFDE, $FFDF Enhanced Capture Timer overflow I-Bit TSRC2 (TOI) $DE $FF8B

$FFDC, $FFDD Pulse accumulator A overflow I-Bit PACTL (PAOVI) $DC

$FFDA, $FFDB Pulse accumulator input edge I-Bit PACTL (PAI) $DA 5.3 Effects of Reset
$FFD8, $FFD9 SPI0 I-Bit SPICR1 (SPIE, SPTIE) $D8
SCICR2 When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the
$FFD6, $FFD7 SCI0 I-Bit $D6
(TIE, TCIE, RIE, ILIE)
respective module Block Guides for register reset states.
SCICR2
$FFD4, $FFD5 SCI1 I-Bit $D4
(TIE, TCIE, RIE, ILIE)
$FFD2, $FFD3 ATD0 I-Bit ATDCTL2 (ASCIE) $D2
5.3.1 I/O pins
$FFD0, $FFD1 ATD1 I-Bit ATDCTL2 (ASCIE) $D0
PIEJ Refer to the HCS12 Multiplexed External Bus Interface (MEBI) Block Guide for mode dependent pin
$FFCE, $FFCF Port J I-Bit $CE
(PIEJ7, PIEJ6, PIEJ1, PIEJ0) configuration of port A, B, E and K out of reset.
$FFCC, $FFCD Port H I-Bit PIEH (PIEH7-0) $CC
Refer to the PIM Block Guide for reset configurations of all peripheral module ports.

73 74
Alphabetical List of Commands file:///f:/Temp/DOCS_TP_II2/Doc_NoIce_8/cmdlist.htm Alphabetical List of Commands file:///f:/Temp/DOCS_TP_II2/Doc_NoIce_8/cmdlist.htm

DEFS name value {%type} Abbreviation of DEFSCOPED

NoIce Alphabetical List of Commands DEFTYPE name offset
%type
Define data type "name"

A B C D E F G H I J K L M N O P Q R S T U V W X Y Z ; DEFT name offset %type Abbreviation of DEFTYPE

DELAY time Set delay for command playback
For more details on the operation and parameter format of each command, click on the command
DTR value Set serial line DTR active (value=1) or inactive (value=0)
name hot-link.
DUMP {addr} {size} Dump block of memory at addr in hex and ASCII
In each command: E {addr} {val} {%type} Abbreviation of EDIT
curly brackets {} denote optional parameters. ECHO {text string} Echo "text string" to data window
"addr" denotes an address or address expression EDIT {addr} {%type}
Examine/change memory. Optional data type override
"size" denotes a size or size expression {val.}
"value" denotes an expression ENDENUM {name} End definition of enumeration "name"

ASSEMBLE {addr} Assemble into memory ENDFILE {addr} Define the end of the current file scope for symbol definition

ASM {addr} Assemble into memory ENDFUNCTION {addr} Define the end of the current function scope for symbol definition

AUTOGEN value Abbreviation of AUTOGENERATE ENDF {address} Abbreviation of ENDFUNCTION

AUTOGENERATE value Turn automatic symbol generation on and off ENDS size {name} Abbreviation of ENDSTRUCT

B {addr} Abbreviation of BREAKPOINT ENDSTRUCT size {name} Declare the end of the current data structure definition

BREAK Same as HALT ENUM offset {name}

Begin definition of enumeration "name"
{%type}
BREAKPOINT {addr} Insert, delete, or display breakpoints
ENUMVAL value name Define "name" as a member of the current enumeration
BRK value Begin (value=1) or end (value=0) serial line break
EX1 {tail} Run the extension EX1
CALL {addr} Call a subroutine
EX2 {tail} Run the extension EX2
CALLSKIP name skipsize Define a subroutine called with post-bytes
F {text string} Abbreviation of FIND
CAP file Abbreviation of CAPTURE
FIND {text string} Find the string in the view file
CAPTURE file Capture disassembly, dump, and target output to file
FILE file {offset} Define the current file for source debug
CASE value Turn symbol case sensitivity on and off
FILL addr size value Fill memory block at addr with value
CHECK addr size Abbreviation of CHECKSUM
FRAMEPOINTER str Set name of IEEE 695 frame pointer
CHECKSUM addr size Compute byte checksum on region
FUNC name {addr} Abbreviation of FUNCTION
CLEARLINEINGO {Y} Delete all source line information
FUNCTION name {addr} Define a function for scoped symbol definition
CLEARSYMBOLS {Y} Delete all symbols
G {addr} Abbreviation of GO
COPY addr1 size addr2 Copy memory from addr1 to addr2
GO {addr} Begin execution at addr or at PC
D {addr} {size} Abbreviation of DUMP
HALT Interrupt target execution
DEF name value {%type} Abbreviation of DEFINE
I addr Abbreviation of IN
DEFB name value {%type} Abbreviation of DEFBASE
IN addr Read byte from port
DEFBASE name value
Define base symbol "name". Optional data type override INTSIZE n Set size of IEEE 695 integer
{%type}
DEFINE name value ISTEP Step one machine instruction
Define global symbol "name". Optional data type override
{%type} L file {offset} {B} Abbreviation of LOAD
DEFREG name address size Define pseudo-register "name". LARGEPOINTERSIZE n Set size of IEEE 695 large pointer
DEFSCOPED name value
Define scoped symbol "name". Optional data type override
{%type}

1 sur 5 11/01/2006 00:21 2 sur 5 11/01/2006 00:21

Alphabetical List of Commands file:///f:/Temp/DOCS_TP_II2/Doc_NoIce_8/cmdlist.htm Alphabetical List of Commands file:///f:/Temp/DOCS_TP_II2/Doc_NoIce_8/cmdlist.htm

Delete breakpoints, watches, symbols, and line information if the STATETEXT n text Set text for target state n
LASTFILELOADED
filename or its modification time have changed from the last STATICFUNCTION name
{filename} Define a static function for scoped symbol definition
invocation of this command. {addr}
LINE linum View the specified source line STEP Step into subroutines
LINE linum addr Define address of source line STOP Stop recording commands to file
LEADINGDIGIT n Set requirement for leading digit on hex numbers STRUCT offset {name} Begin definition of a data structure
LOAD file {offset} {B} Load Intel, Motorola/Freescale, Tektronix or other file SYM expr Abbreviation of SYMBOL
LONGSIZE n Set size of IEEE 695 long integer SYMBOL expr Show symbol with value "expr"
M {addr} Same as MEM TIME {comment} Show elapsed time since last TIME command
MEM {addr} Show/edit the block of memory at addr in hex or ASCII U {addr} Abbreviation of UNASM
MODE val Set source mode (0,1,2) UNASM {addr} Disassemble beginning at addr
N Abbreviation of NEXT V {file} Abbreviation of VIEW
NEXT Step over subroutine VAL expr Abbreviation of VALUE
NOFILES Delete file and line number information VALUE expr Show value of "expr"
O addr val Abbreviation of OUT VER Abbreviation of VERSION
OPEN file Open file via LOAD, PLAY, or VIEW VERSION Show host and target versions
OUT addr val Write byte to port VIEW {file} View file
PLAY file Execute commands from "file" W addr {len} {%type} Abbreviation of WATCH
POINTERSIZE n Set size of default pointer WAIT time Wait for "time" milliseconds
Q Abbreviation of QUIT WAITFORSTOP {time} Wait up to "time" seconds for the target to stop running
QUIT Exit to DOS WATCH addr {len}
Watch data at "addr"
R {reg val} Abbreviation of REGISTER {%type}
RADIX val Set radix for formatted input and output. "Val" must be 10 or 16 ; {string} Remark (comment) for command files
REC file Abbreviation of RECORD
The following commands may also be invoked by pressing the indicated function key.
RECORD file Record commands to file
F1 Help
REGISTER {reg val} Change register
F2 Dump next block
REM {string} Remark (comment) for command files F3 Find next
RESET Reset target hardware F4 View file
RTS value Set serial line RTS active (value=1) or inactive (value=0) F5 Go
S {addr} Abbreviation of SOURCE F6 List breakpoints
S2FORMAT format Set the format of Motorola/Freescale S2 addresses F7 Step into (traditional NoICE key)
Save a block of memory as an Intel or Motorola/Freescale hex file, or F8 Step over (traditional NoICE key)
SAVE file addr size
as a binary file F9 Step one instruction
SCOPE name Set current scope for scoped symbol definition and use F10 Step over (same as DevStudio)
SET name value Same as DEFINE F11 Step into (same as DevStudio)
SFUNC name {addr} Abbreviation of STATICFUNCTION
Pressing Alt and a function key will attempt to invoke the command files ALTF1.NOI through
SHORTSIZE n Set size of IEEE 695 short integer ALTF12.NOI, respectively.
SMALLPOINTERSIZE n Set size of IEEE 695 small pointer
SOURCE {addr} Show source code at beginning at addr NoICE (tm) Debugger, Copyright © 2005 by John Hartman
ST Abbreviation of STEP

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IUT GEII Rouen Freescale 9S12 Instruction Set Page 1 / 2

Add accumulator B to accumulator BHS Branch if higher or same CPD Compare accumulator D zero
ABA
A BITA Bit test accumulator A CPS Compare register SP Increment and branch if not equal
IBNE
Add accumulator B to index BITB Bit test accumulator B CPX Compare index register X to zero
ABX
register X 16-bit / 16-bit integer division
BLE Branch if less than or equal CPY Compare index register Y IDIV
Add accumulator B to index (unsigned)
ABY BLO Branch if lower DAA Decimal adjust accumulator A
register Y 16-bit / 16-bit integer division
BLS Branch if lower or same Decrement counter and branch if IDIVS
ADCA Add with carry to accumulator A DBEQ (signed)
BLT Branch if less than equal to zero
ADCB Add with carry to accumulator B INC Increment memory location
BMI Branch if minus Decrement counter and branch if
Add without carry to accumulator DBNE INCA Increment accumulator A
ADDA not equal to zero
A BNE Branch if not equal
DEC Decrement memory location INCB Increment accumulator B
Add without carry to accumulator BPL Branch if plus
ADDB DECA Decrement accumulator A INS Increment register SP
B BRA Branch always
DECB Decrement accumulator B INX Increment index register X
Add without carry to accumulator BRCLR Branch if bit clear
ADDD DES Decrement register SP INY Increment index register Y
D BRN Branch never
DEX Decrement index register X JMP Jump
ANDA Logical and with accumulator A BRSET Branch if bits set
DEY Decrement index register Y JSR Jump to subroutine
ANDB Logical and with accumulator B BSET Set bit(s) in memory
EDIV Division 32-bits/16 bits (unsigned) LBCC Long branch if carry clear
ANDCC Logical and CCR with mask BSR Branch to subroutine
EDIVS Division 32-bits/16 bits (signed) LBCS Long branch if carry Set
ASL Arithmetic shift left memory BVC Branch if overflow cleared
EMACS Multiply and accumulate signed LBEQ Long branch if equal
Arithmetic shift left accumulator BVS Branch if overflow set
ASLA Long branch if greater than or
A Maximum of 2 unsigned integer in LBGE
call subroutine in extended EMAXD equal
ASLB Arithmetic shift left accumulator B CALL accumulator D
memory LBGT
Maximum of 2 unsigned integer in Long branch if greater than
Arithmetic shift left accumulator CBA Compare accumulator A and B EMAXM
ASLD memory LBHI Long branch if higher
D
CLC Clear carry bit
ASR Arithmetic shift right memory Minimum of 2 unsigned integer in LBHS Long branch if higher or same
CLI Clear interrupt bit EMIND
accumulator D LBLE Long branch if Less Than or equal
Arithmetic shift right accumulator
ASRA CLR Clear memory Minimum of 2 unsigned integer in
A EMINM LBLO Long branch if lower
CLRA Clear accumulator A memory
Arithmetic shift right accumulator LBLS Long branch if lower or same
ASRB CLRB Clear accumulator B 16-bit * 16-bit multiplication
B EMUL LBLT Long branch if less than
BCC Clear two’s complement overflow (unsigned)
Branch if carry clear CLV LBMI Long branch if Minus
BCLR bit 16-bit * 16-bit multiplication
Clear bit(s) in memory EMULS LBNE Long branch if not equal
CMPA Compare accumulator A (signed)
BCS Branch if carry set LBPL Long branch if plus
CMPB Compare accumulator B EORA Exclusive or with accumulator A
BEQ Branch if equal LBRA Long branch always
COM One’s complement on memory EORB Exclusive or with accumulator B
BGE Branch if greater than or equal LBRN Long branch never
One’s complement on accumulator ETBL Table Lookup and Interpolate
BGND Enter background debug mode COMA LBVC Long branch if overflow clear
A EXG Exchange register contents
BGT Branch if greater than LBVS Long branch if overflow set
One’s complement on accumulator FDIV 16-bit / 16-bits fractional divide
BHI Branch if higher COMB
B IBEQ Increment and branch if equal to LDAA Load accumulator A
IUT GEII Rouen Freescale 9S12 Instruction Set Page 2 / 2

LDAB Load accumulator B ORAB Inclusive or with accumulator B STAA Store accumulator A WAV Weighted Average Calculation
LDD Load accumulator D ORCC Inclusive or CCR with mask STAB Store accumulator B Exchange accumulator D with
XGDX
LDS Load register SP PSHA Push accumulator A STD Store accumulator D index register X
LDX Load index register X PSHB Push accumulator B STOP Stop processing Exchange accumulator D with
XGDY
index register Y
LDY Load index register Y PSHC Push register CCR STS Store register SP
LEAS Load SP with effective address PSHD Push accumulator D STX Store index register X
LEAX Load X with effective address PSHX Push index register X STY Store index register Y
LEAY Load Y with effective address PSHY Push index register Y Subtract without carry from
SUBA
LSL Logical shift left in memory PULA Pop accumulator A accumulator A
LSLA Logical shift left accumulator A PULB Pop accumulator B Subtract without carry from
SUBB
accumulator B
LSLB Logical shift left accumulator B PULC Pop register CCR
Subtract without carry from
LSLD Logical shift left accumulator D PULD Pop accumulator D SUBD
accumulator D
LSR Logical shift left in memory PULX Pop index register X SWI Software interrupt
LSRA Logical shift right accumulator A PULY Pop index register Y
Transfer accumulator A to
LSRB Logical shift right accumulator B REV Rule Evaluation for 8-bits values TAB
accumulator B
LSRD Logical shift right accumulator D REVW Rule Evaluation for 16-bits values TAP Transfer accumulator A to CCR
Get maximum of 2 unsigned byte ROL Rotate memory left Transfer accumulator B to
MAXA TBA
in accumulator A ROLA Rotate left accumulator A accumulator A
Get maximum of 2 unsigned byte ROLB Rotate left accumulator B Test counter and branch if equal to
MAXM TBEQ
in memory zero
ROR Rotate right memory
MEM Membership function 8-Bit Table Lookup and
RORA Rotate right accumulator A TBL
Get minimum of 2 unsigned byte Interpolate
MINA RORB Rotate right accumulator B
in accumulator A Test counter and branch if not
RTC Return from call TBNE
Get minimum of 2 unsigned byte equal to zero
MINM RTI Return from interrupt
in memory TFR Transfer register to register
MOVB Memory to memory byte move RTS Return from subroutine TPA Transfer CCR to accumulator A
MOVW Memory to memory word move SBA Subtract accumulators TRAP Software interrupt
MUL 8*8-bit unsigned multiplication Subtract with carry from TST
SBCA Test memory
NEG accumulator A
Negate memory (2’s complement) TSTA Test accumulator A
Subtract with carry from
Negate accumulator A (2’s SBCB TSTB Test accumulator B
NEGA accumulator B
complement) TSX
SEC Set carry bit Transfer SP to index register X
Negate accumulator B (2’s TSY
NEGB SEI Set interrupt bit Transfer SP to index register Y
complement)
Set two’s complement overflow TXS Transfer index register X to SP
NOP No operation SEV
bit TYS Transfer index register Y to SP
ORAA Inclusive or with accumulator A
SEX Sign extend into 16-bit register WAI Wait for Interrupt
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