Low Power Design for Analog/Mixed-Signal

IP
Navraj Nandra, Synopsys
3/4/2008 10:21 AM EST
Introduction

Power reduction and management techniques using multiple clock and power domains,
dynamic voltage and frequency scaling and power gating are effective for digital circuits but
for analog design, lowering power consumption must be considered early in the design phase.
Starting with the techniques for lowering the power consumption in analog circuits such as
operational amplifiers, this article will then focus on low power design for high speed serial
interconnects. Different architectures for output drivers and methods such as level shifting,
for ac-coupled systems such as PCI Express®, SATA, and XAUI will be discussed. System
designers are influencing the specifications of high speed serial interconnects and a good
example of this can be seen with the emerging standards for the USB protocol - LPM and
HSIC. USB is prevalent as the high speed serial interconnect in portable devices such as
smart phones and mobile internet devices. The goal of Link Power Management (LPM) is to
reduce power consumption of USB devices and hosts, potentially extending battery life by at
least 20%. HSIC or "high speed inter-chip USB" allows low power high-speed data transfers
(480 Mbps) using a source synchronous clocked serial interface. Both will be reviewed in this
article.

Going Back To Basics " The Operational Amplifier

In the design of analog/mixed-signal IP many factors contribute to the overall consumption of

power. The common methods include:

• Simplifying the complexity of the circuit and using folded designs exploiting the
complementary properties of NMOS and PMOS devices.
• Taking conventional architectures and converting them into designs that consume less
power with adaptive biasing.
• Gearing the integrated circuit technology towards low power performance by using
high Vt processes for example 65 nm LP or 40 nm LP. Although this may not
necessarily reduce power in the active mode as more current is needed to drive the
high speed transmitter in the slower, low power technologies.
• Decreasing transistor dimensions together with lowering the supply voltage.

Before delving into power reduction techniques for high speed serial interfaces, consider the
case of an operational amplifier as the techniques applied here are pertinent to many other
circuit examples.

1. The power consumption of the operational amplifier can be reduced by use of an

architecture with only a single (differential) stage. This will reduce the current
consumption of the device. However, a method of maximizing the gain, whilst
 preserving an acceptable bandwidth and slew rate are now required in the single gain
stage.
2. The output stage could be designed to provide sufficient output drive while
quiescently consuming as little power as possible.
3. Optimizing the biasing circuit will reduce the power consumption in the op-amp. This
is achieved by reducing the internal stage currents by programming an external
current in the form of a resistor outside the integrated circuit. Speed, voltage noise and
junction leakage will now become major considerations for the designer as these
parameters are affected by the value of the bias current programmed.
4. Two important factors that determine the maximum power dissipation in an integrated
circuit are the technology used for the design and the type of application. A particular
application for CMOS op-amps could be low power switched capacitor filters. If a
lower power/low leakage CMOS technology such as 65LP or 40LP is used, then there
are two important requirements in the op-amp design. First there must be enough
current to charge the compensation capacitor and load capacitor in the required time.
Second there must be enough current in the second gain stage transistor to maintain a
phase margin of 45 to avoid ringing and degradation of the settling time. If the output
current of this circuit is less than the quiescent bias current then this is known as a
Class A circuit.
5. Quiescent power dissipation can be reduced by replacing Class A op-amps with Class
AB and dynamic op-amps. The Class AB output stage is designed to be biased at
small currents so quiescent power dissipation is correspondingly lower.
6. The basic two-stage differential input op-amp can be designed in the sub-threshold
current region to minimize the current consumption.

Scaling Issues “Is Analog Anti-Moore?

Whereas scaling of digital circuits is has been investigated in detail, the application of scaling
analog circuits is still not that common. For example typical transistor dimensions in an
analog circuit are a few multiples larger than 40 nm minimum channels.

The sub-threshold characteristics of devices with channel lengths below 2 μm are very
different to devices with larger dimensions. It has been observed that the current becomes
exponentially dependent on drain voltage independent of VDS. This effect is sometimes
referred to as "drain induced barrier lowering" (DIBL). If this effect can be avoided then
IDdecreases exponentially as VGS is reduced below VT.

Scaling devices, and reducing the supply voltage accordingly, will not degrade open circuit
voltage gain. Scaling dimensions but keeping supply voltage constant will, however, decrease
the gain. The dynamic range of circuits such as op-amps fall because the analog signal range
becomes limited due to the reduction in the power supply voltage. The problems of scaling
down include fabrication challenges, limitations in the design of devices and circuits and the
efficiency and distribution of power supplies.

Thermal noise will remain constant because the device transconductance remains constant
under constant field scaling. The 1/f noise intensifies, but the effect of this can be reduced by
translating the signal to a higher portion of the frequency spectrum, using chopper
stabilization.

Low Power Design Guidelines

A set of guide-lines can be developed for low power analog design, considering the op-amp
as an example: the biasing circuitry, input, output and compensation stages can be examined.

The DC biasing circuitry for the op-amp must provide accurately determined and suitably
regulated quiescent biasing currents at very low current levels. The current must be
insensitive to changes in temperature, supply voltage and process tolerances.

The configuration of the input stage will dictate whether the op-amp can be used in a single
low voltage (1.2 V, or lower) supply application. Therefore the following properties are
desirable (but not always possible) on a particular low power analog design:

• Very low power supply operation using core devices

• Class B or AB output stage " this reduces the quiescent power dissipation particularly
in a leaky process
• A rail to rail common mode input range
• A load-capacitance aware compensation scheme
• Capability to drive a small output load
• Bandwidth and slew rate commensurate with supply current
• Getting high precision by keeping offsets low, high input impedance, high CMRR and
high PSRR.

Low Power Design Example

The following is an example of a low-power, high-speed driver used in a USB 2.0 PHY.
Power is kept very low with the use of a voltage-mode driver, shown in Figure 1. A voltage-
mode driver draws 50% less current from the supply when compared to a conventional
current-mode driver shown in Figure 2. In fact, for AC-coupled systems such as PCI
Express®, SATA, and XAUI, a voltage-mode driver draws 25% of the supply current of a
current-mode implementation. For example, a classical USB 2.0 driver requires nominal
amplitude of 400 mV for high-speed data transmission into a 45-ohm load. The static power
dissipation from the supply for a current-mode driver is approximately 60 mW. Whereas, the
power dissipation from the supply for a voltage-mode driver is approximately 30 mW.

1. Simplified Voltage Mode Driver Implemented in Synopsys DesignWare USB 2.0 PHY.
 2. Schematics of a conventional USB 2.0 PHY Current-Mode Driver.

Another power-reduction technique is to optimize by level shifting down into the low-voltage
core device domain as early as possible in the signal path so that device characteristics are
leveraged as much as possible in order to reduce power. This strategy enables most high-
frequency analog signal processing to be done in the low-voltage domain (for example in the
USB, high-speed squelch detection and high speed receive function are implemented using
low voltage core devices).

Low-power design is also important in sleep modes (non-functional modes) especially for
mobile devices. For example, in the USB protocol the PHY can be held in suspend mode for
long periods of time. As a result the power dissipation in this mode can become a significant
portion of the total and must be scaled aggressively.

Power gating in digital circuits is often used where more aggressive power reduction is
necessary. Power gating helps reduce both channel and gate leakage by collapsing the supply
and eliminating the leakage current path. This can be implemented on a sub-block level by
implementing collapsible, thick-oxide regulators that can be disabled in low-power modes.

Digital supply leakage often dominates the power down current and so many SOC's collapse
the digital (core) supply rail in these modes as well. Doing so can cause serious side-effects
as analog level-shifters found in MSIP can often cause excessive current draw. Special care
in the design of level shifters found in MSIP is necessary to avoid this. One example includes
circuitry that detects when the digital power supply is collapsed; the circuitry then presets the
analog control signals to the IDDQ state thereby eliminating unwanted leakage current.

Emerging Low Power Standards For USB

For portable devices system designers are looking at ways to reduce power and one area
where power can be saved is using low power versions of USB. Two standards are emerging:
"Link Power Management" (LPM) and "High Speed Inter-chip USB" (HSIC).
LPM defines a new power sleep state between enable and suspend thereby conserving more
power than the present suspend/resume mode. Also sleep mode occurs more often and faster
reducing the transitional power states by three orders of magnitude. This reduces power
consumption of USB devices and hosts and potentially extending battery life by at least 20%
of the portable device.

HSIC is USB without the cable or the connector. It allows low power high-speed data
transfers (480 Mbps) using a source synchronous clocked serial interface. Low power is
achieved with 1.2 V LVCMOS signaling levels " that is there no 3.3 V signaling.

Summary
Novel circuit techniques can be used to reduce power significantly - enabling integration in
very low-power mobile applications. Power reduction techniques include investigating the
following:

1. Transmitter architectures
2. Analog signal processing in low-voltage domain
3. Sleep mode power reduction

Technology choice can impact power consumption although an LP technology may not
necessarily give the lowest power for high speed serial interconnects. From a systems
perspective applications that need to support low power embedded designs and portable
devices such as smart phones and mobile internet devices will require new standards such as
LPM and HSIC.

References:
"Building High-Quality, Mixed-Signal IP in 65-nm and Beyond" by Chong, Lam, Nandra,
Toffolon, IP07, December 2007.