Sie sind auf Seite 1von 4

Embedded Systems Interfacing

Overview
„ Interrupt mechanism
Interrupts „ Nesting of interrupt
„ Traps vs Hardware Interrupts
Embedded Systems Interfacing „ Example 1: Timer 1 Interrupt
„ Secondary Oscillator
„ Example 2: Timer 1 with Secondary
Oscillator
1 2

Interrupt Mechanism Interrupt Mechanism


„ An interrupt is an internal or external „ Processor state must be preserved [C-30
event that forces a hardware call to a compiler]
function called an interrupt service „ Interrupt service routine (ISR) must
routine. process data [user code]
„ Interrupt enable must be set [initialization] „ Interrupt flag must be cleared [user code]
„ Internal or external event forces interrupt „ Processor state must be restored [C-30
flag to be set [hardware] compiler]
„ Event forces routine at interrupt vector to
be called, see Table 5-1 [hardware]

3 4

C-30 Rules for ISR ISR Templates


„ ISR cannot return anything „ Template 1
void _ _attribute_ _ (( interrupt,no_auto_psv)) _T1Interrupt(void){
„ No parameters maybe passed to ISR // interrupt service routine code here … }
„ ISR may not be directly called by other „ Template 2
functions void _ISR _T1Interrupt(void){
// interrupt service routine code here … }
„ Ideally, ISR should not call other
function
• Template 1 preferred because it reduces latency.
• Template 2 inserts save/restore of PSVPAG register.

5 6

Copyright James Grover, 2008 1


Embedded Systems Interfacing

Interrupt Sources Interrupt Sources


„ 5 x external pins with level trigger „ 1 x Parallel Master Port
detection „ 5 x 16-bit timers (2 x 32-bit timers)
„ 22 x external pins connect to Change
„ 1 x Analog-to-digital converter
Notification module
„ 5 x input capture modules „ 1 x Analog comparator module
„ 2 x serial port interfaces (UARTs) „ 1 x Real-time clock and calendar
„ 4 x synchronous serial interfaces (SPI „ 1 x Cyclic redundancy check generator
and I2C)

7 8

Traps Real Example with Timer1


„ Generated by processor fault conditions // 32 MHz fosc or Tcyc = 62.5 ns
„ Non-maskable interrupts volatile int dSec = 0; //decisecond
volatile int Sec = 0; //second
„ Sources volatile int min = 0; //minute
„ Oscillator failure
„ Address error void _ISR_ _T1Interrupt(void)
„ Stack error dSec++
if(dSec > 9) {
„ Math error dSec = 0;
„ Reserved (four) Sec++;
if(Sec > 59) {
9
Sec = 0; 10

Real Example with Timer1 Real Example with Timer1


int main(void) {
Sec = 0; _T1IP = 4;
Min++; TMR1 = 0;
if(Min > 59){ PR1=25000-1;
TRISA = 0xff00; Initialization
Min = 0;
T1CON = 0x8020; // 1:64 prescaler
} _T1IF=0;
} _T1IE=1;
} _IPL = 0;
_T1IF = 0; while(1) {
PORTA = Sec; Endless Loop
}
}
return(0);
}
11 12

Copyright James Grover, 2008 2


Embedded Systems Interfacing

Secondary Oscillator Modified for Secondary Osc.


„ Timer1 has //Use similar code to Interrupt.C except
„ External clock input or T1CON = 0x8002;
„ Amplifier with feedback to be used with external PR1 = (32 x 1024) –1;
crystal (resonator)
„ Inexpensive 32,768 resonator are available
„ Configure Timer1 for external crystal
(resonator)
„ Set PR1 to 32768-1
„ Produces interrupt once per second

15 16

Real-Time Clock Calendar Managing Multiple Interrupt


„ Available in 16-Bit „ Year on specified day „ Most real applications have two or more
and 32-Bit PICs of year interrupt sources
Four years for 29
Interrupt once every Keep each ISR as short as possible
„
„ „
February
„ Second Use priority levels to determine event
„ All counting done in „
„ Minute that will be serviced first in case of
hardware (not
„ Hour coincidental interrupt events
software)
Day
Nested interrupt require much more
„

Week
„ See next set of „
care ( _NSTDIS = 1 to disable nesting)
„

„ Month
slides for details

17 18

Additional Info Additional Info


„ C-30 has two interrupt vector tables „ No global interrupt disable
„ One for normal program execution „ __asm__ volatile(“disi #0x0007”);
„ Second one for debugging will disable all interrupts for 7 TCYC
„ The _ISRFAST macro will allow register „ __asm__ volatile(“disi #0x3FFF”);
will disable all interrupts for very long
swapping for critical registers for faster
time (16383 TCYC)
processor state save and restore
„ DISICNT = 0;
will re-enable all interrupts

19 20

Copyright James Grover, 2008 3


Embedded Systems Interfacing

Additional Info Homework #6


„ To use secondary oscillator you must „ Chapter 5 -- Handout
set SOSCEN bit (see text for necessary „ 1 Bit Bang Serial Port
code)
„ Secondary oscillator cannot be
simulated with MPSIM „ 2 Bit Bang Slave Synchronous Peripheral
„ To set current time and date you must Interface
set RTCWREN bit (see text for 7 6 5 4 3 2 1 0
necessary code) RA2 RA1

datum
21 23

Copyright James Grover, 2008 4

Das könnte Ihnen auch gefallen