Graphene for Electronic Applications – Transistors and More

F. Schwierz

Technical University Ilmenau, PF 100565, 98684 Ilmenau, Germany

Abstract — During the last five years, the new use graphene MOSFETs in real applications. We
material graphene has gained increasing attention in the discuss this issue subsequently for MOSFETs to be
device community. The progress in the development of used in digital logic and for RF MOSFETs.
graphene transistors is breathtaking and graphene-
based devices are now considered as an option for a
Modern logic is based on Si CMOS
post-Si electronics. However, to realistically assess the (complementary MOS) comprising both n-channel
potential of graphene, the existing problems with and p-channel MOSFETs. Complex logic ICs
graphene and the options to solve them have to be (integrated circuit) consist of many cascaded
analyzed carefully. The present paper provides an individual logic gates (e.g., NAND, NOR), where the
overview of the current status of graphene transistor output signal of one gate serves as the input for the
development and discusses the prospects and problems
of these devices.
ensuing gates. The cascaded gate arrangement
requires the restoration of the signal levels to ensure
that a logic gate can reliably identify if it receives a
Index Terms — Graphene, bandgap, carrier
transport, mobility, MOSFET, RF transistor, transistor. logic 1 or 0 at its input.
As shown in Fig. 1, CMOS logic gates consist of
an n-channel branch connected to ground and a p-
I. INTRODUCTION channel branch connected to the supply voltage VDD.
Only once in a blue moon, a single paper ignites a The beauty of CMOS is that it provides ideal signal
revolution in solid-state physics. Precisely this came restoration combined with the property that in steady-
about, however, when in October 2004 researchers of state, regardless of the input signals, always one of
the two branches is off and no current – except a
the University of Manchester reported on the
small off-current – can flow from VDD to ground.
preparation of a material called graphene and on the
Thus, Si CMOS offers ultimately low static power
observation of the field-effect in their samples [1].
dissipation and noticeable power is only dissipated
Since than, the interest in graphene literally exploded,
during switching.
and physicists and device engineers became intrigued
by this material [2-3]. Graphene is indeed fascinating,
yet due to the predominantly euphoric appraisal of the
potential of this material, its prospects in electronics
are frequently assessed overly optimistic.
Since so far most work on graphene devices was
related to MOSFETs (metal-semiconductor-oxide
field-effect transistor), in the present paper we focus
on the properties of graphene relevant to MOSFETs
and on the current state-of-the-art of graphene
MOSFETs. However, other options to use graphene
in electronics will also be touched.

II. IS MOSFET SWITCH-OFF INDISPENSABLE?

Conventional FETs show a reasonably good
switch-off behavior and an exponential dependence
of the drain current on the gate voltage in the
subthreshold region. This results in on-currents Ion
several orders of magnitude larger compared to the
currents in the off-state Ioff, and thus in large on-off
ratios Ion/Ioff. Key to this behavior is a semiconducting
FET channel having a sizeable bandgap. Large-area
graphene, however, is a zero-gap material. This leads
to the situation that MOSFETs with large-area
graphene channels cannot be switched off and the
question arises whether or not switch-off is needed to
978-1-4244-8579-6/10/$26.00 ©2010 IEEE
Fig. 1. Basic principle of CMOS on the example of a
NAND gate. If, for instance, the signal at input 1 (at the
gate terminals of transistors T1 and T3) is a logic 1 (Vin1 =
VDD) and that at input 2 is a logic 0 (Vin2 = 0), the
MOSFETs T1 and T4 are on while T2 and T3 are off. Since
T2 is off, the n-channel branch is off and no current can
flow from VDD to ground. For any possible combination of
input signals one branch of the NAND gate is off.
173
 This issue is extremely important since power shows very high mobilities. In exfoliated graphene,
dissipation and the resulting self-heating is a major mobilities in excess of 10,000 cm2/Vs are routinely
problem of complex logic ICs, such as high- measured and for ideal graphene mobilities of
performance microprocessors. Si CMOS has 200,000 cm2/Vs are predicted [9].
superseded all other competing logic technologies
4
due to its low static power dissipation. Thus, a FET- 10
3p+1
based successor for Si CMOS will need transistors 3p
able to switch off. This can only be achieved if the 3
3p+2
10
FET channel is semiconducting having a reasonably

Bandgap (meV)
wide bandgap, preferably 0.4 eV or more. In other
words, gapless large-area graphene channels are not 10
2

suitable for logic FETs and ways to open a gap in Experiment

Han
graphene have to be found (and have been found as Li
Theory
we will show later). 10
1 Yang - Ideal ac GNRs
Yang - Extrapolation ideal 3p+1 ac GNRs
The situation is different in RF (radio frequency) Yang - Ideal zz GNRs

applications. Here, switch-off is not required per se.

Let us consider, for example, a small-signal low-noise 10
0

amplifier. In such a circuit, the FET is permanently
operated in the on-state and the small RF signals to be
amplified are superimposed onto the dc gate voltage.
To summarize we state that (i) for graphene
transistors to be used in a CMOS-like logic, switch-
off is indispensable and a semiconducting channel is
needed, and (ii) for RF graphene MOSFETs the
ability to switch off would certainly be useful but is
not mandatory.
III. PROPERTIES OF GRAPHENE
Single-layer graphene is a purely two-dimensional
material with a lattice consisting of regular hexagons
with one carbon atom at each corner. By nature,
large-area graphene is gapless, but several approaches
to create a gap in graphene are explored. Most
popular is constraining one dimension of large-area
graphene thus forming narrow GNRs (graphene
nanoribbon) [4-5], while a second option is biasing
0.1 1 10 100
GNR width (nm)
Fig. 2. Calculated and measured GNR bandgap as a
function of ribbon width, after [3]. Stars: experimental data
[4-5], triangles: simulation [7].
On the other hand, theoretical investigations
suggest that the gap opening in narrow GNRs will be
accompanied by a dramatic mobility reduction. This
is not a big surprise since a decreasing mobility for
increasing bandgap is a well known trend for
semiconductors. This trend is indicated in Fig. 3
showing the electron mobility in several conventional
semiconductors, Si nanowires, carbon nanotubes,
large-area graphene, and GNRs.
10
6 Large-area graphene
GNRs
CNTs (sim, exp)

bilayer graphene [6]. The two ideal GNR types are

Electron mobility (cm /Vs)

Ge (bulk
5
10 Si (bulk)
armchair (ac) and zigzag (zz) nanoribbons. It has
2

Si MOS
been predicted that both these GNR configurations Si nanowires
III-Vs (bulk)
show a bandgap EG that depends on the GNR width w 10
4 SiC (bulk)

roughly according to EG ∝ 1/w [7].

The gap opening has been verified experimentally
for GNRs with widths down to about 1 nm [4-5]. It 10
3

should be noted, however, that experimental GNRs

do not have ideal armchair or zigzag edges but 2
10
possess rough non-regular edges instead. Already 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
modest edge disorder obliterates any difference in the Bandgap (eV)
gap between GNRs of different edge geometry [8].
Figure 2 shows a compilation of reported theoretical Fig. 3. Electron mobility vs. bandgap. Black circles: III-
and experimental data for the bandgap of GNRs as a V compounds, from left to right InSb, InAs, In0.53Ga0.47As,
function of GNR width. It can be seen that, to get a InP, GaAs, In0.49Ga0.51P, GaN. Blue squares and blue lines:
carbon nanotubes, simulated [10-11]. Open blue circle:
gap of about 0.4 eV, very narrow GNRs with a width carbon nanotube, experiment [12]. Red diamonds: Si
around/below 10 nm are needed. nanowires, simulated [13]. Magenta stars and line: large-
We now move to the discussion of carrier transport area graphene [9, 14-16]. Light blue area: GNRs, simulated
and start with the mobility. Most frequently the high [17-18]. Green triangle (up), red full and open triangles
carrier mobility is stated to be the major advantage of (down): bulk Ge, bulk Si and Si MOS channels.
graphene. Indeed, large-area (but gapless) graphene
174
 Figure 3 indicates that for a given bandgap,
graphene does not offer a distinct advantage in terms
of electron mobility compared to the more
conventional semiconductors. Less frequently the
high-field transport in graphene is discussed.
Simulations have shown that graphene shows much
higher electron velocities at high fields (around 4 ×
107 cm/s [19-20]) than the conventional materials.
Note that at high fields, the electron saturation
velocity in Si and in most of the III-V compounds is
only around 107 cm/s.
Graphene offers another feature that is highly
desirable for MOSFETs. Aggressively scaled Si
MOSFETs with nm gates are known to suffer from
short-channel effects, such as threshold voltage roll-
off, drain-induced barrier lowering, and impaired
saturation of drain currents [21-22]. The scale length
theory predicts that a MOSFET having a thin gate
dielectric and a thin gate-controlled channel region
will be robust against short-channel effects [23].
Since graphene offers the thinnest possible MOSFET
channels (only one atomic layer thick), nm-gate
graphene MOSFET are expected to be very robust
against short-channel effects and probably will be
scalable beyond the limits of Si MOSFETs. It is
important to note, however, that the scale length
concept is valid only for MOSFETs having a
semiconducting channel. Thus, our statement
regarding the scalability does not apply to graphene
MOSFETs with gapless channels.
IV. GRAPHENE TRANSISTORS
The currently most popular approaches to prepare
graphene for electronic applications are (i)
mechanical exfoliation of pyrolytic graphite [1], (ii)
epitaxial graphene growth on metals and subsequent
transfer of the grown graphene to insulating
substrates [24], and (iii) thermal decomposition of
SiC [25]. It should be noted that, although method (ii)
involves epitaxy while method (iii) is not a true
epitaxial process (since no material is deposited but
rather Si is removed from the surface of SiC wafers),
graphene produced by method (iii) is commonly
called epitaxial graphene. Method (i), i.e., exfoliation,
is still popular for lab purposes but not suited to the
semiconductor industry since it is extremely labor-
intensive and provides graphene flakes of only
limited size (several µm × several µm). The other two
methods, however, have the potential for the
production of wafer-scale graphene. Once the
graphene layer is produced, well-established
semiconductor processing technology (lithography,
etching, layer deposition, etc.) can be applied to
fabricate graphene transistors.
A growing number of groups are now successfully
fabricating different versions of graphene MOSFETs
175
with graphene channels produced by one of the
methods mentioned above:
- Back-gated graphene MOSFETs with either
gapless large-area graphene channels, e.g., [1,
26] or narrow semiconducting GNR channels
[7, 27]. Back-gate MOSFETs are easy to
fabricate and useful for proof-of-concept
purposes but are not suitable for practical
applications.
- Top-gated MOSFETs with either gapless large-
area graphene channels [24, 28-34] or narrow
GNR channels [35].
We start the discussion with MOSFETs having
gapless large-area graphene channels. So far, these
transistors constitute the majority of experimental
graphene devices. As mentioned above, the gapless
channels of these transistors cannot be switched off.
Figure 4 shows the transfer characteristics of a top-
gate graphene MOSFET with a large-area epitaxial
graphene channel on SiC. It can clearly be seen that
this transistor does not switch off. For negative gate
voltages, the transistor has a p-type channel, at the
Dirac point (the point of minimum drain current) the
conductivity type of the channel switches from p- to
n-type, and for positive gate voltages the transistor
behaves as an n-channel FET.
Fig. 4. Transfer characteristics of a graphene MOSFET with
large-area epitaxial graphene channel [32]. The point of
minimum drain current is called the Dirac point. © IEEE
2008.
While due to the missing switch-off MOSFETs
with gapless large-area graphene channels are not
suitable for logic applications, they may be useful for
RF applications, and indeed significant efforts have
been spent on investigating (and improving) the RF
performance of these transistors.
As an example, Fig. 5 shows information on a top-
gate graphene MOSFET reported by an IBM group
[34]. The channel consists of exfoliated graphene
deposited on a SiO2-covered (300 nm) Si wafer
serving as a back-gate. The top-gate dielectric is a 12-
nm Al2O3 layer. As shown in Fig. 5c, the output
characteristics of this transistor do not show a
saturation of the drain current. In [3] it has been
discussed in detail that a FET should be operated in
drain current saturation to exploit the full high-speed
potential of the channel material. In spite of the
missing current saturation, the transistor from Fig. 5
shows a remarkably high cutoff frequency fT of 50
GHz.
Figure 6 compares the cutoff frequency of
experimental graphene MOSFETs (all with gapless
large-area graphene channels) with the best fT values
reported for other types of RF FETs: InP HEMTs
(high electron mobility transistor), GaAs mHEMTs
(metamorphic HEMT), Si MOSFETs, GaAs pHEMTs
(pseudomorphic HEMT). So far, the fastest (in terms
of fT) graphene transistors are a 240-nm gate
graphene MOSFET showing an fT of 100 GHz and a
transistor with an fT of 53 GHz and a 550-nm gate
[25].
Fig. 5. Details of a 350-nm gate graphene MOSFET
reported by an IBM group [34]. (a) cross-section, (b)
layout, (c) output characteristics, (d) small-signal current
gain vs. frequency and cutoff frequency. © IEEE 2010.
The reported record fT data for the competing RF
FET types are as follows: 660 GHz for a 20-nm gate
GaAs mHEMT [37], 628 GHz for a 30-nm gate InP
HEMT [38], 485 GHz for a 29-nm gate Si MOSFET
[39], and 152 GHz for a 100-nm gate GaAs pHEMT
[40]. For comparison, the fastest carbon nanotube
MOSFET reported so far has a 300-nm gate and
shows an fT of 80 GHz [41].
As can be seen from Fig. 6, in terms of cutoff
frequency the best graphene MOSFETs already
outperform the fastest Si MOSFETs with comparable
gate length and aggressively attack the GaAs
176
pHEMTs. Compared to the many reported fT data of
graphene MOSFETs, much less experimental data on
the maximum frequency of oscillation fmax has been
published so far. Current the record fmax for a
graphene MOSFET is 14 GHz [25]. So far, no data on
the RF noise performance of graphene transistors is
available.
Due to the fast improvement of the high-speed
performance of graphene MOSFETs during the last
two years (note that the first graphene MOSFET with
GHz operation has been reported in late 2008 [30]),
we expect significant further enhancement of the RF
performance of graphene MOSFETs in the nearest
future.
1000
Cutoff frequency (GHz)
100
Record Graphene FETs
240-nm gate, 100 GHz fT
550-nm gate, 53 GHz fT
10
InP HEMT, GaAs mHEMT
Si MOSFET
GaAs pHEMT
Graphene FET
1
0.01 0.1 1 2
Gate length (µm)
Fig. 6. Cutoff frequency vs. gate length for different RF
FET types. The symbols indicate experimental data
compiled from the literature [36] and the lines are a guide
for the eye. Red open circles: GaAs mHEMTs and InP
HEMTs, blue full circles: Si MOSFETs, green triangles:
GaAs pHEMTs, stars: graphene MOSFETs.
Back-gate MOSFETs with narrow GNR channels
(GNR width down to less than 5 nm) have been
reported [7, 27]. These transistors showed excellent
switch-off (on-off ratios up to 106) and provided
evidence for the suitability of GNR MOSFETs for
logic applications. Recently also the first GNR
MOSFET with top-gate has been demonstrated [35].
The on-off ratio of this transistor is around 70 which
significantly exceeds the on-off ratios of MOSFETs
with large-area graphene channels (typically 2…20)
but is still too low for logic application where on-off
ratios of 104 to 107 are required [42]. The GNR
channel of this transistor was about 10-20 nm wide
and apparently did not offer a bandgap wide enough
to sufficiently suppress the off-current. However, a by
further reduction of the ribbon width we can expect
much better on-off ratios of top-gated GNR
MOSFETs in the near future. So far, experimental
data on the dynamic behavior (e.g., on the cutoff
frequency or the switching delay) of GNR MOSFETs
is not available.
 The graphene transistor discussed so far are based
on the conventional MOSFET principle, i.e.,
controlling the carrier concentration and thus the
channel conductivity by the applied gate voltage. In
spite of the impressing performance obtained with
experimental devices we have seen that these
"conventional" graphene MOSFETs suffer from
several fundamental problems. Some of these are: (i)
the loss of mobility in narrow GNRs, (ii) the need of
extremely narrow GNRs (only a very few nm wide)
to open a gap useful for switch-off, (iii) the
unsatisfying drain current saturation of graphene
MOSFETs with large-area graphene channels. This
has motivated research on novel graphene-based FET
concepts. Two examples, that have already gathered
considerable attention in the device community, are
the graphene tunnel FET [43] and the graphene
BiSFET (Bilayer PseudoSpin FET) [44]. Although
these two transistor concepts are still at an embryonic
stage, they already found their way into the Emerging
Research Devices section of the most recent issue of
the ITRS [42].
V. ARE GRAPHENE BIPOLAR TRANSISTORS AN
OPTION?
The FETs we discussed in the previous Section did
not use intentionally doped graphene. However,
graphene can be doped and both n-type and p-type
graphene can be realized [44-45]. Thus, in principle
bipolar graphene transistors are imaginable. However,
due to the purely two-dimensional structure of
graphene, these devices should involve lateral npn (or
pnp) structures. This in turn would require the base
dimensions to be defined by lithography. In common
bipolar transistors, the critical device dimension in the
direction of current flow is the base thickness, i.e., a
vertical dimension defined by the thickness of an
epitaxially grown layer in heterojunction bipolar
transistors or the thickness of an implanted region in
homojunction bipolar transistors. Thus, a graphene
bipolar transistor would suffer from the limitations of
conventional lateral bipolar transistors, most notably
a wide base. So far, no reports on graphene bipolar
transistors could be found in the literature.
VI. FURTHER POSSIBLE APPLICATIONS OF GRAPHENE
Since large-area graphene is gapless and behaves
like a semimetal, it may be used for interconnects.
This would open the possibility of all-graphene ICs
with both the active devices and the wiring made of
graphene [47-48]. This vision has stirred more
detailed investigations on the potential of graphene
for use as interconnect. It has been shown that
graphene interconnects show comparable or even
better performance compared to copper interconnects
at room temperature [49-51] and that graphene can
177
support current densities in excess of 108 A/cm2 [52].
Note that this is two orders of magnitude more than
the current density supported by copper and
comparable with that supported by carbon nanotubes.
Graphene devices for sensing applications look
also promising. Graphene virtually consists only of
surface without a bulk and therefore should be very
sensitive to its environment. Graphene sensors able to
detect single gas molecules have been reported [53].
Another possible class of sensor devices is graphene-
based NEMS (nano electromechanical system) that
benefit from the superior mechanical properties and
the extremely small mass of graphene [54].
VII. CONCLUSION
During the past 30 months, we have witnessed
huge progress in the development of graphene
transistors. Most impressing was the demonstration of
a 100 GHz fT graphene MOSFETs and of the
excellent switching behavior of MOSFETs with
narrow GNR channels. The progress has been
accompanied, however, by the exposure of numerous
problems. Due to the missing gap, MOSFETs with
large-area channels cannot be switched off and
therefore are not suited for logic applications.
Moreover, they show an unsatisfying drain current
saturation behavior limiting the RF performance.
Another problem is the fact that so far the extremely
narrow GNRs needed to open a useful gap face
serious fabrication issues.
Currently it seems that the biggest advantage of
graphene MOSFETs may not be, as commonly stated,
the high mobility but rather the ultimately thin
channel and the resulting ultra-short scale length.
Experiences from the past have shown that RF
chipmakers are more open to novel device and
material concepts than chipmakers in Si mainstream
VLSI electronics. Therefore, graphene might make its
first appearance in RF applications rather than in
logic circuits [3].
When assessing the prospects of graphene in
electronics, it is important to recognize that all other
options considered as possible successors of the
conventional mainstream transistors also face serious
problems. Concepts that have been investigated
already for many years, such as spin transistors or
molecular devices, seem to be farther from
applications than graphene transistors, and it is not
clear if they will ever reach the production stage. At
the moment it is impossible to assess which of the
alternative device concepts, if any, has the potential to
replace Si MOSFETs and III-V HEMTs. The race is
still open and the chances for electronic graphene
devices are at least as promising as those of other
device concepts. The commercialization of graphene-
based devices and ICs in the near future, however, is
not likely.
 ACKNOWLEDGEMENT
This work was financially supported by the 2008-
2009 Excellence Research Grant of TU Ilmenau.
REFERENCES
[1] K. S. Novoselov et al., “Electric field effect in
atomically thin carbon films”, Science, vol. 306, pp.
666-669, 2004.
[2] A. K. Geim and K. S. Novoselov, “The rise of
graphene”, Nature Mater., vol. 6, pp. 183-191, 2007.
[3] F. Schwierz, “Graphene transistors” Nature Nanotech.,
vol. 5, DOI: 10.1038/NNANO.2010, to appear in the
printed version in the July issue, 2010.
[4] M. Han et al., “Energy band-gap engineering of
graphene nanoribbons”, Phys. Rev. Lett., vol. 98, p.
206805, 2007.
[5] X. Li et al., “Chemically derived, ultrasmooth
graphene nanoribbon semiconductors”, Science, vol.
319, pp. 1229-1232, 2008.
[6] E. V. Castro et al., “Biased bilayer graphene:
Semiconductor with a gap tunable by the electric field
effect”, Phys. Rev. Lett., vol. 99, p. 216802, 2007.
[7] L. Yang et al., “Quasiparticle energies and band gaps
in graphene nanoribbons”, Phys. Rev. Lett., vol. 99, p.
186801, 2007.
[8] M. Evaldsson et al., “Edge-disorder-induced Anderson
localization and conduction gap in graphene
nanoribbons”, Phys. Rev. B, vol. 78, p. 161407, 2008.
[9] S. V. Morozov et al., “Giant intrinsic carrier mobilities
in graphene and its bilayer”, Phys. Rev. Lett., vol. 100,
p. 016602, 2008.
[10] X. Zhou et al., “Band structure, phonon scattering, and
performance limit of single-walled carbon nanotube
transistors”, Phys. Rev. Lett., vol. 95, p. 146805, 2005.
[11] V. Perebeinos, J. Tersoff, and Ph. Avouris, “Electron-
phonon interaction and transport in semiconducting
carbon nanotubes”, Phys. Rev. Lett., vol. 94, p.
0786802, 2005.
[12] G. Pennington and N. Goldsman, “Low-field
semiclassical transport in semiconducting carbon
nanotubes”, Phys. Rev. B, vol. 71, p. 205318, 2005.
[13] S. Jin, M. V. Fischetti, and T.-W. Tang, “Modeling of
electron mobility in gated silicon nanowires at room
temperature: Surface roughness scattering, dielectric
screening, and band nonparabolicity”, J. Appl. Phys.,
vol. 102, p. 083715, 2007.
[14] J.-H. Chen et al., “Intrinsic and extrinsic performance
limits of graphene devices on SiO2”, Nature
Nanotechnol., vol. 3, pp. 206-209, 2008.
[15] F. Chen et al., “Dielectric screening enhanced
performance in graphene FET”, Nano Lett., vol. 9, pp.
2571-2574, 2009.
[16] A. Geim, “Graphene update”, http://meetings.aps.org/
link/BAPS.2010.MAR.J21.4.
[17] B. Obradovic et al., “Analysis of graphene
nanoribbons as a channel material for field-effect
transistors”, Appl. Phys. Lett., vol. 88, p. 142102,
2006.
178
[18] T. Fang et al., “Mobility in semiconducting
nanoribbons: Phonon, impurity, and edge roughness
scattering”, Phys. Rev. B, vol. 78, p. 205403, 2008.
[19] A. Akturk and N. Goldsman, “Electron transport and
full-band electron-phonon interactions in graphene”, J.
Appl. Phys., vol. 103, p. 053702, 2008.
[20] R. S. Shishir and D. K. Ferry, “Velocity saturation in
intrinsic graphene”, J. Phys.: Cond. Matter, vol. 21, p.
344201 (2009).
[21] Y. Taur and T. H. Ning, Fundamentals of Modern
VLSI Devices, Cambridge University Press, Cambridge
1998.
[22] F. Schwierz, H. Wong, and J. J. Liou, Nanometer
CMOS, Pan Stanford Publishing, Singapore 2010.
[23] D. J. Frank, Y. Taur, and H.-S. P. Wong, “Generalized
scale length for two-dimensional effects in
MOSFETs”, IEEE Electron Device Lett., vol. 19, pp.
385-387, 1998.
[24] J. Kedzierski et al., “Graphene-on-insulator transistors
made using C on Ni chemical-vapor deposition”, IEEE
Electron Device Lett., vol. 30, pp. 745-747, 2009.
[25] Y.-M. Lin et al., “100-GHz transistors from wafer-
scale epitaxial graphene”, Science, vol. 327, p. 662,
2010.
[26] C. Hummel et al., “Ambient and temperature
dependent electric properties of backgate graphene
transistors”, phys. stat. sol. B, vol. 247, pp. 903-906,
2010.
[27] X. Wang et al., “Room-temperature all-
semiconducting sub-10-nm graphene nanoribbon field-
effect transistors”, Phys. Rev. Lett., vol. 100, p.
206803, 2008.
[28] M. C. Lemme et al., “A graphene field-effect device”,
IEEE Electron Device Lett., vol. 28, pp. 282-284,
2007.
[29] Y.-M. Lin et al., “Operation of graphene transistors at
gigahertz frequencies”, Nano Lett., vol. 9, pp. 422-426,
2009.
[30] I. Meric et al., “RF performance of top-gated, zero-
bandgap graphene field-effect transistors”, Tech. Dig.
IEDM, p. 21.2, 2008.
[31] I. Meric et al., “Current saturation in zero-bandgap,
top-gated graphene field-effect transistors”, Nature
Nanotech., vol. 3, pp. 654-659, 2008.
[32] J. Kedzierski et al., “Epitaxial graphene transistors on
SiC substrates”, IEEE Trans. Electron Devices, vol.
55, pp. 2078-2085, 2008.
[33] J. S. Moon et al., “Epitaxial-graphene RF field-effect
transistors on Si-face 6H-SiC substrates”, IEEE
Electron Device Lett., vol. 30, pp. 650-652, 2009.
[34] Y.-M. Lin et al., “Dual-gate graphene FETs with fT of
50 GHz”, IEEE Electron Device Lett., vol. 31, pp. 68-
70, 2010.
[35] L. Liao et al., “Top-gated graphene nanoribbon
transistors with ultrathin high-k dielectrics”, Nano
Lett., vol. 10, pp. 1917-1921, 2010.
[36] F. Schwierz, “Microwave Transistors: State of the art
in the 1980s, 1990s, and 2000s – A compilation of
1000 top references”, TU Ilmenau, unpublished, 2010.
[37] M. Schlechtweg, Private communication, 2010.
[38] D.-H. Kim and J. A. del Alamo, 30-nm InAs
pseudomorphic HEMTs on InP substrate with a
current-gain cutoff frequency of 628 GHz, IEEE
Electron Device Lett., vol. 29, pp. 830-833, 2008.
[39] S. Lee et al., “Record RF performance of 45-nm SOI
CMOS technology”, Tech. Dig. IEDM, pp. 255-258,
2007.
[40] L. D. Nguyen et al., “Characterization of ultra-high-
speed AlGaAs/InGaAs (on GaAs) MODFETs”, IEEE
Trans. Electron Devices, vol. 36, pp. 2243-2248, 1989.
[41] L. Nougaret et al., “80 GHz field-effect transistors
produced using high purity semiconducting single-
walled carbon nanotubes”, Appl. Phys. Lett., vol. 94, p.
243505, 2009.
[42] The International Technology Roadmap for
Semiconductors ITRS, 2009 edition, Semiconductor
Industry Association (2009). See also at
http://www.itrs.net/Links/2009ITRS/Home2009.htm.
[43] G. Iannoccone et al., “Perspectives of graphene
nanoelectronics: Probing technological options with
modeling”, Tech. Dig. IEDM, pp. 245-248, 2009.
[44] S. K. Banerjee, et al., “Bilayer pseudospin field-effect
transistor (BiSFET): A proposed new logic device”,
IEEE Electron Device Lett., vol. 30, pp. 158-160,
2009.
[45] S. S. Yu, W. T. Zheng, and Q. Jiang, “Electronic
properties of nitrogen-/boron-doped graphene
nanoribbons with armchair edges”, IEEE Trans.
Nanotechnol., vol. 9, pp. 78-81, 2010.
[46] Y.-C. Lin, C.-Y. Lin, and P.-W. Chiu, “Controllabe
graphene N-doping with ammonia plasma”, Appl.
Phys. Lett., vol. 96, p. 133110, 2010.
[47] C. Berger et al., “Electronic confinement and
coherence in patterned epitaxial graphene”, Science,
vol. 312, pp. 1191-1196, 2006.
[48] R. Van Noorden, “Moving towards a graphene world”,
Nature, vol. 442, pp. 228-229, 2006.
[49] A. Naeemi and J. D. Meindl, “Conductance modeling
for graphene nanoribbon (GNR) interconnects”, IEEE
Electron Device Lett., vol. 28, pp. 428-431, 2007.
[50] C. Xu and K. Banerjee, “Graphene nano-ribbon (GNR)
interconnects: A genuine contender or a delusive
dream?”, Tech. Dig. IEDM, p. 8.5, 2008.
[51] R. Murali et al., “Resistivity of graphene nanoribbon
interconnects”, IEEE Electron Device Lett., vol. 30,
pp. 611-313, 2009.
[52] J. Moser, A. Barreiro, and A. Bachtold, Current-
induced cleaning of graphene, Appl. Phys. Lett., vol.
91, p. 163513, 2007.
[53] F. Schedin et al., “Detection of individual gas
molecules adsorbed on graphene”, Nature Materials,
vol. 6, pp. 652-655, 2007.
[54] J. S. Bunch, “Electromechanical resonators from
graphene sheets”, Science, vol. 315, pp. 490-493,
2007.

179