Beruflich Dokumente
Kultur Dokumente
• Introduction
• Fault models
– Stuck-line (single and multiple)
– Bridging
– Stuck-open
• Test pattern generation
– Combinational circuit test generation
– Sequential circuit test generation
Outline
• Testing
– Logic Verification
– Silicon Debug
– Manufacturing Test
• Fault Models
• Observability and Controllability
• Design for Test
– Scan
– BIST
• Boundary Scan
1
Testing
• Testing is one of the most expensive parts of chips
– Logic verification accounts for > 50% of design effort
for many chips
– Debug time after fabrication has enormous cost
– Shipping defective parts can sink a company
Logic Verification
• Does the chip simulate correctly?
– Usually done at HDL level
– Verification engineers write test bench for HDL
• Can’t test all cases
• Look for corner cases
• Try to break logic design
• Ex: 32-bit adder
– Test all combinations of corner cases as inputs:
• 0, 1, 2, 231-1, -1, -231, a few random numbers
• Good tests require ingenuity
2
Silicon Debug
• Test the first chips back from fabrication
– If you are lucky, they work the first time
– If not…
• Logic bugs vs. electrical failures
– Most chip failures are logic bugs from inadequate simulation
– Some are electrical failures
• Crosstalk
• Dynamic nodes: leakage, charge sharing
• Ratio failures
– A few are tool or methodology failures (e.g. DRC)
• Fix the bugs and fabricate a corrected chip
Shmoo Plots
3
Need for Testing
• Physical defects are likely in manufacturing
– Missing connections (opens)
– Bridged connections (shorts)
– Imperfect doping, processing steps
– Packaging
• Yields are generally low
– Yield = Fraction of good die per wafer
• Need to weed out bad die before assembly
• Need to test during operation
– Electromagnetic interference, mechanical stress, electromigration,
alpha particles
Manufacturing Test
• A speck of dust on a wafer is sufficient to kill chip
• Yield of any chip is < 100%
– Must test chips after manufacturing before delivery to
customers to only ship good parts
• Manufacturing testers are
very expensive
– Minimize time on tester
– Careful selection of
test vectors
4
Testing Your Chips
• If you don’t have a multimillion dollar tester:
– Build a breadboard with LED’s and switches
– Hook up a logic analyzer and pattern generator
– Or use a low-cost functional chip tester
5
XBox 360 Technical Problems and
Test-Cost Projections
• July 5, 2007, Xbox issues to cost Microsoft $1 billion-plus.
Unacceptable number of repairs leads to company extending
warranties.
• Matt Rosoff, an analyst at the independent research group Directions
on Microsoft, estimates that Microsoft’s entertainment and devices
division has lost more than $6 billion since 2002.
Manufacturing
cost
Test cost
ITRS
Cost of Test
• “The emergence of more advanced ICs and SOC semiconductor devices is
causing test costs to escalate to as much as 50 percent of the total
manufacturing cost.”
– M. Kondrat, “Bridging design and ATE cuts test cost - Test & Measurement -
automatic test equipment”, Electronic News, Sept 9, 2002.
• “As a result, semiconductor test cost continues to increase in spite of the
introduction of DFT, and can account for up to 25-50% of total
manufacturing cost”.
– T. Cooper, G. Flynn, G. Ganesan, R. Nolan, C. Tran, Motorola,
“Demonstration and Deployment of a Test Cost Reduction Strategy Using
Design-for-Test (DFT) and Wafer Level Burn-In and Test”, (6/29/2001) Future
Fab Intl. Volume 11.
• “Test may account for more than 70% of the total manufacturing cost - test
cost does not directly scale with transistor count, dies size, device pin
count, or process technology”, ITRS 2003.
6
Motivation for Testing
• billion+
Cost escalates
rapidly • Rule of Ten
7
Testing Levels and Test Costs
• Wafer • Cost to detect a fault (per
• Packaged chip chip)
– Wafer: $0.01-$0.1
• Board
– Packaged chip: $0.1-$1
• System – Board: $1-$10
• Field – System: $10-$100
– Field: $100-1000
• Concurrent checking
Manufacturing Testing
Goal: Detect manufacturing detects
8
Testing : The Buzzwords
• Errors • Types of testing
– Permanent – Off-line, on-line
– Intermittent – Self-test vs external test
– Transient – DC (static) vc AC (at-speed)
• Faults – Edge-pin, guided-probe, bed-
of-nails, E-beam, in-circuit
– Physical
– Logical
• Test Evaluation
– Fault coverage
– Fault simulation
9
Testing and Diagnosis
Design
10
Fault Models
• Defects are too many and too difficult to explicitly
enumerate
• Abstraction (technology independence): presence of
physical defect is modeled by changing the logic function
(or delay)
• Reduced complexity: distinct physical defects may be
represented by the same logical fault
• Generality: tests derived for logical faults may detect
vaguely-understood or hard-to-analyze physical defects
• A test pattern detects a fault from the fault model
s-a-0 A A
s-a-1
B B
z z
C C
D D
11
Stuck-At Faults
• How does a chip fail?
– Usually failures are shorts between two conductors or
opens in a conductor
– This can cause very complicated behavior
• A simpler model: Stuck-At
– Assume all failures cause nodes to be “stuck-at” 0 or 1,
i.e. shorted to GND or VDD
– Not quite true, but works well in practice
Examples
12
SSL Fault Detection
• A test pattern for fault x s-a-d is an input combination that
1) places d on x (activation), 2) propagates fault effect (D
or D) to primary output
D: 1/0, D: 0/1
Good circuit
Bad circuit
A
s-a-0
B
z
C
E
13
Observability & Controllability
14
Test Pattern Generation
• Exhaustive testing: Apply 2n pattern to n-input circuit
• Not practical for large n
• Advantage: Fault-model independent
Fault-Oriented Test Generation Algorithm:
A s-a-0 1) Set x to 1: activate fault
B y 2) Justify D on x, propagate D
z
C x to z
D
Test Example
SA1 SA0
• A3 {0110} {1110}
• A2 {1010} {1110}
• A1 {0100} {0110}
• A0 {0110} {0111}
• n1 {1110} {0110}
• n2 {0110} {0100}
• n3 {0101} {0110}
• Y {0110} {1110}
15
Bridging Faults
• Models short circuits, pairs of nodes considered
• Number of bridging faults?
• Feedback vs non-feedback bridging faults
bridge
A B z zf Wired-AND Wired-OR
A
z
0 0 0 0 0 0
B 0 1 0 ? 0 1
1 0 1 ? 0 1
1 1 1 1 1 1
zf = ?
What are the test patterns in this example?
Stuck-Open Faults
VDD
a
Fault-free circuit: z = a+b
b
Floating node ~
Faulty circuit: zf = a+b + abz
z
~
z: Previous value of z
a b
16
Sequential Circuit Test Generation
Primary
n Primary
Combinational outputs
inputs
(controllable) logic (observable)
State outputs
State inputs
m Registers
(not observable)
(not controllable)
• Difficult problem!
• Exhaustive testing requires 2m+n patterns (2m states and 2n
transitions from each state)
• Every fault requires a sequence of patterns
Initializing sequence: drive to known state
Test activation
Propagation sequence: propagate discrepancy to observable output
ECE 261 Krish Chakrabarty 34
D Q y+
A
B y A
z B y
C x z
C x
y
17
Sequential Circuit Test Generation
s-a-0 D Q
Assume initial state
A of flip-flop is not
B y
z known
C x
1
y+ y+
A1 A 0 0
B1 y B 1 y D
z 1 z
C x C1 D x
y y
Backward
ABC = 11X traversal ABC = 011
in time
Current time frame
Test pattern sequence: {11X, 011}
ECE 261 Krish Chakrabarty 36
Summary
• Think about testing from the beginning
– Simulate as you go
– Plan for test after fabrication
18