7632 Group: Description

MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION Schmitt trigger input ports . . . . . . . . . . . . . . . . . . . 32 selectable

z Interrupts. . . . . . . . . . . . . . . . . . . . . . . . .24 sources, 24 vectors
The 7632 group is a single chip microcomputer designed with
CMOS silicon gate technology.
z Timers
16-bit timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 channels
Being equipped with a CAN (Controller Area Network) module, the 8-bit timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 channels
microcomputer is suited to drive automotive equipments. The CAN
module complies with 2.0B specification and allows priority based
z Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
message management.
z Serial I/Os
UART or clock synchronous . . . . . . . . . . . . . . . . . . . 2 channels
In addition to the microcomputers simple instruction set, the ROM,
RAM and I/O addresses are placed in the same memory map to
z CAN module 2.0B active. . . . . . . . . . . . . . . . . . . . . . . 1 channel
enable easy programming. Acceptance filter support unit(ASU)
The built-in ROM is available as mask ROM or One Time PROM. z A-D converter . . . . . . . . . . . . . . . . . . . . . . . 8-bits X 8 channels
For development purposes emulator- and EPROM-type microcom- z Clock generating circuit
puters are available as well. Main Clock (XIN-XOUT) . . . . . . . . . . . . .Internal feedback resistor
z Power source voltage
FEATURES (at 10 MHz oscillation frequency) . . . . . . . . . . . . . . .4.0 to 5.5 V
z Power dissipation
z Basic machine-language instructions. . . . . . . . . . . . . . . . . . .71 In high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 mW
z Minimum instruction execution time (at 8 MHz oscillation frequency, at 5 V power source voltage)
(at 10 MHz oscillation frequency) . . . . . . . . . . . . . . . . . . 0.2 µs z Operating temperature range . . . . . . . . . . . . . . . . . –40 to 85 °C
z Memory size z Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 QFP (80P6S-A)
ROM . . . . . . . . . . . . . . . . . . .60 Kbytes (M37632MFT-XXXFP)
RAM . . . . . . . . . . . . . . . . . . . . .2 Kbytes (M37632MFT-XXXFP)
z I/O ports
APPLICATION
Programmable input/output ports . . . . . . . . . . . . . . . . . . . . . 72 Automotive controls, Automotive audio.
PIN CONFIGURATION (TOP VIEW)

P83/SRDY1/URTS1
P87/SRDY2/URTS2
P82/SCLK1/UCTS1
P86/SCLK2/UCTS2
P81/SOUT1/UTXD1
P85/SOUT2/UTXD2
P80/SIN1/URXD1
P84/SIN2/URXD2
P70/AN0
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P76/AN6
P77/AN7
P20/ST0
P21/ST1
AVSS
VREF
79
76
80
64
61
77
69
66
65
78
74
70
62
75
71
67
63
72
68
73
P67/PWM 1 60 P22/ST2
P66/CNTR1 2 59 P23/ST3
3 58 P24/ST4
P65/CNTR0
4 57 P25/ST5
P64/TX0
5 56 P26/ST6
P63/INT1
P62/INT0 6 55 P27/ST7
CNVSS 7 54 P00/ST00
8 53 P01/ST01
RESET
P61 9 M37632MFT-XXXFP 52 P02/ST02
P60 10 51 P03/ST03
VSS 11 M37632EFT-XXXFP 50 P04/ST04
XIN 12 49 P05/ST05
XOUT 13 48 P06/ST06
VCC 14 47 P07/ST07
P57/KW7 15 46 P10/ST10
P56/KW6 16 45 P11/ST11
P55/KW5 17 44 P12/ST12
P54/KW4 18 43 P13/ST13
P53/KW3 19 42 P14/ST14
P52/KW2 20 41 P15/ST15
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P51/KW1
P50/KW0
P47
P46
P45
P44
P43
P40
ST37
ST36
ST35
ST34
ST33
ST32
ST31
ST30
P42/CRX
P41/CTX
P17/ST17
P16/ST16
Package type: 80P6S-A

80-pin plastic molded QFP
Fig. 1 Pin configuration of M37632MFT-XXXFP
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M37632MFT-XXXFP FUNCTIONAL BLOCK DIAGRAM (PACKAGE : 80P6S-A)
Functional block diagram
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Reset
Clock Clock input
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output input
XOUT XIN RESET VCC VSS AVSS CNVSS
13 12 8 14 11 71 7
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Clock generating circuit
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CPU A (8) ROM RAM WDT
2
Timer X (16) Timer 1 (8)
X (8)
Y (8) Timer Y (16) PWM Timer 2 (8)
S (8)
Timer 3 (8)
PCH PCL
PS (8)
ELECTRIC
MITSUBISHI
Key-on
USART2 USART1 A-D converter wake-up CAN

4 2
4
INT0, INT1
P8 (8) P7 (8) P6 (8) P5 (8) P4 (8) P3 (8) P2 (8) P1 (8) P0 (8)
63 6465 66 67 68 69 70 72 7475 76 77 78 79 80 18 01 02 03 04 05 06 09 10 15 16 17 18 19 20 21 22 23 2425 26 27 28 29 30 31 3233 34 35 36 37 38 55 56 57 58 59 60 61 62 39 4041 42 43 44 45 46 47 48 49 50 51 52 53 54
VREF
7632 Group
I/O port P6 I/O port P4 I/O port P3 I/O port P2 I/O port P1 I/O port P0
I/O port P8 I/O port P7 I/O port P5
E: ation. 7632 Group

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PIN DESCRIPTION
Table 1: Pin Description
Input/
Pin Name Description
Output
VCC, VSS Power source Power supply pins; apply 4.0 to 5.5V to VCC and 0V to VSS.
AVSS Analog power source Ground pin for A/D converter. Connect to VSS.
Reset input pin for active ”L”. This pin must be kept at “L” level for more than
RESET Reset input Input 2µs, to enter the reset state. If the crystal or ceramic resonator requires
more time to stabilize, extend the “L” level period.
XIN Clock input Input Input and output pins of the internal clock generating circuit. Connect a
ceramic or quartz crystal between the XIN and XOUT pins. If an external clock
XOUT Clock output Output source is used, connect it to XIN and leave XOUT open.
Reference voltage
VREF Input Reference voltage input pin for A-D converter
input
Controls the chip mode. Normally connected to VSS .This pin will be used as
CNVSS CNVSS Input
VPP pin during PROM writing of One Time PROM microcomputers.
CMOS I/O ports. Either CMOS compatible input or Schmitt trigger input is
P00/ST00 — P07/ST07 I/O port P0 I/O
selectable.
P10/ST10 — P17/ST17 I/O port P1 I/O CMOS I/O ports with the same function as Port 0
P20/ST20 — P27/ST27 I/O port P2 I/O CMOS I/O ports with the same function as Port 0
P30/ST30— P37/ST37 I/O port P3 I/O CMOS I/O ports with the same function as Port 0
CMOS I/O ports. CMOS 3-state output structures and CMOS compatible
P40 I/O
input level
CMOS I/O port with the same function as Port 40 or CAN transmit data out-
P41/CTX I/O
I/O port P4 put pin.
CMOS I/O port with the same function as Port 40 or CAN receive data input
P42/CRX I/O
pin.
P43 — P47 I/O CMOS I/O port with the same function as Port 40
CMOS I/O ports with the same function as Port 40. These ports can also be
P50 /KW0 — P57/KW7 I/O port P5 I/O
used for key-on wake-up when configured as inputs.
P60 — P61 CMOS I/O port with the same function as Port 40
CMOS input port with the same function as Port 40 or external interrupt input
P62/INT0 port. The active edge (rising or falling) of external interrupts can be
selected.
CMOS I/O port or external interrupt input port. The active edge (rising or fall-
P63/INT1
ing) of external interrupts can be selected.
P64/TX0 I/O port P6 I/O CMOS I/O port or input pin used in bi-phase counter mode.
CMOS I/O port or timer X input pin used for pulse period measurement,
P65/CNTR0
pulse width measurement and bi-phase counter mode.
CMOS I/O port or timer Y input pin used for event counter, pulse width and
P66/CNTR1
pulse period measurement mode.
P67/PWM CMOS I/O port or PWM output pin used in PWM mode of timers 2 and 3.
P70/AN0 — P77/AN7 I/O port P7 I/O CMOS I/O ports or analog input ports.
P80/SIN1/URXD1
P81/SOUT1/UTXD1
USART1 I/O CMOS I/O ports or USART synchronous and asynchronous serial I/O pins.
P82/SCLK1/UCTS1
P83/SRDY1/URTS1
P84/SIN2/URXD2
P85/SOUT2/UTXD2
USART2 I/O CMOS I/O ports or USART synchronous and asynchronous serial I/O pins.
P86/SCLK2/UCTS2
P87/SRDY2/URTS2
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FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU) CPU Mode Register
The core of 7632 group MCUs is the 7600 series CPU. This core is The CPU mode register contains the stack page selection bit and
based on the standard MELPS 740 instruction set; however the internal system clock selection bit. The CPU mode register is allo-
performance is improved by allowing to execute the same instruc- cated to address 000016.
tions in less cycles than with 740 series CPU. Refer to the 7600
series Software Manual for details of the instruction set.
7 0
CPU mode register (address 000016)
CPUM
Processor Mode Bits (set these bits to “00”)

b1 b0
0 0: Single chip mode
0 1: Not used (do not write)
Stack Page Selection Bit

0 : In zero page
1 : In page 1
Not used (“0” when read, do not write “1”)
Internal Clock Selection Bit
0 : f(XIN) divided by 2 (high speed mode)
1 : f(XIN) divided by 8 (middle speed mode)
Fig. 3 Structure of CPU Mode Register
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MEMORY
Special Function Register (SFR) Area The interrupt vector area is for storing jump destination addresses
used at reset or when an interrupt is generated.
The special function register (SFR) area contains the registers
relating to functions such as I/O ports and timers. Zero Page
RAM This area can be accessed most efficiently by means of the zero
RAM is used for data storage and for stack area of subroutine calls page addressing mode.
and interrupts.
Special Page
ROM
ROM is used for storing user‘s program code as well as the inter- This is accessed in special page addressing mode.
rupt vector area.
RAM area
RAM size Address 000016

(byte) XXXX16
192 013F16 004016 SFR area

CAN Zero page
256 017F16
SFRs
384 01FF16 008016
512 027F16 010016

RAM
640 02FF16
768 037F16
896 03FF16
XXXX16
1024 047F16
Reserved
1536 06FF16
087F16 088016
2048
Not used
ROM area
ROM size Address Address

(byte) YYYY16 ZZZZ16
YYYY16
4096 F00016 F08016 Reserved ROM area
ZZZZ16
8192 E00016 E08016
12288 D00016 D08016
16384 C00016 C08016
20480 B00016 B08016 ROM
24576 A00016 A08016
FF0016
28672 900016 908016
32768 800016 808016
FFCA16 Special page
36864 700016 708016 Interrupt vector area
FFFB16
40960 600016 608016 FFFC16
Not used ROM area
45056 500016 508016 FFFF16
49152 400016 408016

53248 300016 308016
57344 200016 208016
61440 100016 108016
Fig. 4 Memory map
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SPECIAL FUNCTION REGISTERS (SFR)
000016 CPU Mode Register CPUM 003016 UART 2 mode register U2MOD
000116 not available 003116 UART 2 baud rate generator U2BRG
000216 Interrupt request register A IREQA 003216 UART 2 control register U2CON
000316 Interrupt request register B IREQB 003316 UART 2 status register U2STS
000416 Interrupt request register C IREQC 003416 UART 2 transmit buffer register 1 U2TBR1
000516 Interrupt control register A ICONA 003516 UART 2 transmit buffer register 2 U2TBR2
000616 Interrupt control register B ICONB 003616 UART 2 receive buffer register 1 U2RBR1
000716 Interrupt control register C ICONC 003716 UART 2 receive buffer register 2 U2RBR2
000816 Port P0 register P0 Port P0/ P1/ P2/ P3/ pullup control
000916 Port P0 direction register P0D 003816 register (4 bits) PUP03
000A16 Port P1 register P1 Schmitt Trigger Selection (4 bits)
003916 Port P4 pullup/down control register PUP4
000B16 Port P1 direction register P1D
003A16 Port P5 pullup control register PUP5
000C16 Port P2 register P2
003B16 Port P6 pullup control register PUP6
000D16 Port P2 direction register P2D
003C16 Port P7 pullup control register PUP7
000E16 Port P3 register P3
003D16 Port P8 pullup control register PUP8
000F16 Port P3 direction register P3D
003E16 Watch dog timer register WDT
001016 Port P4 register P4
Polarity control register (2 bits)
001116 Port P4 direction register P4D 003F16 PCON
CAN Prescaler (3 bits)
004016 CAN transmit control register CTRM
001316 Port P5 direction register P5D
004116 CAN bus timing control register 1 CBTCON1
004216 CAN bus timing control register 2 CBTCON2
004316 CAN acceptance code register 0 CAC0
001A16 Serial I/O 1 shift register SIO1
004816 CAN acceptance mask register 0 CAM0
001B16 Serial I/O 1 control register SIOCON1
004916 CAN acceptance mask register 1 CAM1
001C16 A-D conversion register AD
004A16 CAN acceptance mask register 2 CAM2
001D16 A-D control register ADCON
004B16 CAN acceptance mask register 3 CAM3
001E16 Timer 1 T1
004C16 CAN acceptance mask register 4 CAM4
001F16 Timer 2 T2
004D16 CAN receive control register CREC
002016 Timer 3 T3
004E16 CAN abort control register CABORT
002116 Timer 123 mode register T123M
004F16 Reserved
002216 Timer XL TXL
005016 CAN transmit buffer 0 CTB0
002316 Timer XH TXH
002416 Timer YL TYL
002516 Timer YH TYH
002616 Timer X mode register TXM
002716 Timer Y mode register TYM
002816 UART 1 mode register U1MOD
002916 UART 1 baud rate generator U1BRG
002A16 UART 1 control register U1CON
002B16 UART 1 status register U1STS
002C16 UART 1 transmit buffer register 1 U1TBR1
005A16 CAN transmit buffer A CTBA
002D16 UART 1 transmit buffer register 2 U1TBR2
005B16 CAN transmit buffer B CTBB
002E16 UART 1 receive buffer register 1 U1RBR1
005C16 CAN transmit buffer C CTBC
002F16 UART 1 receive buffer register 2 U1RBR2
005D16 CAN transmit buffer D CTBD
005E16 Reserved
005F16 Reserved
Fig. 5 Memory map of special function registers(SFR) (1)
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006016 CAN receive buffer 0 CRB0 007016 Acceptance SID(11:3) ASID

006116 CAN receive buffer 1 CRB1 007116 Acceptance SID(2:0) converted CSID
006216 CAN receive buffer 2 CRB2 007216 Reserved
006A16 CAN receive buffer A CRBA 007A16 Serial I/O 2 shift register SIO2
006B16 CAN receive buffer B CRBB 007B16 Serial I/O 2 control register SIOCON2
006C16 CAN receive buffer C CRBC 007C16 Reserved
006D16 CAN receive buffer D CRBD 007D16 Interrupt polarity selection register IPOL
006E16 CAN receive buffer E CRBE 007E16 Reserved
006F16 CAN receive buffer F CRBF 007F16 Reserved
Fig. 6 Memory map of special function registers(SFR) (continued) (2)
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I/O PORTS
The 7632 group has 72 programmable I/O pins arranged in nine I/O If data is read from a port configured as output, the port latch is read
ports (ports P0 to P8). The I/O ports are controlled by the corre- rather than the port level. A port configured as input becomes float-
sponding port registers and port direction registers; each I/O pin ing and its level can be read. Data written to this port will affect the
can be controlled separately. port latch only; the port remains floating.
Please refer to Figure 7 and Figure 8.
7 0
Port Pi data register (i =0 to 8) (address 000816 + 2 · i)
Pi
Port Pij control bit (j = 0 to 7)

0 : “L” level
1 : “H” level
7 0
Port Pi direction register (i =0 to 8) (address 000916 + 2 · i)
PiD
Port Pij direction control bit (j = 0 to 7)

0 : Port configured as input
1 : Port configured as output
Fig. 7 Structure of port- and port direction registers
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(1) Ports P0, P1, P2, P3 (2) Ports P40, P43 - P47, P60, P61
Pull-up control bit Pull-up control bit
Direction Direction
register register
Data bus Port latch Data bus Port latch
Schmitt trigger selection bit
(3) Ports P50/KW0 to P57/KW7 (4) Port P80/SIN1, Port P84/SIN2, when SIO selected
Key-on wake-up control bit
Pull-up/down control bit
Pull-up control bit
Direction
register
Direction
register
Data bus Port latch

Data bus Port latch
SIO1 input
Key-on wake-up interrupt
(5) Port 80/URXD1 ,Port 84/URXD2, when UART selected (6) Port P81/SOUT1, Port P85/SOUT2, when SIO selected
Reception in progress Pull-up control bit Pull-up control bit

SIO port selection bit
Transmit complete signal
Receive enable bit
Direction Direction
register register
Port latch Data bus Port latch

Data bus
URXD input SIO output
(7) Port P81/UTXD1, Port P85/UTDX2, when UART selected (8) Port P82/SCLK1, Port P86/SCLK2, when SIO selected

Clock selection bit
Receive enable bit Port selection bit
Direction direction
register register
UTXD output SIO clock output External clock input
Fig. 8 Structure of port I/Os (1)
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(9) Port P82/UCTS1, Port P86/UCTS2, when UART selected (10) Port P83/SRDY1, Port P8//SRDY2, when SIO selected
RTS/CTS selection bit

Transmission in progress
SRDY output selection bit
Transmit enable bit
Direction Direction
register register
URXD or UCTS input SRDY output
(11) Port P83/URTS1, Port P86/URTS2, when UART selected (12) Port P64/TX0
RTS/CTS selection bit

Receive enable bit

Direction Direction
register register
Data bus Port latch

Data bus Port latch
URTS output
Timer bi-phase mode input
(13) Ports P65/CNTR0, P66/CNTR1 (14) Port P67/PWM
PWM output enable

Direction reg- Direction
ister register
PWM output
Timer bi-phase mode input
(15) Port P41/CTX (16) Port P42/CRX
CAN dominant level control bit

Pull-up control bit Pull-up/down control bit
CAN port selection bit
Direction reg-
Direction ister
register
Data bus Port latch

Data bus Port latch
CTX output CAN interrupt
CRX input
Fig. 9 Structures of port I/Os (2)
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(17) Ports P62/INT0, P63/INT1 (18) Ports P70/AN0 to P77/AN7
Pull-up control bit

Pull-up control bit
AD ch. sel.
Direction
register Direction
register
Data bus Port latch

Data bus Port latch
Interrupt input ADC input

Analog input selection bit
Fig. 10 Structures of port I/Os (3)
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Port pull-up/pull-down function down registers together with the polarity control register (see Figure
12).
Each pin of ports P0 to P8 is equipped with programmable pull-up
transistors. P42/CRX and P50/KW0 to P57/KW7 are equipped with Schmitt Trigger Input Control
programmable pull-down transistors as well. The pull-up function of
P0 to P8 can be controlled by the corresponding port pull-up control Ports P0 to P3 are equipped with additional schmitt trigger circuits.
registers (see Figure 11). The pull-up/down function of ports P42 They can be selected by setting the corresponding bits of the port
and P5 can be controlled by the corresponding port pull-up/pull- P0 to P3 control register (see Figure 11).
7 0
Port P0, P1, P2, P3 control register (address 003816)
PUP0, PUP1, PUP2, PUP3, ST0, ST1, ST2, ST3
Pi pull-up transistor control bit (j = 0, 2, 4, 6)

STi Schmitt trigger control bit (j = 1, 3, 5, 7)
7 0
Port P4 pull-up control register (address 003916)
PUP4
P4j pull-up transistor control bit (j = 0 - 1)

P42 pull-up/down transistor control bit
P4j pull-up transistor control bit (j = 3, 4, 5, 6, 7)
7 0
Port P5 pull-up/down control register (address 003A16)
PUP5
P5j pull-up/down transistor control bit (j = 0 to 7)

0 : Pull-up/down transistor disabled
1 : Pull-up/down transistor enabled
7 0
Port Pi pull-up control register (address 003016 + i) (i = B, C, D)
PUP6, PUP7, PUP8
Pij pull-up transistor control bit (j = 0 to 7)

0 : Pull-up transistor disabled
1 : Pull-up transistor enabled
Fig. 11 Structure of port pull-up/down control registers
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7 0
Polarity and CAN clock control register (address 003F16)
PCON
Key-on wake-up polarity control bit

0 : Low level active
1 : High level active
CAN module dominant level control bit
0 : Low level dominant
1 : High level dominant
Not used (read as “0”, do not write “1”)
Not used (undefined when read)
Fig. 12 Structure of polarity and CAN clock control register.
Port Over-/undervoltage Application • Avoid to subject ports to undervoltage causing VCC to fall below
–0.5 V.
When configured as input ports, P0 to P6 and P8 may be subjected
to overvoltage (VI > VCC) or undervoltage (VI < VSS) if the input cur- • The over- or undervoltage condition causing input current flow-
rent to the applicable port is limited to the specified values (see ing through the internal port protection circuits has a negative
“Recommended operating conditions” on page 44). Please use a effect on the ports noise immunity. Therefore, careful and
serial resistor of appropriate size to limit the input current. To esti- intense testing of the target systems noise immunity is required.
mate the resistor value assume the port voltage to be VSS at under- Please refer to the “countermeasures against noise” of the corre-
voltage and VCC at overvoltage condition. sponding users manual.
Notes: • Port P7 can be subjected to over- or undervoltage conditions as
• Subjecting ports to over- or undervoltage may effect the supply specified in see “Recommended operating conditions” on
voltage. Assure to keep VCC and VSS within the target limits. page 44.
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INTERRUPTS
Interrupts may be caused by 27 different events, each with separate cation, the remaining 2 sources are Not used for Mitsubishi factory
interrupt vector. 25 of these interrupts are available for user‘s appli- use.
All interrupts are vectored with priorities shown in the table below.
Table 2: Interrupt vector addresses and priority
Vector Address (Note 1)

Interrupt Request Generating
Interrupt source Priority Remarks
Conditions
High Low
Reset (Note 2) 1 FFFB16 FFFA16 At Reset Non-maskable

Watchdog timer 2 FFF916 FFF816 At Watchdog timer underflow Non-maskable
At detection of either rising or falling External Interrupt
INT0 3 FFF716 FFF616
edge of INT0 interrupt (active edge selectable)
INT1 4 FFF516 FFF416
edge of INT1 interrupt (active edge selectable)
CAN successful At CAN module’s successful transmis- Valid when CAN module is acti-
5 FFF316 FFF216
transmit sion of message vated and request transmit
CAN successful At CAN module’s successful reception Valid when CAN module is acti-
6 FFF116 FFF016
receive of message vated
If CAN module receives message Valid when CAN module is acti-
CAN overrun 7 FFEF16 FFEE16
when receive buffers are full. vated
CAN error When CAN module enters into error Valid when CAN module is
8 FFED16 FFEC16
passive passive state active
When CAN module enters into bus off Valid when CAN module is
CAN error bus off 9 FFEB16 FFEA16
state active
When CAN module wakes up via CAN
CAN wake up 10 FFE916 FFE816
bus
Timer X 11 FFE716 FFE616 At Timer X underflow or overflow
Timer Y 12 FFE516 FFE416 At Timer Y underflow
Timer 1 13 FFE316 FFE216 At Timer 1 underflow
Timer 2 14 FFE116 FFE016 At Timer 2 underflow
Timer 3 15 FFDF16 FFDE16 At Timer 3 underflow
CNTR0 16 FFDD16 FFDC16
edge in CNTR0 input (active edge selectable)
CNTR1 17 FFDB16 FFDA16
edge in CNTR1 input (active edge selectable)
At completion of UART1 receive
UART1 receive Valid when UART1 or SIO1 are
18 FFD916 FFD816 At completion of Serial I/O1 data trans-
Serial I/O 1 selected
mit & receive
UART1 transmit 19 FFD716 FFD616 At completion of UART1 transmit Valid when UART1 is selected
At completion of UART2 receive
UART2 receive Valid when UART2 or SIO2 are
20 FFD516 FFD416 At completion of Serial I/O2 data trans-
Serial I/O2 selected
mit & receive
UART2 transmit 21 FFD316 FFD216 At completion of UART2 transmit Valid when UART2 is selected
22 FFD116 FFD016 Not used
A-D conversion 23 FFCF16 FFCE16 At completion of A-D conversion
At detection of either rising or falling of External Interrupt
Key-on wake-up 24 FFCD16 FFCC16
edge of P5 input (active edge selectable)
BRK instruction 25 FFCB16 FFCA16 At BRK instruction execution Non-maskable
Note 1 Vector addresses contain interrupt jump destination address
Note 2 Reset function in the same way as an interrupt with the highest priority
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Interrupt Control 2. The contents of the program counter and processor status
register are automatically pushed onto the stack.
Each interrupt except the BRK instruction interrupt has both an 3. Concurrently with the push operation, the interrupt jump
interrupt request bit and an interrupt enable bit, and is controlled by destination address is read from the vector table into the
the interrupt disable flag. An interrupt occurs when the correspond- program counter.
ing interrupt request and enable bits are “1” and the interrupt dis-
4. The interrupt disable flag is set and the corresponding interrupt
able flag is “0”. Interrupt enable bits can be cleared or set by
request bit is cleared
software. Interrupt request bits can be cleared by software but can-
not be set by software. The BRK instruction interrupt and reset can- Notes on use
not be disabled with any flag or bit. The I flag disables all interrupts When the active edge of an external interrupt (INT0, INT1, CNTR0,
except the BRK instruction interrupt and reset. If several interrupt CNTR1, CWKU or KOI) is changed, the corresponding interrupt
requests occur at the same time, the interrupt with the highest prior- request bit may also be set. Therefore, take the following sequence.
ity is accepted first. (1) Disable the external interrupt which is selected.
Interrupt Operation (2) Change the active edge in interrupt edge selection register.
(in the case of CNTR0: Timer X mode register; in the case of
Upon acceptance of an interrupt, the following operations are auto- CNTR1: Timer Y mode register)
matically performed. (3) Clear the interrupt request bit to “0”.
1. The processing being executed is stopped. (4) Enable the external interrupt which is selected.
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7 0 Interrupt request register A 7 0

Interrupt control register A
(address 000216)
(address 000516)
IREQA
ICONA
Not used (“0” when read) Not used (“0” when read, do not write
External interrupt INT0 request bit “1”)
External interrupt INT0 enable bit
External interrupt INT1 request bit
External interrupt INT1 enable bit
CAN successful transmission
interrupt request bit CAN successful transmission inter-
rupt enable bit
CAN successful receive
interrupt request bit CAN successful receive interrupt
enable bit
CAN overrun interrupt request bit
CAN overrun interrupt enable bit
CAN error passive
interrupt request bit CAN error passive interrupt enable bit
CAN bus off interrupt request bit CAN bus off interrupt enable bit
7 0 Interrupt request register B 7 0 Interrupt control register B

(address 000316) (address000616)
IREQB ICONB
CAN wake up interrupt request bit CAN wake up interrupt enable bit
Timer X interrupt request bit Timer X interrupt enable bit
Timer Y interrupt request bit Timer Y interrupt enable bit
Timer 1 interrupt request bit Timer 1 interrupt enable bit
CNTR0 interrupt request bit CNTR0 interrupt enable bit
CNTR1 interrupt request bit CNTR1 interrupt enable bit
7 0 Interrupt request register C 7 0 Interrupt control register C

(address 000416) (address 000716)
IREQC ICONC
UART1 receive complete UART1 receive complete (receive
(receive buffer full) buffer full) interrupt request bit, SIO1
interrupt request bit, SIO1 Interrupt Interrupt
UART1 transmit complete (transmit UART1 transmit complete (transmit
register empty) interrupt request bit register empty) interrupt request bit
UART2 receive complete UART2 receive complete (receive

(receive buffer full) buffer full) interrupt request bit, SIO2
interrupt request bit, SIO2 Interrupt Interrupt
UART2 transmit complete UART2 transmit complete (transmit

register empty) interrupt request bit
(transmit register empty)
interrupt request bit Not used (“0” when read)
Not used (“0” when read) AD conversion complete interrupt
enable bit
AD conversion complete
interrupt request bit Key-on wake-up interrupt enable bit
Key-on wake-up interrupt request bit Not used (“0” when read, do not
write “1”)
Not used (“0” when read)
0 : No interrupt request 0 : Interrupt disabled

1 : Interrupt requested 1 : Interrupt enabled
Fig. 13 Structure of interrupt request registers and of interrupt control registers A, B and C
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For the external interrupts INT0 and INT1 the active edge causing edge selection bits of the interrupt polarity selection register (IPOL);
the interrupt request can be selected by the INT0 and INT1 interrupt please refer to Figure 14 below.
7 0
Interrupt polarity selection register (address 007D16)
IPOL

INT0 interrupt edge selection bit
INT1 interrupt edge selection bit
0 : Falling edge active

1 : Rising edge active
Fig. 14 Structure of interrupt polarity selection register
Interrupt request bit
Interrupt enable bit
Interrupt disable flag I
BRK instruction Interrupt request

Reset
Fig. 15 Interrupt control
KEY-ON WAKE-UP
“Key on wake up” is one way of returning from a power down state PCON (see Figure 12). If any pin of port P5 has the selected active
caused by the STP or WIT instruction. Any pin of port P5 can be level applied, the key on wake up interrupt request will be set to “1”.
used to generate the key on wake up interrupt request. The active Please refer to Figure 16.
polarity can be selected by the key on wake up polarity control bit of
Key-on wake-up control bit
P5Dj
PUPD5j
Port P5j/KWj
Key-on wake-up interrupt
…
Port P5j I/O circuit

j = 0 to 7
Fig. 16 Block diagram of key-on wake-up circuit
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TIMERS
The timer section of 7632 group is equipped with six timers: two 16- 16-BIT TIMERS
bit timers, three 8-bit timers and one watchdog-timer. All these tim-
ers will be described in detail below. Timers X and Y are 16-bit timers with multiple operating modes.
Please refer to Figure 17.
XIN TYM1,0
1/8
“00”
TXM5,4 TXL latch (8) TXH latch (8)
TXM7
1/32 “01” “x0”, “11”
1/128 “10” “01”
TXL counter (8) TXH counter (8) TX interrupt request
1/256
“11”
“10”
Count
direction
control
P64/TX0
Down
Edge detector “00”, “10”,
“11”
“01”
Sign generator
P65/CNTR0
TXM5, 4
Edge detector
TXM5, 4=“10”
“1”
falling edge detector CNTR0 interrupt request
“0” TXM
6
TXM5, 4=“11” TYL latch (8) TYH latch (8)

1/4 “00” TYM7
TYM3, 2
1/16 “01” “0x”, “11”
TYM5, 4
TYL counter (8) TYH counter (8) TY interrupt request
1/64 “10”
1/128 “11” “10”
TYM5, 4=“11”
Rising edge detector
Falling edge detector
P66/CNTR1 “1” TYM5, 4=“01” “11”

“0” “0x”, “10”
CNTR1 interrupt request
TYM6 TYM5, 4
Fig. 17 Block diagram of timers X and Y
TIMER X same address as TXL. Next write the high-order byte. When this is
finished, the data is placed in the timer X high-order reload latch
Timer X is a 16-bit timer with 16-bit reload latch supporting the fol- and the low-order byte is transferred from its temporary register to
lowing operating modes: the timer X low-order reload latch. Depending on the timer X write
• Timer mode control bit, the latch contents are reloaded to the timer immediately
• Bi-phase counter mode (write control bit = “0”) or on the next timer underflow (write control
• Pulse period measurement bit = “1”).
• Pulse width measurement mode
Read method
These modes can be selected by timer X mode register (TXM). In
timer-, pulse period measurement and pulse width measurement When reading the timer X, read the high-order byte first. This
mode the timers count source can be selected by the timer X count causes the timer X high- and low-order bytes to be transferred to
source selection bits of timer Y mode register (TYM). Please refer temporary registers being assigned to the same addresses as TXH
to the figures below for the TXM and TYM bit assignment. and TXL. Next read the low-order byte, which is read from the tem-
On read or write access to timer X please note, that the high-order porary register. This method assures the correct timer value can be
and low-order bytes must be accessed in a specific order. read during timer count operation.
Write method
When writing to the timer X, write the low-order byte first. The data
written is stored in a temporary register which is assigned to the
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Timer X count stop control by setting the timer X count stop bit (bit 7 of timer X mode register)
to “1”.
Regardless of the actual operating mode, timer X can be stopped
7 0
Timer X mode register (address 002616)
TXM
Timer X data write control bit

0 : Data is written to latch and timer
1 : Data is written to latch only
Timer X mode bits
b5 b4
0 0: Timer mode
0 1: Bi-phase counter mode
1 0: Pulse period measurement mode
1 1: Pulse width measurement mode
CNTR0 polarity selection bit
0 : For pulse period measurement mode: falling edge active
For interrupt request: falling edge active
For pulse width measurement mode: measure “H” period
1 : For pulse period measurement mode: rising edge active
For interrupt request: rising edge active
For pulse width measurement mode: measure “L” period
Timer X stop control bit
0 : Timer counting
1 : Timer stopped
Fig. 18 Structure of timer X mode register
TIMER Y same address as TYL. Next write the high-order byte. When this is
finished, the data is placed in the timer Y high-order reload latch
Timer Y is a 16 bit timer with 16-bit reload latch supporting the fol- and the low-order byte is transferred from its temporary register to
lowing operating modes: the timer Y low-order reload latch.
• Timer mode
• Pulse period measurement mode Read method
• Event counter mode
When reading the timer Y, read the high-order byte first. This
• H/L pulse width measurement mode
causes the timer Y high- and low-order bytes to be transferred to
These modes can be selected by timer Y mode register (TYM). In
temporary registers being assigned to the same addresses as TYH
timer-, pulse period- and pulse width measurement mode the timers
and TYL. Next read the low-order byte, which is read from the tem-
count source can be selected by the timer Y count source selection
porary register. This method assures the correct timer value can be
bits. Please refer to Figure 19.
read during timer count operation.
On read or write access to timer Y please note, that the high-order
and low-order bytes must be accessed in a specific order. Timer Y count stop control
Write method Regardless of the actual operating mode, timer Y can be stopped
When writing to the timer Y, write the low-order byte first. The data by setting the timer Y count stop bit (bit 7 of timer Y mode register)
written is stored in a temporary register which is assigned to the to “1”.
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7 0
Timer Y mode register (address 002716)
TYM
Timer X count source selection bits

b1 b0
0 0: f(XIN) divided by 8
Timer Y count source selection bits
b3 b2
Timer Y operation mode bits
b5 b4
0 0: Timer mode
0 1: Pulse period measurement mode
1 0: Event counter mode
1 1: H/L pulse width measurement mode
CNTR1 polarity selection bit
0 : For event counter mode: rising edge active
For interrupt request: falling edge active
For pulse period measurement mode: refer falling edges
1 : For event counter mode: falling edge active
For interrupt request: rising edge active
For pulse period measurement mode: refer rising edges
Timer Y stop control bit
0 : Timer counting
1 : Timer stopped
Fig. 19 Structure of timer Y mode register
16-BIT TIMER OPERATING MODES
Timer mode The count direction is determined by the edge polarity and level
of count source inputs and may change during count operation.
This mode is available with timer X and timer Y. Please refer to the table below.
• Count source Table 3: Timer X count direction in bi-phase counter mode
The count source for timer X and Y is the output of the corre-
sponding clock divider. The divider ratio can be selected by timer P64/TX0 P65/CNTR0 Count direction
Y mode register.
L up
• Operation ↑ edge
Both timer X and Y are down counters. On timer underflow, the H down
corresponding timer interrupt request bit will be set to “1”, the L down
contents of the corresponding timer latches will be reloaded to ↓ edge
H up
the counters and counting continues.
L down
Bi-phase counter mode ↑ edge
H up
This mode is available with timer X only. L up
↓ edge
• Count source H down
The count sources are P65/CNTR0 and P64/TX0 pins.
• Operation
Timer X will count both rising and falling edges on both input pins
(see above). Please refer to Figure 20 to see the timing chart of
bi-phase counter mode.
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P60/TX0 input signal
P61/CNTR0 input signal
TX counter
Count direction Down Up
Fig. 20 Timer X bi-phase counter mode operation
Event counter mode • Operation

The active edge of input signal to be measured can be selected
This mode is available with timer Y only. by CNTR0 or CNTR1 polarity selection bit (Figure 19). When
• Count source these bits are set to “0” the time between two consecutive falling
The count source for timer Y is the input signal to P66/CNTR1 edges of the signal input to P65/CNTR0 or P66/CNTR1 pin will be
pin. measured, when the polarity bit is set to “1”, the time between
two consecutive rising edges will be measured.
• Operation The timers count down. The content of timer latch is perma-
The timer counts down. On timer underflow, the corresponding nently transferred to the temp latch. On detection of an active
timer interrupt request bit will be set to “1”, the contents of the
edge of input signal, data transfer from timer latch to temp latch
corresponding timer latches will be reloaded to the counters and is interrupted(but counting continues).TX and TY latches are
counting continues. The active edge used for counting can be reloaded. Reading the content of the temp latches triggers the
selected by the polarity selection bit of the corresponding pin data transfer between timer latch and temp latch to resume.The
P66/CNTR1. These bits are part of TYM (Figure 19) register. active edge of input signal also causes the CNTR0 or CNTR1
Pulse width measurement mode interrupt request bit to be set to “1”. The measurement result
may be obtained by reading timer X or timer Y during interrupt
This mode is available with timer X only. service.
• Count source
The count source is the output of timer X clock divider. The
divider ratio can be selected by timer Y mode register.
H/L pulse width measurement mode
• Operation This mode is available with timer Y only.
The timer counts down while the input signal level on
P65/CNTR0 matches the active polarity selected by the CNTR0 • Count source
polarity selection bit of TXM (Figure 18). On timer underflow the The count source is the output of timer Y clock divider.
timer X interrupt request bit will be set to “1”, the contents of the • Operation
timer latches are reloaded to the counters and counting contin- This mode measures both the “H” and “L” periods of a signal
ues. When the input level changes from active polarity (as input to P62/CNTR1 pin continuously. On detection of any edge
selected) the CNTR0 interrupt request bit will be set to “1”. The (rising or falling) of input signal to P62/CNTR1 pin, the contents of
measurement result may be obtained by reading timer X during timer Y counters are stored to temporary registers which are
interrupt service. assigned to the same addresses as timer Y. At the same time
the contents of timer Y latches are reloaded to the counters and
counting continues. The detection of edge causes the CNTR1
Pulse period measurement mode interrupt request bit to be set to “1” as well. The result of mea-
surement may be obtained by reading timer Y during interrupt
This mode is available with timer X and timer Y.
service. This read access will address the temporary registers.
• Count source On timer underflow, the timer Y interrupt request bit will be set to
The count source for timer Y is the output of timer Y clock divider “1”, the contents of timer Y latches will be transferred to the
and for timer X the output of timer X clock divider. counters and counting continues.
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8-BIT TIMERS
Timers 1 to 3 are 8-bit timers with 8-bit reload latches and one com- timers 2 and 3 can be used to generate a PWM output signal timing
mon pre-divider. Timer 1 can operate in timer mode only whereas as well. Timers 1 to 3 are down-count timers. Please see Figure 21.
XIN T123M7,6 T1 latch (8)

1/2 “00”
1/16 “01”
T1 counter (8) T1 interrupt
“10”
1/64
“11”
1/256
T2 latch (8)
T123M3 “0”
“1” T2 counter (8) T2 interrupt

“0” “1”
S
T123M1 Q
R
T3 latch (8)
“0”
“1”
T123M4 T3 counter (8) T3 interrupt
“0” “1”
S
P6D7 T123M1 Q
R T123M0
T123M1
P17 latch S
P67/PWM T Q
Fig. 21 Block diagram of timers 1 to 3
Timer 1 selected by the timer count source selection bits of timer 123 mode
register (T123M).
The count source of timer 1 is the output of timer 123 pre-divider.
The division ratio of the pre-divider can be selected by the pre- Writing to timer 2 register affects the reload latch only or reload
divider division ratio bits of timer 123 mode register (T123M). latch and counter both depending on the timer 2 write control bit of
Please refer to Figure 22. T123M. When the timer write control bit is set to “0”, both latch and
On timer 1 underflow the timer 1 interrupt request bit will be set to counter will be initialized simultaneously; when set to “1” only the
“1”. reload latch will be initialized, on underflow the counter will be set to
Writing to timer 1 initializes latch and counter. the modified reload value. Writing to timer 3 initializes latch and
Timers 2 and 3 counter both.
The count source of timer 2 and 3 can be either the output of timer Timer 2 or 3 underflow causes the timer 2 or 3 interrupt request bit
123 pre-divider or timer 1 underflow. The count source can be to be set to “1”.
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7 0
Timer 123 mode register (address 002116)
T123M
PWM polarity selection bit

0 : Start on “H” level output
1 : Start on “L” level output
PWM output enable bit
0 : PWM output disabled
1 : PWM output enabled
Timer 2 write control bit
0 : Latch and counter
1 : Latch only
Timer 2 count source selection bit
0 : Timer 1 underflow
1 : Pre-divider output
Timer 3 count source selection bit
0 : Timer 1 underflow
1 : Pre-divider output
Not used (“0” when read, don‘t write “1”)
Pre-divider division ratio bits
b7 b6
Fig. 22 Timer 123 mode register configuration
8-BIT TIMER OPERATING MODES

Timer mode PWM mode
This mode is available with timers 1 to 3. This mode is available with timer 2 and 3.
• Count source
• Count source The count source can be separately selected to be either the
For timer 1 the count source is the output of the corresponding pre-divider output or timer 1 underflow.
pre-divider. For timers 2 and 3 the count source can be sepa- • Operation
rately selected to be either the pre-divider output or timer 1 When the PWM-mode is enabled timer 2 starts counting. As
underflow. soon as timer 2 underflows, timer 2 stops and timer 3 starts
• Operation counting. If bit 0 is set, timer 2 determines the low duration and
The timer counts down. On timer underflow, the corresponding the initial output level is low. Timer 3 determines the high dura-
timer interrupt request bit will be set to “1”, the contents of the tion. If bit 0 is zero timer 2 determines the high duration and the
corresponding timer latch will be reloaded to the counter and initial output level is high. In this case timer 3 determines the low
counting continues. duration.
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SERIAL I/Os
The 7632 has two USART interfaces. The interfaces are equal. internal or external clock. When internal clock is selected a pro-
Both contain a clock synchronous SIO and an UART as described grammable clock divider allows eight different transmission speeds.
in the following section. Either SIO or UART can be selected by set- Refer to Figure 23. The operation of the clock synchronous serial
ting the bit in Figure . I/O can be configured by the serial I/O control register SIOCON;
please refer to Figure 25.
Clock synchronous SI/O
The clock synchronous interface allows full duplex communication
based on 8 bit word length. The transfer clock can be selected to be
XIN SIOCON2, 1, 0
Clock divider
P83/SRDY1, P87/SRDY2 SIOCON4 SIOCON6

Sync. circuit
“1” “1”
“0”
“0”
P83, P87 latch
P82/SCLK1, P86/SCLK2 SIOCON3

SIO counter (3) SIO interrupt
“1”
“0”
P82, P86 latch
P81/SOUT1, P85/SOUT2 SIOCON3

SIO shift register (8)
“1”
“0”
P81, P85 latch
P80/SIN1, P84/SIN2 SIOCON3
“1”
“0”
P80, P84 latch
Fig. 23 Block diagram of clock synchronous I/O
Clock synchronous SI/O operation SIO1, address 007A16). After an eight bit transfer has been com-
pleted, the SOUT pin will change to high impedance and the SIO
Either internal or external transfer clock can be selected by bit 6 of
interrupt request bit will be set to “1”.
SIOCON. The internal clock divider can be programmed by bits 0 to
2 of SIOCON. Bit 3 of SIOCON determine if the double function If external transfer clock is selected, the SIO interrupt request bit
pins P80 to P82 and P84 to P86 will act as I/O ports or serve as SIO will be set to “1” after 8 cycles but the contents of the SI/O shift reg-
ister continue to be shifted while the transfer clock is being input.
pins. Bit 4 of SIOCON allows the same selection for pin P83 and
Therefore the clock needs to be controlled externally; the SOUT pin
P87.
will not change to high impedance automatically.
If internal transfer clock is selected, transmission can be triggered
by writing data to the SI/O shift register (SIO1, address 001A16,
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Synchronous clock
Transfer clock
Write signal to SIO
Receive enable signal SRDY
Serial Output TxD D0 D1 D2 D3 D4 D5 D6 D7
Serial input RxD D0 D1 D2 D3 D4 D5 D6 D7
SIO interrupt request bit = “1”
Note: When internal clock is selected, SOUT pin will change to high impedance after 8 bit of data have been transmitted.
Fig. 24 Timing of clock synchronous SI/O function (LSB first selected)
7 0
SIO1 control register (address 001B16)
SIO2 control register (address 007B16)
SIOCON1, SIOCON2
Clock divider selection bits
b2 b1 b0
0 0 0: f(XIN) divided by 8
P80/SIN1, P84/SIN2, P81/SOUT1 ,P85/SOUT2 and P82/SCLK1, P86/SCLK2function selection bit
0 : I/O port function
1 : SI/O function
P83/SRDY1, P83/SRDY2 function selection bit
1 : SI/O function
Transmission order selection bit
0 : LSB first
1 : MSB first
Synchronization clock selection bit
0 : Use external clock
1 : Use internal clock
Fig. 25 Structure of serial I/O control register, SIOCON
UART written to or read from directly, transmit data is written to the trans-
mit buffer and receive data is read from the receive buffer. A trans-
The UART is a full duplex asynchronous transmit/receive unit. The
mit or receive operation will be triggered by the transmit enable bit
built-in clock divider and baud rate generator enable a broad range
and receive enable bit of the UART control register UCON (see Fig-
of transmission speeds. Please refer to Figure 26. UART1 is
ure ). The double function pins P81/UTXD1, P83/URTS1 and
selected by setting bit 0 in UMOD1 Figure . UART2 is selected by
P80/URXD1, P82/UCTS1 and P85/UTXD2, P86/URTS2 and
setting bit 0 in UMOD2 Figure .
P84/URXD2, P87/UCTS2 will be switched to serve as UART pins
Description automatically.
The transmit and receive shift registers have a buffer (consisting of
high and low order byte) each. Since the shift registers cannot be
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Baud rate selection Handshaking signals

The baud rate of transmission and reception is determined by the When used as transmitter the UART will recognize the clear-to-
setting of the prescaler and the contents of the UART baud rate send signal via P82/UCTS1, P81/UTXD1, P83/URTS1 and
generator register. It can be calculated by using the following for- P80/URXD1 pin or P86/UCTS2, P85/UTXD2, P87/URTS2 and
mula: P84/URXD2 pin for handshaking. When used as receiver it will
issue a request-to-send signal through P83/URTS1 and P87/URTS2
f ( X IN ) pins.
b = -----------------------------------
16 ⋅ p ⋅ ( n + 1 )
Clear-to-send input
where p is the division ratio of the prescaler and n is the contents of When used as a transmitter (transmit enable bit set to “1”), the
the UART baud rate generator register. The prescalers division UART starts transmission after recognizing “L” level on P82/UCTS2
ration can be selected by the UART mode register (see below). or P86/UCTS2. After starting the UART will continue to transmit
UART mode register (UMOD, Figure 27) regardless of the actual level of P82/UCTS1 or P86/UCTS2 or status
of the transmit enable bit.
The UART mode register allows to select the transmission and
reception format with the following options: Request-to-send output
• word length: 7, 8 or 9 bits
The UART controls the P83/URTS1 or P87/URTS2 output according
• parity: none, odd or even to the following conditions.
• stop bits: 1 or 2
Table 4: Output control conditions
It allows to select the prescalers division ratio as well.
UART baud rate generator (UBRG) P83/URTS
Condition
This 8-bit register allows to select the baud rate of the UART (see P87/URTS
above). Set this register to the desired value before enabling recep-
Receive enable bit is set to “1”
tion or transmission.
Reception completed during receive enable “L”
UART control register (UCON, Figure 28) bit set to “1”
The UART control register consists of four control bits (bit 0 to bit 3)
Start bit (falling edge) detected
which allow to control reception and transmission.
Receive enable bit is set to “0” before recep-
UART status register (USTS, Figure 29) tion started “H”
The read-only UART status register consists of 7 bits (bit 0 to bit 6)
Hardware reset
which indicate the operating status of the UART function and vari-
ous errors. Receive initialization bit is set to “1”
Data bus
UART control register UART status register Transmit buffer (9)

XIN Transmit buffer empty flag
UMOD2,1
1/2 “00” UMOD7, 6 Transmit register empty interrupt request
1/16 “01” UBRG (8) Bit counter Transmit shift register (9) P81/UTXD1, P85/UTXD2
1/64 “10”
1/512 “11” UMOD5,4,3
Transmit register empty flag
Transmission
control circuit P82/UCTS1, P86/UCTS2
Reception control P83/URTS1, P87/URTS2

circuit
UMOD7, 6
Bit counter Receive shift register (9) P80/URXD1, P40/URXD2
Receive error flags
Receive buffer (9) Receive buffer full interrupt request
Receive buffer full flag
Data bus
Fig. 26 Block diagram of UART
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7 0 UART1 mode register (address 002816), UART2 mode register (address 003016)
U1MOD, U2MOD
SIO/UART Selection bit

0 : UART
1 : SIO
Clock divider selection bits
b2 b1
Stop bits selection bit
0 : One stop bit
1 : Two stop bits
Parity selection bit
0 : Even parity
1 : Odd parity
Parity enable bit
0 : Parity disabled
1 : Parity enabled
UART word length selection bits
b7 b6
0 0: 7 bits/word
0 1: 8 bits/word
1 0: 9 bits/word
1 1: —
Fig. 27 Structure of UART mode register, UMOD
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7 0
UART1 control register (address 002A16) UART2 control register (address 003216)
UCON1, UCON2
Transmit enable bit
0 : Transmit disabled (an ongoing transmission will be finished correctly)
1 : Transmit enabled
Receive enable bit

0 : Receive disabled (an ongoing reception will be finished correctly)
1 : Receive enabled
Transmission initialization bit
0 : No action
1 : Clear transmit buffer full flag and transmit shifter full flag, set the
transmit status register bits and stop transmission
Receive initialization bit
0 : No action
1 : Clear receive status flags and the receive enable bit
Transmit Interrupt selection bit
0 : Transmit shift register empty interrupt
1 : Transmit buffer empty interrupt
CTS/RTS function selection bit

1 : CTS/RTS function
Fig. 28 Structure of UART control register, UCON
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7 0
UART1 status register (address 002B16), UART2 status register (address 003316)
U1STS, U2STS
Transmission register empty flag

0 : Register full
1 : Register empty
Transmission buffer empty flag
0 : Buffer full
1 : Buffer empty
Receive buffer full flag
0 : Buffer full
1 : Buffer empty
Receive parity error flag
0 : No parity error detected
1 : Parity error detected
Receive framing error flag
0 : No framing error detected
1 : Framing error detected
Receive overrun flag
0 : No overrun detected
1 : Overrun detected
Receive error sum flag
0 : No error detected
1 : Error detected
Note : This register is read only; writing does not affect its contents.
Fig. 29 Structure of UART status register, USTS
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A-D CONVERTER
The A-D converter uses the successive approximation method with Channel Selector
8-bit resolution. The functional blocks of the A-D converter are
The channel selector selects one of the ports P70/AN0 to P77/AN7,
described below. Refer to Figure 30.
and inputs its voltage to the comparator.
Comparison Voltage Generator
A-D Conversion Register
The comparison voltage generator divides the voltage between
The A-D conversion register is a read-only register that stores the
AVSS and VREF by 256, and outputs the divided voltage.
result of an A-D conversion. This register must not be read during
an A-D conversion.
Data bus
b7 b0
A-D control register
A-D control circuit A-D interrupt request
P70/AN0
channel selector
Comparator A-D conversion register
Comparison voltage
P77/AN7 generator
VREF AVSS
Fig. 30 A-D converter block diagram
A-D Control Register (Figure 31) D conversion, and changes to “1” when an A-D conversion ends.
Writing “0” to this bit starts the A-D conversion. Bit 4 is the VREF
The A-D control register controls the A-D conversion process. Bits 0
input switch bit.
to 2 select a specific analog input pin. Bit 4 signals the completion
of an A-D conversion. The value of this bit remains “0” during an A-
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7 0 A-D control register (address 001D16)
ADCON
Analog input pin selection bits
b2 b1 b0
0 0 0: P70/AN0
0 0 1: P71/AN1
0 1 0: P72/AN2
0 1 1: P73/AN3
1 0 0: P74/AN4
1 0 1: P75/AN5
1 1 0: P76/AN6
1 1 1: P77/AN7
A-D conversion completion bit
0 : Conversion in progress
1 : Conversion completed
VREF input switch bit
0 : Off
1 : On
Fig. 31 Structure of A-D control register
A-D Converter Operation rupt request bit to “1”. The result of A-D conversion can be obtained
from the A-D conversion register, AD (address 001C16).
The comparator and its control circuit compare an analog input volt-
Note that the comparator is linked to a capacitor, so set f(XIN) to 500
age with the comparison voltage, then stores the result in the A-D
kHz or higher during A-D conversion.
conversion register. When an A-D conversion is complete, the con-
trol circuit sets the A-D conversion completion bit and the A-D inter-
WATCHDOG TIMER
The watchdog timer consists of two separate counters: one 7-bit regardless of the data written to the WDT register. Reading the
counter (WDH) and one 4-bit counter (WDL). Cascading both watchdog timer register will return the corresponding control bit sta-
counters or using the high-order counter allows only to select the tus, not the counter contents.
time-out to either 1048576 or 65536 cycles of the external clock. Once the WDT register is written to, the watchdog timer starts
Refer to Figure 32 and Figure 33. counting down and the watchdog timer interrupt is enabled. Once it
is running the watchdog timer can not be disabled or stopped
Both counters are addressed by the same watchdog timer register except by reset. On watchdog timer underflow a non-maskable
WDT. When writing to this register both counters will be set to the watchdog timer interrupt will be requested.
following default values: To prevent the system being stopped by STP instruction, this
instruction can be disabled by the STP instruction disable bit of
• the high-order counter will be set to address 7F16
WDT register. Once the STP instruction is disabled it can not be
• the low-order counter will be set to address F16 enabled again except by RESET.
XIN “1”
“0”
1/512 WDL counter (4) WDH counter (7) WDT interrupt
WDT7
“F16” “7F16”
WDT register (8)
Fig. 32 Block diagram of watchdog timer
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7 0
Watchdog timer register (address 003E16)
WDT
Not used (undefined when read)

Stop instruction disable bit
0 : Stop instruction enabled
1 : Execute two NOP instructions instead (once this bit is set to
“1” it can not be cleared to “0” again, except on RESET.)
Upper byte count source selection bit
0 : Underflow of the low order counter
1 : f(XIN) divided by 512
Fig. 33 Structure of watchdog timer register
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CAN MODULE
The CAN (Controller Area Network) interface of the 7632 group CAN Bus Timing Control
complies with CAN specification version 2.0, part B, enabling recep-
Each bit time consists of four different segments (see Figure 34):
tion and transmission of frames with either 11- or 29-bit identifier
• Synchronization segment (SS),
length. Refer to Figure 35 for a block diagram of the CAN interface.
• Propagation time segment (PTS),
The programmer’s interface to the CAN module is formed by one • Phase buffer segment 1 (PBS1) and
status/control register (Figure 38), two bus timing control registers • Phase buffer segment 2 (PBS2).
(Figure 39 and Figure 40), several registers for acceptance filtering
(Figure 41), the transmit and receive buffer registers (Figure 43)
and one dominant level control bit (Figure 12). Bit time
SS PTS PBS1 PBS2
Baud Rate Selection
A programmable clock prescaler is used to derive the CAN mod-
Sampling point
ule’s basic clock from the internal clock frequency fcan. fcan selection
is shown in Figure 48. Bit 0 to bit 3 of the CAN bus timing control Fig. 34 Bit time
register represent the prescaler allowing a division ratio from 1 to
The first of these segments is of fixed length (one Time Quantum)
1/16 to be selected. So the CAN module’s basic clock frequency
the latter three can be programmed to be 1-8 Time Quanta by the
fCANB can be calculated as follows:
CAN bus timing control register 1 and 2 (see Figures Figure 39 and
f can Figure 40). The whole bit time has to consist of 8(Min.) to 25(Max.)
f CANB = -----------------
(p + 1) Time Quanta. The duration of one Time Quantum is the cycle time
of fCANB. For example, assuming fcan = 5 MHz, p = 0, one Time
where p is the value of the prescaler (selectable from 1 to 15). The Quantum will be 200 ns long. This allows a maximum transmission
valid baud rate of the CAN bus communication depends on the rate of 625 kb/s to be reached (assuming 8 Times Quanta per bit
CAN bus timing control parameters and will be explained below. time).
Data bus
Polarity control CAN control register Bus timing control Acceptance mask Acceptance code
register register register register
Receive buffer 1
Acceptance filter
P41/CTX
Receive buffer 2
Protocol controller
P42/CRX
Transmit buffer
Wake-up logic CAN wake-up
Data bus
Fig. 35 CAN module block diagram
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7 0
CAN transmit control register (address 004016)
CTRM
Sleep control bit

0 : CAN module in normal mode
1 : CAN module in sleep mode
Reset/configuration control bit
0 : CAN module in normal mode
1 : CAN module in configuration mode (plus reset at write)
Port double function control bit
0 : P41/CTX serves as I/O port
1 : P41/CTX serves as CAN pin
Transmit request bit
0 : No transmission requested
1 : Transmission requested
(write “0” has no effect)
Not used (no operation, read as “0”)

Transmit buffer control bit
0 : CPU access possible
1 : No CPU access
( write “0” has no effect, while CTRM(3) = 1)
Not used (no operation, read as “0”)

Transmit status bit (read only)
0 : CAN module idle or receiving
1 : CAN module transmitting
Fig. 36 Structure of CAN transmit control register
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7 0
CAN receive control register (address 004D16)
CREC
Receive buffer control bit

0 : Receive buffer empty
1 : Receive buffer full
( write “1” has no effect )
Receive status bit (read only)

0 : CAN module idle or transmitting
1 : CAN module receiving
Not used (do not write “1”, read as “0”)
Receive interrupt disable bit (CAN module is transmitter)

0 : Receive Interrupt enabled
1 : Receive Interrupt disabled
Not used (do not write “1”, read as “0”)
Fig. 37 Structure of CAN receive control register
7 0
CAN transmit abort register (address 004E16)
CABORT
Transmit abort control bit

0 : No transmit abort request
1 : Transmit abort request
(write “1” has no effect, while CTRM(3) = 0)
Not used (No operation, read as “0”)
Fig. 38 Structure of CAN transmit abort request register
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7 0
CAN bus timing control register 1 (Address 004116)
CBTCON1
Prescaler division ratio selection bits

b3 b2 b1 b0
0 0 0 0: Division ratio 1
0 0 0 1: Division ratio 1/2
0 0 1 0: Division ratio 1/3
…
1 1 1 0 : Division ratio 1/15
1 1 1 1 : Division ratio 1/16
Sampling control bit
0 : One sample per bit
1 : Three sample per bit
Propagation time duration control bits
b7 b6 b5
0 0 0: One Time Quantum
0 0 1: Two Time Quanta
…
1 1 0: Seven Time Quanta
1 1 1: Eight Time Quanta
Fig. 39 Structure of CAN bus timing control register 1
7 0
CAN bus timing control register 2 (Address 004216)
CBTCON2
Phase buffer segment 1 duration control bits

b2 b1 b0
…
Phase buffer segment 2 duration control bits

b7 b6 b5
…
Synchronization jump width control bits

b7 b6
0 0: One Time Quantum
0 1: Two Time Quanta
1 0: Three Time Quanta
1 1: Four Time Quanta
Fig. 40 Structure of CAN bus timing control register 2
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Name 7 0 Address
Acceptance code CAC0 CSID10 CSID9 CSID8 CSID7 CSID6 004316
registers:
CAC1 CSID5 CSID4 CSID3 CSID2 CSID1 CSID0 004416
CAC2 CEID17 CEID16 CEID15 CEID14 004516
CAC3 CEID13 CEID12 CEID11 CEID10 CEID9 CEID8 CEID7 CEID6 004616
CAC4 CEID5 CEID4 CEID3 CEID2 CEID1 CEID0 004716
Select the bit pattern of identifiers which allows to pass acceptance filtering.
7 0
Acceptance mask CAM0 004816
MSID10 MSID9 MSID8 MSID7 MSID6
registers:
CAM1 MSID5 MSID4 MSID3 MSID2 MSID1 MSID0 004916
CAM2 MEID17 MEID16 MEID15 MEID14 004A16
CAM3 MEID13 MEID12 MEID11 MEID10 MEID9 MEID8 MEID7 MEID6 004B16
CAM4 MEID5 MEID4 MEID3 MEID2 MEID1 MEID0 004C16
0 : Mask identifier bit (do not care)

1 : Compare identifier bit with acceptance code register bit
Fig. 41 Structure of CAN mask and code registers
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Acceptance Filter Support Unit

The Acceptance Filter Support Unit (ASU) provides a set of regis- which ease the implementation of efficient acceptance filtering rou-
ters tines.The ASU uses the following register mapping:
Name 7 0 Address
ASU Write Register ASID SID10 SID9 SID8 SID7 SID6 007016
Map: CSID SID5 SID4 SID3 SID2 SID1 SID0 007116
Name 7 0 Address
ASU Read Register 007016
ASID SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3
Map:
CSID CSID7 CSID6 CSID5 CSID4 CSID3 CSID2 CSID1 CSID0 007116
Fig. 42 Structures of ASU registers for reading and writing

Table 5: 3 to 8 decoder truth table
The write registers need the first two bytes of the receive buffer as
input. As illustrated in Figure 41 these bytes contain the standard 3 bit 8 bit
identifier bits of the received message and some control bits as 2 1 0 7 6 5 4 3 2 1 0
well. These control bits may be written into the ASU as well but are
0 0 0 0 0 0 0 0 0 0 1
ignored.
Consecutive read access to the same addresses provides the iden- 0 0 0 0 0 0 0 0 0 1 0
tifier bits in a new or converted order. So CSID is 3 to 8 decoded .
from SID2.SID0 (refer to Figure 42 and Table 5 ). .
The presentation of identifier bits in the read registers is suitable for .
an efficient software acceptance filtering of a received CAN mes-
1 1 1 1 0 0 0 0 0 0 0
sage.
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Name 7 0 Offset
CTB0, CRB0 SID10 SID9 SID8 SID7 SID6 000016
CTB1, CRB1 SID5 SID4 SID3 SID2 SID1 SID0 RTR/SRR IDE 000116
CTB2, CRB2 EID17 EID16 EID15 EID14 000216
CTB3, CRB3 EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6 000316
CTB4, CRB4 EID5 EID4 EID3 EID2 EID1 EID0 RTR r1 000416
CTB5, CRB5 r0 DLC3 DLC2 DLC1 DLC0 000516
CTB6, CRB6 Data byte 0 000616
CTBA, CRBA Data byte 4 000A16
CTBB, CRBB Data byte 5 000B16
CTBC, CRBC Data byte 6 000C16
CTBD, CRBD Data byte 7 000D16
Calculate the actual address as follows:

TxD buffer address = 005016 + offset
RxD buffer address = 006016 + offset
Fig. 43 Structure of CAN transmission and reception buffer registers
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RESET
The 7632 group is put into reset state by holding RESET pin at “L”
level for 2 µs or longer while the power source voltage is within the
Power on
specified range and XIN is in stable oscillation. The CPU and special
function registers are initialized according to the values shown in
Figure 46. After releasing RESET pin to “H” level, program execu- Power source voltage 4.0 V
tion starts from the address formed by the contents of the
addresses FFFBh and FFFAh. 0V
Refer to Figure . for an example of a power-on reset circuit.
Reset input voltage
0.8 V
0V
VCC
5
RESET
M51953AL 0.1 µF
4
3
VSS
7632 group
Fig. 44 Example of reset circuit
XIN
RESET
internal reset
Address ? ? ? ? ? FFFA16 FFFB16 ADL, ADH …
Data ? ? ? ? ? ADL ADH 1st op code
28 to 34 24 cycles of XIN 20 cycles of XIN

8192 cycles cycles of XIN
of XIN (T1, T2)
Fig. 45 Reset sequence
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Register Address Register contents Register Address Register contents

CPU mode register 000016 4816 UART1 mode register 002816 0016
Interrupt request register A 000216 0016 UART1 control register 002A16 0016
Interrupt request register B 000316 0016 UART1 status register 002B16 0716
Interrupt request register C 000416 0016 UART2 mode register 003016 0016
Interrupt control register A 000516 0016 UART2 control register 003216 0016
Interrupt control register B 000616 0016 UART2 status register 003316 0716
Interrupt control register C 000716 0016 Port P0/ P1/ P2/ P3 pull-up schmitt
003816 0016
trigger control register
Port P0register 000816 0016
Port P4 pull-up/down control regis-
Port P0 direction register 000916 0016 003916 0016
ter
Port P1register 000A16 0016 Port P5 pull-up control register 003A16 0016
Port P1 direction register 000B16 0016 Port P6 pull-up control register 003B16 0016
Port P2 register 000C16 0016 Port P7 pull-up control register 003C16 0016
Port P2 direction register 000D16 0016 Port P8 pull-up control register 003D16 0016
Port P3 register 000E16 0016 Watchdog timer register 003E16 3F16
Port P3 direction register 000F16 0016 Polarity control register 003F16 0016
Port P4 data register 001016 0016 CAN transmit register 004016 0216
Port P4 direction register 001116 0016 CAN bus timing control register 1 004116 0016
Port P5 register 001216 0016 CAN bus timing control register 2 004216 0016
Port P5 direction register 001316 0016 CAN receive register 004D16 0016
Port P6 register 001416 0016 CAN abort register 004E16 0016
Port P6 direction register 001516 0016 Serial I/O2 control register 007B16 0016
Port P7 register 001616 0016 Interrupt polarity selection register 007D16 0016
Port P7 direction register 001716 0016 Processor status register (PS) 0416
Port P8 register 001816 0016 Program counter (high-order byte) (PCH) content of FFFB16
Port P8 direction register 001916 0016 Program counter (low-order byte) (PCL) content of FFFA16
Serial I/O1 control register 001B16 0016
A-D control register 001D16 0816
Timer 1 001E16 FF16
Timer 2 001F16 0116
Timer 3 002016 FF16
Timer 123 mode register 002116 4016
Timer XL 002216 FF16
Timer XH 002316 FF16
Timer YL 002416 FF16
Timer YH 002516 FF16
Timer X mode register 002616 0016
Timer Y mode register 002716 0016
Note: The contents of registers RAM and registers other than above are undefined after reset; thus software initialization
is required.
Fig. 46 Internal status of microcomputer after reset
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CLOCK GENERATING CIRCUIT

The 7632 group is equipped with an internal clock generating cir- Timers 1 and 2 will be cascaded and initialized by their reload
cuit. latches’ contents. The count source for timer 1 will be set to
Refer to Figure 47 as a circuit example using a ceramic resonator f(XIN)/16.
or quartz-crystal oscillator. For the capacitor values, refer to the
Oscillation is restarted when an external interrupt is accepted or at
manufacturers recommended parameters which depend on each
reset. When using an external interrupt, internal clock ø remains at
oscillators characteristics. When using an external clock, input it to
“H” level until timer 2 underflows allowing a time-out until the clock
the XIN pin and leave XOUT open.
oscillation becomes stable. When using reset, a fixed time-out will
be generated allowing oscillation to stabilize.
Wait mode
XIN XOUT
The microcomputer enters the wait mode by executing the WIT
instruction. Internal clock ø stops at “H” level while the oscillator
keeps running.
CIN COUT Recovery from the wait mode can be done in the same way as from
stop mode. However, the time-out period mentioned above is not
required to return from the wait-mode, thus no such time-out mech-
anism has been implemented.
Fig. 47 Ceramic resonator circuit
Note: Set the interrupt enable bit of the interrupt source to be used
to return from the stop or wait mode to “1” before executing STP or
WIT instruction.
Oscillation Control
The 7632 group has two low power modes: the stop and the wait Middle Speed Mode
mode.
The microcomputer enters the middle speed mode by selecting bit
Stop mode
6 of CPMA. In this mode the CPU clock is f(Xin)/8. The clock for all
The microcomputer enters the stop mode by executing the STP peripherals is still f(Xin)/2. Because of this also a CAN transmission
instruction. The oscillator stops with internal clock ø at “H” level. will not be affected.
XOUT 1/4
“1”
“0”
CPUM6
XIN
1/2 Internal clock
for
peripherals
Interrupt request R Q D Q
Interrupt disable flag
S Q STP S T
RESET
STP delay R
Internal clock
for CPU
R Q
D Q
STP S
T
Oscillator countdown R Q P2
(Timer 1 and 2)
WIT S
Fig. 48 Block diagram of clock generating circuit
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DATA REQUIRED FOR MASK ORDERS

The following items are necessary when ordering a mask ROM pro-
Programming with PROM programmer
duction:
[1] Mask ROM Order Confirmation Form
[2] Mark Specification Form
[3] Contents of Mask ROM, in EPROM form (three identi-
cal copies) Screening *Note
(150 °C for 40 hours)
PROM PROGRAMMING METHOD

The built-in PROM of the blank One Time PROM version and built-
in EPROM version can be read or programmed with a general pur- Verification with PROM programmer
pose PROM programmer using a special programming adapter. Set
the address of PROM programmer to the user ROM area.
For the programming adapter type name, refer to the following
table:
Table 6: Programming adapter name
Functional test in target unit
MCU type Package Programming adapter type
One Time Note :

80P6S-A PCA7431
PROM The screening temperature is at the limit of the storage temper-
EPROM 80DO PCA4731 ature ratings. Never subject the device to 150 °C exceeding
100 hours.
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and the following processes. To Fig. 49 Programming and testing of One Time PROM version
ensure proper operation after programming, the procedure shown
in Figure 49 is recommended to verify programming.
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Table 7: Absolute maximum ratings
Symbol Parameter Conditions Ratings Unit

VCC Power source voltage –0.3 to 7.0 V
Input voltage P00—P07, P10—P17,
P20—P27, P30—P37,
VI P40—P47, P50—P57, –0.3 to VCC + 0.3 V
P60—P67, P70—P77, All voltages with respect to
P80—P87, RESET, XIN VSS and output transistors
Output voltage P00—P07, P10—P17, are “off”.
P20—P27, P30—P37,
VO P40—P47, P50—P57, –0.3 to VCC + 0.3 V
P60—P67, P70—P77,
P80—P87, XOUT
Pd Power dissipation Ta = 25°C 500 mW
Topr Operating temperature –40 to 85 °C
Tstg Storage temperature –60 to 150 °C
Table 8: Recommended operating conditions (VCC = 4.0 to 5.5V, VSS = AVSS = 0V, Ta = –40 to 85 °C unless otherwise noted)
Limits
Symbol Parameter Unit
min. typ. max.
VCC 4.0 5.0 5.5 V
Power source voltage
VSS 0 V
P00—P07, P10—P17,
P20—P27, P30—P37,
VIH “H” Input voltage P40—P47, P50—P57, 0.8 · VCC VCC V
P60—P67, P70—P77,
P80—P87,RESET, XIN
P00—P07, P10—P17,
P20—P27, P30—P37,
VIL “L” Input voltage P40—P47, P50—P57, 0 0.2 · VCC V
P60—P67, P70—P77,
P80—P87, RESET, XIN
P00—P07, P10—P17,
VIH “H” Schmitt trigger Input 2.5 VCC V
P20—P27, P30—P37,
“L” Schmitt trigger Input P00—P07, P10—P17,
VIL VSS 1.3 V
P20—P27, P30—P37,
P00—P07, P10—P17,
P20—P27, P30—P37,
∑ IOH (peak) “H” sum peak output current P40—P47, P50—P56, –80 mA
P60—P67, P70—P77,
P80—P87
∑ IOH (avg) “H” sum average output current –40 mA
∑ IOL (peak) “L” sum peak output current 80 mA
∑ IOL (avg) “L” sum average output current 40 mA

IOH (peak) “H” peak output current –10 mA
IOH (avg) “H” average output current –5 mA
IOL (peak) “L” peak output current 10 mA
IOL (avg) “L” average output current 5 mA
P65/CNTR0, P66/CNTR1
f(XIN)/16 MHz
Timer input frequency (except bi-phase counter mode)
f(CNTR)
(based on 50% duty) P64/TX0, P65/CNTR0
f(XIN)/32 MHz
(bi-phase counter mode)
f(XIN) Clock input oscillation frequency 10 MHz
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Table 9: Electrical characteristics (1) (VCC = 4.0 to 5.5V, VSS = AVSS = 0V, Ta = –40 to 85 °C unless otherwise noted)
Test Limits
conditions min. typ. max.
P00—P07, P10—P17,P20—P27,
VOH “H” output voltage P30—P37,P40—P47, P50—P56, IOH = –5.0mA VCC – 2.0 V
P60—P67, P70—P77,P80—P87
P00—P07, P10—P17,P20—P27,
VOL “L” output voltage P30—P37,P40—P47, P50—P56, IOH = 5.0mA 2.0 V
P60—P67, P70—P77,P80—P87
P42/CRX, P50/KW0- P57/KW7,
P62/INT0, P63/INT1, P64/TX0,
P65/CNTR0, P66/CNTR1,
VT+ – VT– Hysteresis P80/SIN1/URXD1, P82/SCLK1/UCTS1, 0.5 V
P83/SRDY1/URTS1, P84/SIN2/URXD2,
P86/SCLK2/UCTS2, P87/SRDY2/URTS2,
RESET
Hysteresis for Schmitt- P00—P07, P10—P17,
VT+ – VT– 0.5 V
trigger Input P20—P27, P30—P37
P00—P07, P10—P17, P20—P27,
P30—P37,P40—P47, P50—P57,
IIH “H” input current VI = VCC 5 µA
P60—P67, P70—P77, P80—P87,
RESET
IIH “H” input current XIN VI = VCC 4 µA
P00—P07, P10—P17, P20—P27,
P30—P37,P40—P47, P50—P57,
IIL “L” input current VI = VSS –5 µA
P60—P67, P70—P77, P80—P87,
RESET
IIL “L” input current XIN VI = VSS –4 µA
input current at over-volt- P00—P07, P10—P17, P20—P27,
IIO(peak) age condition P30—P37, P40—P47, P50—P57, 2 mA
(VI > VCC) P60—P67, P80—P87,
total input current at P00—P07, P10—P17, P20—P27,
∑ IIO(peak) overvoltage condition P30—P37, P40—P47, P50—P57, 50 mA
(VI > VCC) P60—P67, P80—P87
input current at under- P00—P07, P10—P17, P20—P27,
IIO(peak) voltage condition P30—P37, P40—P47, P50—P57, -2 mA
(VI < VSS) P60—P67, P80—P87,
total input current at und- P00—P07, P10—P17, P20—P27,
∑ IIO(peak) ervoltage condition P30—P37, P40—P47, P50—P57, - 50 mA
(VI < VSS) P60—P67, P80—P87
P00—P07, P10—P17,
input current at over-volt- P20—P27, P30—P37,
IIO age condition P40—P47, P50—P57, 1 mA
(VI > VCC) P60—P67,
P80—P87,
P00—P07, P10—P17,
total input current at
∑ IIO
P20—P27, P30—P37,
overvoltage condition 16 mA
P40—P47, P50—P57,
(VI > VCC)
P60—P67, P80—P87
P00—P07, P10—P17,
input current at under- P20—P27, P30—P37,
IIO voltage condition P40—P47, P50—P57, -1 mA
(VI < VSS) P60—P67,
P80—P87,
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Table 9: Electrical characteristics (2) (VCC = 4.0 to 5.5V, VSS = AVSS = 0V, Ta = –40 to 85 °C unless otherwise noted)
Test Limits
conditions min. typ. max.
P00—P07, P10—P17,
total input current at und-
P20—P27, P30—P37,
∑ IIO ervoltage condition
P40—P47, P50—P57,
- 16 mA
(VI < VSS)
P60—P67, P80—P87
RAM hold voltage when clock
VRAM 2.0 V
stopped
high-speed
mode,
f(XIN) = 8 MHz,
VCC = 5 V, out-
12.0 20.0 mA
put transistors
off, CAN mod-
ule running,
ADC running
high-speed
mode,
f(XIN) = 8 MHz,
VCC = 5 V, out-
10.0 18.0 mA
put transistors
off, CAN mod-
ule stopped,
ADC running
middle-speed
mode,
f(XIN) = 8 MHz,
VCC = 5 V, out-
6.0 11.0 mA
ICC Power source current put transistors
off, CAN mod-
ule running,
ADC running
middle-speed
mode, wait
mode,
f(XIN) = 8 MHz,
VCC = 5 V, out- 2.5 mA
put transistors
off, CAN mod-
ule stopped,
ADC stopped
stop-mode,
f(XIN) = 0 MHz,
VCC = 5 V, 0.1 1.0 µA
Ta = 25 °C
stop-mode,
f(XIN) = 0 MHz,
VCC = 5 V, 10.0 µA
Ta = 85 °C
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Table 10: A-D converter characteristics (VCC = 4.0 to 5.5V, VSS = AVSS = 0V, Ta = –40 to 85 °C unless otherwise noted)
Limits
Symbol Parameter Test conditions Unit
min. typ. max.
— Resolution 8 Bit
— Absolute accuracy ±1.0 ±2.0 LSB
high-speed mode 106 108 tC(XIN)
tCONV Conversion time
middle-speed mode 424 432 tC(XIN)
VREF Reference input voltage 4.0 VCC V
IREF Reference input current VCC = VREF = 5.12 V 150 200 µA
RLADDER Ladder resistor value 35 kΩ
IIAN Analog input current VI = VSS to VCC 0.5 5.0 µA
IIAN Analog input current 0.45V < VSS < VI < VCC 1.0 µA
Permissible input cur-
rent at overvoltage
applied to one chan-
nel of P7 not affecting
IInjAN 1), 2) VIN > VCC 250 µA
the absolute accuracy
of conversion at
another channel (not
at overvoltage).
1) If this current is injected to the channel used for AD conversion, the absolute accuracy of the conversion is affected.
2) The absolute accuracy of the conversion result will be over +/- 2.0 LSB, if IInjAN is larger than 250 µA.
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Table 11: Timing requirements (VCC = 4.0 to 5.5V, VSS = AVSS = 0V, Ta = –40 to 85 °C unless otherwise noted)
Limits
min. typ. max.
tW(RESET) Reset input “L” pulse width 2 µs
tC(XIN) External clock input cycle time 100 ns
tWH(XIN) External clock input “H” pulse width 37 ns
tWL(XIN) External clock input “L” pulse width 37 ns
CNTR0, CNTR1 input cycle time
1600 ns
tC(CNTR) (except bi-phase counter mode)
CNTR0 input cycle time (bi-phase counter mode) 3200 ns
CNTR0, CNTR1 input “H” pulse width
800 ns
tWH(CNTR) (except bi-phase counter mode)
CNTR0 input “H” pulse width (bi-phase counter mode) 1600 ns
CNTR0, CNTR1 input “L” pulse width
800 ns
tWL(CNTR) (except bi-phase counter mode)
CNTR0 input “L” pulse width (bi-phase counter mode) 1600 ns
Lag of CNTR0 and TX0 input edges
tL(CNTR0-TX0) 800 ns
(bi-phase counter mode)
tC(TX0) TX0 input cycle time (bi-phase counter mode) 3200 ns
tWH(TX0) TX0 input “H” pulse width (bi-phase counter mode) 1600 ns
tWL(TX0) TX0 input “L” pulse width (bi-phase counter mode) 1600 ns
tWH(INT) INT0, INT1 input “H” pulse width 460 ns
tWL(INT) INT0, INT1 input “L” pulse width 460 ns
tC(SCLK) Serial I/O clock input cycle time 8 · tC(XIN) ns
tWH(SCLK) Serial I/O clock input “H” pulse width 4 · tC(XIN) – 50 ns
tWL(SCLK) Serial I/O clock input “L” pulse width 4 · tC(XIN) – 50 ns
tSU(SIN–SCLK) Serial I/O input setup time 200 ns
tH(SCLK–SIN) Serial I/O input hold time 200 ns
Table 12: Switching characteristics (VCC = 4.0 to 5.5V, VSS = AVSS = 0V, Ta = –40 to 85 °C unless otherwise noted)
Limits
min. typ. max.
tWH(SCLK) Serial I/O clock output “H” pulse width 0.5 · tC(SCLK) – 50 ns
tWL(SCLK) Serial I/O clock output “L” pulse width 0.5 · tC(SCLK) – 50 ns
tD(SCLK–SOUT) Serial I/O output delay time 50 ns
tV(SCLK–SOUT) Serial I/O output valid time 0 50 ns
tR(SCLK) Serial I/O clock output rise time 50 ns
tR(CMOS) CMOS output rise time 10 50 ns
tF(CMOS) CMOS output fall time 10 50 ns
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Measurement output pin
100 pF
CMOS output
Fig. 50 CMOS output
TIMING DIAGRAM
tC(TX0)
tWH(TX0) tWL(TX0)
TX0 0.8·VCC
0.2·VCC
tC(CNTR)
tWH(CNTR) tWL(CNTR)
CNTR0, CNTR1 0.8·VCC

0.2·VCC
tWH(INT) tWL(INT)
INT0, INT1 0.8·VCC

0.2·VCC
tWL(RESET)
RESET
0.2·VCC
tC(XIN)
tWH(XIN) tWL(XIN)
XIN 0.8·VCC
0.2·VCC
tC(SCLK)
tF tWL(SCLK) tR tWH(SCLK)
SCLK 0.8·VCC
0.2·VCC
tSU(SIN-SCLK) tH(SCLK-SIN)
SIN 0.8·VCC
0.2·VCC
tD(SCLK-SOUT) tV(SCLK-SOUT)
SOUT
Fig. 51 Timing diagram
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REVISION DATE Page MODIFICATIONS
1.0 05.11.98 Newly issued
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Keep safety first in your circuit designs!

• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead
to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, wit h appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-
flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
• These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customers application; they do not convey any license under any intellectual
property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
• Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in
these materials.
• All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric
Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for
the latest product information before purchasing a product listed herein.
• Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric
Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical,
aerospace, nuclear or undersea repeater use.
• The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
• If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved
destination.
Any diversion or re-export contrary to the export controls laws and regulations of Japan and/or the country of destination is p rohibited.
• Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained herein.
This data sheet, or parts thereof may not be reproduced in any form without permission of Mitsubishi Electric Corporation.
© 1996 Mitsubishi Electric Corporation
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Mitsubishi Electric Europe Mitsubishi Electric Europe

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Tel.: 02102/486-0 GB-Herts. AL10 8XB.
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MITSUBISHI
ELECTRIC 51

7632 Group: Description

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MITSUBISHI MICROCOMPUTERS

DESCRIPTION Schmitt trigger input ports . . . . . . . . . . . . . . . . . . . 32 selectable

PIN CONFIGURATION (TOP VIEW)

Package type: 80P6S-A

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

P8 (8) P7 (8) P6 (8) P5 (8) P4 (8) P3 (8) P2 (8) P1 (8) P0 (8)

E: ation. 7632 Group

E: ation. 7632 Group

Processor Mode Bits (set these bits to “00”)

Stack Page Selection Bit

Fig. 3 Structure of CPU Mode Register

E: ation. 7632 Group

RAM size Address 000016

192 013F16 004016 SFR area

512 027F16 010016

ROM size Address Address

49152 400016 408016

Fig. 4 Memory map

E: ation. 7632 Group

SPECIAL FUNCTION REGISTERS (SFR)

Fig. 5 Memory map of special function registers(SFR) (1)

E: ation. 7632 Group

006016 CAN receive buffer 0 CRB0 007016 Acceptance SID(11:3) ASID

Fig. 6 Memory map of special function registers(SFR) (continued) (2)

E: ation. 7632 Group

Port Pij control bit (j = 0 to 7)

Port Pij direction control bit (j = 0 to 7)

Fig. 7 Structure of port- and port direction registers

E: ation. 7632 Group

Pull-up control bit Pull-up control bit

Data bus Port latch Data bus Port latch

Schmitt trigger selection bit

Data bus Port latch

Reception in progress Pull-up control bit Pull-up control bit

Port latch Data bus Port latch

URXD input SIO output

Reception in progress Pull-up control bit Pull-up control bit

Data bus Port latch Data bus Port latch

UTXD output SIO clock output External clock input

Fig. 8 Structure of port I/Os (1)

E: ation. 7632 Group

RTS/CTS selection bit

Data bus Port latch Data bus Port latch

URXD or UCTS input SRDY output

RTS/CTS selection bit

Receive enable bit

Data bus Port latch

Timer bi-phase mode input

(13) Ports P65/CNTR0, P66/CNTR1 (14) Port P67/PWM

Pull-up control bit Pull-up control bit

PWM output enable

Data bus Port latch Data bus Port latch

(15) Port P41/CTX (16) Port P42/CRX

CAN dominant level control bit

Data bus Port latch

CTX output CAN interrupt

Fig. 9 Structures of port I/Os (2)

E: ation. 7632 Group

(17) Ports P62/INT0, P63/INT1 (18) Ports P70/AN0 to P77/AN7

Pull-up control bit

Data bus Port latch

Interrupt input ADC input

Fig. 10 Structures of port I/Os (3)