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This research was supported in part by the Semiconductor Research Figure 1. Conventional Op-Amp circuit structure
Corporation under Contract No. 2003-TJ-1068, the DARPA/ITO under
AFRL Contract F29601-00-K-0182, the National Science Foundation The high speed Op-Amp method presented in this paper is
under contract No. CCR-0304574, the Fulbright Program under Grant illustrated in Figure 2. Unlike a conventional circuit structure,
No. 87481764, grants from the New York State Office of Science, the OTA is compensated using a Miller capacitance connected
Technology & Academic Research to the Center for Advanced between the input and output of the buffer. Assuming that the
Technology – Electronic Imaging Systems and to the Microelectronics Op-Amp drives a parallel combination of a capacitor CL and a
Design Center, and by grants from Xerox Corporation, IBM Corporation,
resistor RL, the effective capacitance seen at the input and output
Intel Corporation, Lucent Technologies Corporation, and Eastman Kodak
Company.
of the buffer is
M7 M8
Auxiliary Vb4 Auxiliary
Amplifiers 1 Amplifiers 1
M1 M2
Vout + Vout -
Figure 2. High speed Op-Amp circuit structure M9 Vin + Vin - M10
624
Auxiliary Amplifier 1 Auxiliary Amplifier 2 A schematic of the threshold voltage referenced self-biasing
Vdd Vdd
circuit is illustrated in Figure 7. The circuit is used to generate
MAu1 MAu7 MAu5 the voltages required to bias the OTA core, auxiliary amplifiers,
In
VAu11 VAu21 CMFB circuit, and buffers. The transistors MBias5, MBias6, MBias7,
Out and MBias8 and the 11 k resistor constitute a threshold voltage
M Au2 Vdd MAu3 referenced current generator. Note that a start-up circuit (MBias1-
MAu8
In
VAu12
VAu22
MBias4) is utilized to avoid zero current flow in the current
Out
MAu6 generator.
MAu4 Vdd
VAu23
VAu12 MBias1 MBias5 MBias7
MBias9 MBias10 M Bias11
M Bias4 VAu22
M Bias2 VB1 VB2,VCF2
V Au21
Figure 4. Schematic of the auxilary amplifiers
MBias8 MBias12 M Bias13 MBias14
to maintain the output common voltage at the required level (900 11K
mV), while maximizing the output swing of the OTA. The inputs Vdd Vdd
to the circuit are the outputs of the OTA, Vout+ and Vout-. The
MBias17 MBias18
CMFB circuit amplifies the difference between the average of M Bias15 MBias16 MBias19 MBias20
Vout+ and Vout- and the desired common level Vcm (900 mV), and VBF1 VAu12
sends a feedback signal VB4 to set the bias voltage at the gates of VBF2 VCF1,VAu11 VAu23 VB3
M5 and M6 (see Figure 3). Also note that the tail current of the M Bias21 MBias22 MBias23 MBias24 M Bias25 M Bias26
CMFB circuit is set at 50 µA to reduce power consumption.
Vdd
MCF9 MCF10
Figure 7. Schematic of the self-biasing circuit
M BF2
VBF1
MBF3
625
(see Figure 1) results in a unity gain frequency of 251 MHz and a capacitance between the input and output of the buffer. This
phase margin of 37o with Cc=1.4 pF. configuration results in a significant improvement both in the
Convential Op-Amp unity gain frequency and phase margin, providing higher speed
80 and improved stability.
60
Gain ( dB )
-100
-120
-140
is 12 mW with a 1.8 volt single power supply.
-160
-180
PM = 37.3°
Table 1. Unity gain frequency (fµ) and phase margin (P.M.) for
-200
0 2 4 6 8 10
conventional and proposed Op-Amp circuit structures
10 10 10 10 10 10
Log Frequency ( Hz )
Conventional Proposed
(a)
Proposed Op-Amp
fµ P.M. fµ P.M. RL CL
80
Gain ( dB )
60
40
224 MHz 20° 672 MHz 69° 1 pF
20
0
Fm = 392.1 Mhz 166 MHz 14° 413 MHz 73° 2 pF
-20
-40 138 MHz 11° 299 MHz 73° 3 pF
-60
Phase ( Deg )
-80
287 MHz 49° 582 MHz 80° 1 k 1 pF
-100
-120
-140
251 MHz 37° 392 MHz 73° 1 k 2 pF
PM = 73.05°
-160
-180 222 MHz 31° 307 MHz 67° 1 k 3 pF
-200
0 2 4 6 8
10 10 10
Log Frequency ( Hz )
10 10
298 MHz 41° 617 MHz 75° 2 k 1 pF
(b) 248 MHz 30° 402 MHz 71° 2 k 2 pF
Figure 9. Open loop gain and phase response versus frequency, 215 MHz 24° 308 MHz 66° 2 k 3 pF
(a) convential Op-Amp, (b) proposed Op-Amp
297 MHz 37° 630 MHz 73° 3 k 1 pF
The gain and phase response obtained using the proposed
compensation scheme (see Figure 2) is shown in Figure 9(b) for 242 MHz 27° 405 MHz 70° 3 k 2 pF
the same load and compensation capacitance. In this method, the 208 MHz 22° 306 MHz 66° 3 k 3 pF
unity gain frequency and phase margin are 392 MHz and 73o,
respectively. Note that both the bandwidth and stability of the 138 MHz 17° 154 MHz 45° 1 k 10 pF
Op-Amp are significantly improved.
103 MHz 9° 125 MHz 52° 10 k 10 pF
As shown in Figure 9, the location of the dominant pole is close
274 MHz 28° 654 MHz 70° 10 k 1 pF
for both methods, as discussed in Section 2. This behavior
demonstrates that the proposed compensation scheme shifts the 311 MHz 71° 1.36 GHz 93° 1 k 0 pF
first non-dominant pole to a higher frequency, while maintaining
unaltered the location of the dominant pole. 6. REFERENCES
The unity gain frequency (fµ) and phase margin (P.M.) of both [1] A. Younis and M. Hassoun, “A High Speed Fully
the conventional and proposed compensation schemes are listed Differential CMOS Opamp,” Proceedings of the IEEE
in Table 1 for various loads. Note that the compensation Midwest Symposium on Circuits and Systems, Vol. 2, pp.
capacitance is a constant Cc=1.4 pF in all cases. These results 780-783, August 2000.
show that the proposed compensation scheme simultaneously [2] P. E. Allen and D. R. Holberg, CMOS Analog Circuit
results in a higher unity gain frequency and an improved phase Design. Oxford University Press, 2002.
margin under all load conditions. The improvement, however, is [3] R. J. Baker, H. W. Li, and D. E. Boyce, CMOS Circuit
dependent upon the specific values of the compensation Design, Layout, and Simulation. IEEE Press, 1998.
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John Wiley & Sons, 1997.
5. CONCLUSIONS [5] B. Razavi, Design of Analog CMOS Integrated Circuits.
McGraw-Hill, 2001.
A method is presented to efficiently compensate buffered Op- [6] TSMC 0.18-Micron Technology, Taiwan Semiconductor
Amps. In this approach, the OTA is compensated by connecting Manufacturing Company Ltd., Taiwan, April 2003.
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