Running a Behavioral Simulation in Xilinx for Combinational Logic

The Xilinx ISE software has the ability to run a behavioral simulation which is used to verify the
functionality of a circuit. The behavioral simulation provides timing diagrams to understand and
debug circuit operation. These instructions use the following combinational circuit:

The Xilinx help system has instructions for doing a behavioral simulation on a counter. These
instructions are found by selecting Help -> Tutorials -> ISE Quick Start, then selecting the
“Design Simulation” section of the “ISE Quick Start Tutorial.”

To run a behavioral simulation, go to the “Sources” window in Xilinx (usually the upper left
window) select “Behavioral Simulation” from the drop-down box in the top right corner of the
window.

Right click on the *.sch file and select “New Source”.

The “New Source Wizard” should start. Select the “Test Bench WaveForm” type and give this
source a file name (ex: *_test) and click Next. You will then select a source to associate this new
source file with. After selecting the file (it will probably already be selected) click the Next
button, review the information in the summary window and click the Finish button.

The ‘Initial Timing and Clock Wizard’ window should open. For testing a combinational circuit,
select “Combinational (or internal clock)” in the “Clock Information” section of the Wizard and
click Finish. [Note that larger combinational circuits with more inputs may require a longer
length of time for testing than the initial 1000 ns that is the default value.]
A new tab(s) will be added to the various Xilinx windows. The main window will display all the
inputs and outputs in a timing diagram format. Clicking in the turquoise areas of the timing
diagram toggles the values of the inputs that will be used in a behavioral simulation.

When setting up the inputs, the diagram may be used like a truth table. Set the inputs at different
highs and low. Then, when the simulation is run, the simulation output shows the output values
for the various input values. This final wave form may be compared to a truth table for the
circuit to verify that it is operating as desired.

As shown in the picture below, the input variables have an arrow pointing in (to the right).
These are used by clicking on the turquoise sections to change the input signals. Some, or all
combinations of input values, may be used to test the circuit. In this screen, the output(s) are
show as zero(s), they will show data after the simulation is run.

In the display shown above, values picked for the inputs are:
Time 100 200 300 400 500 600 700 800 900
A 0 1 0 1 0 1 0 1 0
B 0 0 1 1 0 0 1 1 0
C 0 0 0 0 1 1 1 1 0

For this simulation the schematic is:

And the expected output is:

X 1 1 1 1 0 0 0 1 1
Once the inputs are set as desired, the simulation is ready to run. Save the simulation (Ctrl-s)
and save often.

In the Sources windows (upper left window), make sure the “Behavioral Simulation” is showing
and the wave form file is selected, then select the “Processes” tab in the Processes window
(usually the bottom left window). Expand the “Xilinx ISE Simulator” item, right click on the
“Simulate Behavioral Model” and select Run (or double click on “Simulate Behavioral Model).

The ModelSim window will now be displayed. This is a black screen with green lines, if the
simulation was successful.

By looking at the waveform we can compare the output X to what was expected and confirm
whether the circuit that was designed works properly. In this case the waveform shows that the
circuit was constructed correctly.

Using a behavioral simulation becomes more important as circuits become more complicated.
Using the simulation allows problems to be found earlier in the design process.

The behavioral simulation also lets you look at different wires (nets) within the schematic, by
connecting an output marker to them, to verify the internal operation of a circuit. This may be a
simpler way to check large circuits than by hooking up signals to the LEDs on the Sparta-3E
board to check/debug the circuit. Doing this, allows large numbers of signals to be viewed at
one time.
Note that any ports that are added to the schematic after the simulation is created will need to be
added to the simulation window. This can be done by saving the new schematic and then double
clicking on the waveform file in the sources window.

Here is an example of showing internal signals in a behavioral simulation.

Here is the changed schematic to show the interconnecting wires:

Here is the resulting wave form:

Binary values for active marker

You may add more than one marker to the display, zoom in and out, group signals together and
give the group a name, and add a divider between signals to make them easier to see. (Right
click various places in the display to access these capabilities. Another useful feature is the
binary value of the waveform that is given for the active marker.