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Lead-Fage
P a c k ns
GAL22V10
Optio le! High Performance E2CMOS PLD
b
Availa Generic Array Logic™
AND-ARRAY
— 45mA Typical Icc on Quarter Power Device
(132X44)
16
• E2 CELL TECHNOLOGY I OLMC I/O/Q
— Reconfigurable Logic
— Reprogrammable Cells I
16
OLMC I/O/Q
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention I 14
OLMC I/O/Q
• TEN OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs I 12
OLMC
• PRELOAD AND POWER-ON RESET OF REGISTERS I/O/Q
I/O/Q
I/O/Q
Description
Vcc
NC
DIP
I
I
4 2 28 26
The GAL22V10, at 4ns maximum propagation delay time, combines I 5 25 I/O/Q
I/CLK 1 24 Vcc
a high performance CMOS process with Electrically Erasable (E2) I I/O/Q
I/O/Q
floating gate technology to provide the highest performance avail- I 7 23 I/O/Q I
NC
GAL22V10
able of any 22V10 device on the market. CMOS circuitry allows Top View
NC I I/O/Q
I 9 21 I/O/Q
the GAL22V10 to consume much less power when compared to I GAL I/O/Q
I
bipolar 22V10 devices. E2 technology offers high speed (<100ms) I/O/Q
I I/O/Q
erase times, providing the ability to reprogram or reconfigure the I 11
12 14 16 18
19 I/O/Q 22V10
device quickly and efficiently. I 6 I/O/Q
I
I
NC
GND
I/O/Q
I/O/Q
I 18 I/O/Q
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by SOIC I I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I I/O/Q
patible with standard bipolar and CMOS 22V10 devices.
I
I I/O/Q
18
24
13
Unique test circuitry and reprogrammable cells allow complete AC, I I/O/Q
GAL22V10
DC, and functional testing during manufacture. As a result, Lat- Top View GND 12 13 I
tice Semiconductor delivers 100% field programmability and func-
12
6
1
GND
I
I
I
I
I
I
I
I
I
I
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. December 2006
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
22v10_12 1
Specifications GAL22V10
GAL22V10 Ordering Information
Conventional Packaging
Commercial Grade Specifications
Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) Ordering # Package
4 2.5 3.5 140 GAL22V10D-4LJ 28-Lead PLCC
5 3 4 140 GAL22V10D-5LJ 28-Lead PLCC
7.5 4. 5 4.5 140 GAL22V10D-7LP 24-Pin Plastic DIP
4.5 4.5 140 GAL22V10D-7LJ 28-Lead PLCC
1. Discontinued per PCN #06-07. Contact Rochester Electronics for available inventory.
2
Specifications GAL22V10
Lead-Free Packaging
Commercial Grade Specifications
Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) Ordering # Package
4 2.5 3.5 14 0 GAL22V10D-4LJN Lead-Free 28-Lead PLCC
5 3 4 140 GAL22V10D-5LJN Lead-Free 28-Lead PLCC
7.5 4.5 4. 5 14 0 GAL22V10D-7LPN Lead-Free 24-Pin Plastic DIP
4.5 4.5 14 0 GAL22V10D-7LJN Lead-Free 28-Lead PLCC
10 7 7 55 GAL22V10D-10QPN Lead-Free 24-Pin Plastic DIP
55 GAL22V10D-10QJN Lead-Free 28-Lead PLCC
XXXXXXXX _ XX X XX X
3
Specifications GAL22V10
Output Logic Macrocell (OLMC)
The GAL22V10 has a variable number of product terms per OLMC. The GAL22V10 has a product term for Asynchronous Reset (AR)
Of the ten available OLMCs, two OLMCs have access to eight and a product term for Synchronous Preset (SP). These two prod-
product terms (pins 14 and 23, DIP pinout), two have ten product uct terms are common to all registered OLMCs. The Asynchronous
terms (pins 15 and 22), two have twelve product terms (pins 16 and Reset sets all registers to zero any time this dedicated product term
21), two have fourteen product terms (pins 17 and 20), and two is asserted. The Synchronous Preset sets all registers to a logic
OLMCs have sixteen product terms (pins 18 and 19). In addition one on the rising edge of the next clock pulse after this product term
to the product terms available for logic, each OLMC has an addi- is asserted.
tional product-term dedicated to output enable control.
NOTE: The AR and SP product terms will force the Q output of the
D
4 TO 1
Q
MUX
CLK Q
SP
2 TO 1
MUX
4
Specifications GAL22V10
Registered Mode
AR AR
CLK Q CLK Q
S0 = 0 S0 = 1
S1 = 0 S1 = 0
Combinatorial Mode
S0 = 0 S0 = 1
S1 = 1 S1 = 1
5
Specifications GAL22V10
GAL22V10 Logic Diagram / JEDEC Fuse Map
DIP (PLCC) Package Pinouts
1 (2)
0 4 8 12 16 20 24 28 32 36 40
0000
ASYNCHRONOUS RESET
(TO ALL REGISTERS)
0044
. 8
. OLMC
. S0 23 (27)
0396 5808
S1
5809
0440
5 (6)
2904
.
.
. 16 18 (21)
.
.
OLMC
. S0
. 5818
3608 S1
5819
6 (7)
3652
.
.
. 14 OLMC 17 (20)
.
. S0
. 5820
4268 S1
5821
7 (9)
4312
.
. 12
. OLMC 16 (19)
. S0
. 5822
4840 S1
5823
8 (10)
4884
.
. 10 OLMC
. S0 15 (18)
. 5824
5324 S1
5825
9 (11)
5368
. 8
. OLMC
. S0 14 (17)
5720 5826
S1
10 (12) 5827
5764 SYNCHRONOUS PRESET
(TO ALL REGISTERS)
11 (13) 13 (16)
6
Specifications
SpecificationsGAL22V10D
GAL22V10
Absolute Maximum Ratings1 Recommended Operating Conditions
Supply voltage VCC ....................................... -0.5 to +7V Commercial Devices:
Ambient Temperature (TA) ............................. 0 to +75°C
Input voltage applied ........................... -2.5 to VCC +1.0V
Supply voltage (VCC)
Off-state output voltage applied........... -2.5 to VCC +1.0V
with Respect to Ground ..................... +4.75 to +5.25V
Storage Temperature .................................. -65 to 150°C
Ambient Temperature with
Industrial Devices:
Power Applied ......................................... -55 to 125°C
Ambient Temperature (TA) ............................ -40 to 85°C
1. Stresses above those listed under the “Absolute Maximum
IIL1 Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — –100 μA
VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.4 V
VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V
IOS2 Output Short Circuit Current VCC = 5V VOUT = 0.5V TA = 25°C –30 — –130 mA
COMMERCIAL
ICC Operating Power VIL = 0.5V VIH = 3.0V L-4/-5/-7 — 90 140 mA
Supply Current ftoggle = 15MHz Outputs Open L-10 — 90 130 mA
L-15/-25 — 75 90 mA
Q-10/-15/-25 — 45 55 mA
INDUSTRIAL
ICC Operating Power VIL = 0.5V VIH = 3.0V L-7/-10 — 90 160 mA
Supply Current ftoggle = 15MHz Outputs Open L-15/-20/-25 — 75 130 mA
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25 °C
7
Specifications
SpecificationsGAL22V10D
GAL22V10
AC Switching Characteristics
Over Recommended Operating Conditions
TEST -4 -5 -7
PARAM DESCRIPTION UNITS
COND.1
MIN. MAX. MIN. MAX. MIN. MAX.
tpd A Input or I/O to Combinatorial Output 1 4 1 5 1 7.5 ns
8
Specifications
SpecificationsGAL22V10D
GAL22V10
AC Switching Characteristics
Over Recommended Operating Conditions
9
Specifications GAL22V10
Switching Waveforms
INPUT or
INPUT or VALID INPUT
VALID INPUT I/O FEEDBACK
I/O FEEDBACK
tsu th
t pd
CLK
COMBINATORIAL
OUTPUT tco
INPUT or
I/O FEEDBACK
t dis t en
OUTPUT
CLK
1/ f max (internal fdbk)
Input or I/O to Output Enable/Disable t cf tsu
REGISTERED
FEEDBACK
CLK
1 / fm a x
(w/o fdbk)
Clock Width
INPUT or
INPUT or
I/O FEEDB ACK
I/O FEEDBACK
DRIVI NG AR
DRIVING SP tarw
tsu th t spr
CLK
CLK
tco tarr
R E G I S T ER E D
REGISTERED
OUTPUT
OUTPUT
tar
10
Specifications GAL22V10
fmax Descriptions
CL K
CLK
LOGIC
LOGIC
R EG I S T E R ARRAY
ARR AY
REGISTER
11
Specifications GAL22V10
Switching Test Conditions
Input Pulse Levels GND to 3.0V GAL22V10D-4 Output Load Conditions (see figure below)
+1.45V
+5V
R1
C L*
R2
12
Specifications GAL22V10
Electronic Signature Output Register Preload
An electronic signature (ES) is provided in every GAL22V10 When testing state machine designs, all possible states and state
device. It contains 64 bits of reprogrammable memory that can transitions must be verified in the design, not just those required
contain user-defined data. Some uses include user ID codes, in the normal machine operations. This is because certain events
revision numbers, or inventory control. The signature data is may occur during system operation that throw the logic into an
always available to the user independent of the state of the se- illegal state (power-up, line voltage glitches, brown-outs, etc.). To
curity cell. test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired
The electronic signature is an additional feature not present in (i.e., illegal) state into the registers. Then the machine can be
other manufacturers' 22V10 devices. To use the extra feature of sequenced and the outputs tested for correct next state condi-
Security Cell The input and I/O pins also have built-in active pull-ups. As a re-
sult, floating inputs will float to a TTL high (logic 1). However,
A security cell is provided in every GAL22V10 device to prevent Lattice Semiconductor recommends that all unused inputs and
unauthorized copying of the array patterns. Once programmed, tri-stated I/O pins be connected to an adjacent active input, Vcc,
this cell prevents further read access to the functional bits in the or ground. Doing so will tend to improve noise immunity and
device. This cell can only be erased by re-programming the reduce Icc for the device. (See equivalent input and I/O schemat-
device, so the original configuration can never be examined once ics on the following page.)
this cell is programmed. The Electronic Signature is always avail-
able to the user, regardless of the state of this control cell. Typical Input Current
Latch-Up Protection
I n p u t C u r r e n t (u A )
In p u t V o lt ag e ( V o lt s)
Device Programming
GAL devices are programmed using a Lattice Semiconductor-
approved Logic Programmer, available from a number of manu-
facturers (see the the GAL Development Tools section). Com-
plete programming of the device takes only a few seconds. Eras-
ing of the device is transparent to the user, and is done automati-
cally as part of the programming cycle.
13
Specifications GAL22V10
Power-Up Reset
Vcc (min.)
Vcc
t su
CLK t wl
t pr
Circuitry within the GAL22V10 provides a reset signal to all reg- chronous nature of system power-up, some conditions must be
isters during power-up. All internal registers will have their Q out- met to guarantee a valid power-up reset of the GAL22V10. First,
puts set low after a specified time (tpr, 1μs MAX). As a result, the the Vcc rise must be monotonic. Second, the clock input must
state on the registered output pins (if they are enabled) will be be at static TTL level as shown in the diagram during power up.
either high or low on power-up, depending on the programmed The registers will reset within a maximum of tpr time. As in nor-
polarity of the output pins. This feature can greatly simplify state mal system operation, avoid clocking the device until all input and
machine design by providing a known state on power-up. The feedback path setup times have been met. The clock must also
timing diagram for power-up is shown below. Because of the asyn- meet the minimum pulse width requirements.
PIN PIN
Feedback
Vcc
(Vref Typical = 3.2V) Active Pull-up Active Pull-up
Circuit Circuit
(Vref Typical = 3.2V)
Vcc
Vcc Vref Vcc Tri-State Vref
ESD Control
Protection
Circuit
PIN Data
PIN
Output
ESD
Protection
Circuit
Feedback
(To Input Buffer)
14
Specifications GAL22V10
GAL22V10D-4/-5/-7/-10L (PLCC): Typical AC and DC Characteristic Diagrams
Normalized Tpd vs Vcc Normalized Tco vs Vcc Normalized Tsu vs Vcc
1.1 1.1 1.1
RISE
RISE
FALL
Normalized Tpd
Normalized Tco
Normalized Tsu
RISE FALL
FALL
1 1 1
FALL
Normalized T
FALL FALL
1.1
1.1 1.1
1 1
1
0.9
0.9
0.9 0.8
0.8 -55 -25 0 25 50 75 100 125 -55 -25 0 25 50 75 100 125
-55 -25 0 25 50 75 100 125
-0.1
Delta Tpd (ns)
-0.1
-0.2
-0.3 -0.4
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10
Number of Outputs Switching Number of Outputs Switching
RISE RISE
Delta Tpd (ns)
8 8
Delta Tco (ns)
FALL FALL
4 4
0 0
-4 -4
0 50 100 150 200 250 300 0 50 100 150 200 250 300
15
Specifications GAL22V10
GAL22V10D-4/-5/-7/-10L (PLCC): Typical AC and DC Characteristic Diagrams
Vol vs Iol Voh vs Ioh Voh vs Ioh
0.6 4 3.95
3.85
3 3.75
0.4
3.65
Voh (V)
Voh (V)
Vol (V)
2 3.55
3.45
0.2
1 3.35
0 0 3.15
0 5 10 15 20 25 30 35 40 0 5 10 1 5 2 0 2 5 3 0 3 5 4 0 4 5 50 55 60 0.00 1.00 2.00 3.00 4.00 5.00
1.2
1.15
1.1
Normalized Icc
Normalized Icc
Normalized Icc
1.1
1.1
1 1
1.05
0.9
0.9
1
0.8
5 20
Delta Icc (mA)
4
40
Iik (mA)
3
60
2
80
1
100
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
-3 -2.5 -2 -1.5 -1 -0.5 1
16
Specifications GAL22V10
GAL22V10D-7/10L (PDIP): Typical AC and DC Characteristic Diagrams
Normalized Tpd vs Vcc Normalized Tco vs Vcc Normalized Tsu vs Vcc
1.1 1.2
1.1
RISE RISE
1.1
Normalized Tsu
FALL
Normalized Tco
1.05 RISE FALL
Normalized Tpd
FALL 1.05
1
1
1
0.9
0.95 0.8
0.9
4.5 4.75 5 5.25 5.5 4.5 4.75 5 5.25 5.5
4.5 4.75 5 5.25 5.5
Normalized Tco
FALL
Normalized Tsu
FALL FALL
1.1 1.1
1
1 1
0.9
0.9 0.9
-0.4 -0.4
-0.5 -0.5
-0.6 -0.6
-0.7 -0.7
RISE RISE
-0.8 -0.8
FALL FALL
-0.9 -0.9
-1 -1
-1.1 -1.1
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10
Number of Outputs Switching Number of Outputs Switching
RISE RISE
8 8
FALL
Delta Tpd (ns)
FALL
4 4
0 0
-4 -4
0 50 100 150 200 250 300 0 50 100 150 200 250 300
17
Specifications GAL22V10
GAL22V10D-7/10L (PDIP): Typical AC and DC Characteristic Diagrams
Vol vs Iol Voh vs Ioh Voh vs Ioh
0.5 4 3.8
3.7
0.4 3.6
3
3.5
Voh (V)
0.3 3.4
Voh (V)
Vol (V)
2 3.3
0.2 3.2
1.1 1.2
1.15
Normalized Icc
Normalized Icc
Normalized Icc
1.05 1.1
1.1
1 1
1.05
0.95 0.9
0.9 1
0.8
7 30
6 40
Iik (mA)
5 50
4 60
3 70
2 80
1 90
0 100
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -2.5 -2 -1.5 -1 -0.5 0
Vin (V) Vik (V)
18
Specifications GAL22V10
GAL22V10D-10Q and Slower (L & Q): Typical AC and DC Characteristic Diagrams
Normalized Tpd vs Vcc Normalized Tco vs Vcc Normalized Tsu vs Vcc
1.1 1.15 1.2
1.05 RISE
Normalized Tco
Normalized Tsu
FALL 1.1
FALL
FALL
1.05
1 1
1
0.95 0.9
0.9
0.9 0.8
4.5 4.75 5 5.25 5.5
4.5 4.75 5 5.25 5.5 4.5 4.75 5 5.25 5.5
Supply Voltage (V) Supply Voltage (V) Supply Voltage (V)
FALL FALL
Normalized Tco
FALL
Normalized Tsu
1.25
1.1
1.1
1.15
1
1 1.05
0.9 0.95
0.9
0.85
0.8
-55 -25 0 25 50 75 100 125 0.8 0.75
-55 -25 0 25 50 75 100 1 25 -55 -25 0 25 50 75 100 1 25
Temperature (deg. C)
Temperature (deg. C) Temperature (deg. C)
-0.4 -0.4
RISE
RISE
FALL
FALL
-0.8 -0.8
-1.2 -1.2
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10
Number of Outputs Switching Number of Outputs Switching
16 16
RISE RISE
Delta Tpd (ns)
12 FALL FALL
12
8
8
4
4
0
-4 0
-8 -4
0 50 100 150 200 250 3 00 0 50 100 150 200 250 3 00
19
Specifications GAL22V10
GAL22V10D-10Q and Slower (L & Q): Typical AC and DC Characteristic Diagrams
Vol vs Iol Voh vs Ioh Voh vs Ioh
0.6 4.5 4.5
3.5 4
0.4 3
Voh (V)
Voh (V)
Vol (V)
2.5
3.5
2
0.2 1.5
3
0 0 2.5
0 5 10 15 20 25 30 35 40 0 20 40 60 0.00 1.00 2.00 3.00 4.00 5.00
1.25 1.3
Normalized Icc
Normalized Icc
Normalized Icc
1.1
1.15
1.2
1 1.05
1.1
0.95
0.9
1
0.85
10
6
20
Delta Icc (mA)
5
30
Iik (mA)
4 40
3 50
60
2
70
1 80
0 90
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -2.5 -2 -1.5 -1 -0.5 0
20
Specifications GAL22V10
Notes
Revision History
21