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Abstract— Reversible logic has emerged as one of the most important approaches for
power optimization, which finds applications in low power CMOS design, quantum compu‐
ting, optical information processing, DNA computing, bioinformatics and nanotechnology.
Multipliers are very essential for the construction of various computational units of a quantum
computer. Quantum cost of a reversible multiplier circuit can be minimized by reducing the
number of reversible logic gates and garbage outputs. This paper proposes an improved design
of a 4 X 4 multiplier using reversible logic gates. It is faster and has lower hardware complexity
compared to the existing designs. In addition, the proposed reversible multiplier is better than
the existing counterparts in terms of number of gates, number of garbage outputs, number of
constant inputs and quantum cost.
Index Terms: Reversible logic gates, Quantum cost, Reversible multiplier circuit, Garbage outputs
—————————— ——————————
1 INTRODUCTION
Traditional technologies more and more start to should have minimum number of gates, constant
suffer from the increasing miniaturization and the inputs, produce minimum number of garbage out‐
exponential growth of the number of transistors in puts and has least quantum cost.
integrated circuits. To face the upcoming challenges, In most computing tasks, the number of output
alternatives are needed. Reversible logic provides bits is relatively small when compared to the num‐
such an alternative that may replace or at least en‐ ber of input bits. However, computational tasks in
hance traditional computer chips. digital signal processing, communication, computer
In present day technology, energy loss due to ir‐ graphics and cryptography require that all of the
reversibility is one of the major concerns. According information encoded in the input must be preserved
to the Landauer[18], KT ln(2) joules of energy is dis‐ at the output. This motivates the study of reversible
sipated for the loss of single bit of information, computation and reversible logic circuits. These logic
where K is the Boltzmann’s constant and T is the circuits are composed of gates with equal number of
absolute temperature at which operation is carried input and output bits in accordance with the pig‐
out. Bennett showed that energy dissipation is re‐ eonhole principle for the computation of reversible
duced or even eliminated if computation becomes functions.
information‐lossless [5]. This holds for reversible In this paper, the focus is on the design of 4 x 4
logic. Bennett also proved that circuits with zero reversible multiplier circuit using minimum number
power dissipation are only possible if they are built of gates and garbage bits which in turn reduce the
from reversible gates. To perform a non‐dissipative quantum cost of the proposed design. It has been
transition of the output, the state of the output prior proved that the proposed multiplier is better than
to and during present output transition must be the existing one in literature; in terms of number of
known. That is the copy of the state of the output garbage outputs, number of gates, number of con‐
must be present at all times. The only way through stant inputs and quantum cost.
which it can be obtained is by using reversible logic.
A logic synthesis technique using reversible gate
JOURNAL OF COMPUTING, VOLUME 3, ISSUE 3, MARCH 2011, ISSN 2151-9617
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2 REVERSIBLE LOGIC output vector is O(P, Q). The outputs are
defined by P=A, Q=A xor B. Quantum cost of
An n x n reversible logic gate can be represented a Feynman gate is 1.
as:
IV = (I1, I2, I3… In)
OV = (O1, O2, O3… On)
Where IV and OV are input and output vectors.
A logic gate L is reversible if, for any output y, there
is a unique input x and same inputs (x) are obtained
back when output (y) is applied to the gate L, as illu‐ Fig1 Feynman gate
strated in eq. (1) and (2)
3.2 Toffoli Gate: Fig. 2 shows a 3 x 3 Toffoli gate [20]
L(x) y The input vector is I(A, B, C) and the output
L(y) x vector is O(P, Q, R). The outputs are defined by
P=A, Q=B, R=AB xor C. Quantum cost of a
Toffoli gate is 5.
A. Optimization issues
Garbage: Garbage is the number of outputs
added to make an n‐input, k‐output Boolean
function reversible. A reversible logic gate
should have equal number of inputs and
outputs. Some of the outputs should be con‐
sidered to make the gate reversible and
those undesired outputs are known as gar‐ Fig 2 Toffoli gate
bage outputs. A heavy price is paid for
every garbage output [19].
Gate count: Gate count is the number of re‐ 3.3 NTG: Fig. 3 shows a 3 x 3 NTG [3,10]. The input
versible gates used to realize the function. vector is I (A, B, C) and the output vector is
Flexibility: This refers to the universality of a O (P, Q, R). The output is defined by P = A, Q = A
xor B and R=AB xor C. Quantum cost of a NTG
reversible logic gate in realizing more func‐
gate is 4.
tions.
Critical path: It is the longest path traversed
in the system to get the desired output.
Constant input: The input that is added to a
n x k function to make it reversible is called
constant input.
Quantum cost: Quantum cost denotes the ef‐
fort needed to transform a reversible circuit
to a quantum circuit [19].
Fig 3 NTG
Transistor cost: This denotes the effort
needed, to realize a reversible circuit in
CMOS [19]. 3.4 Peres gate: Fig. 4 shows a Peres Gate [12]. The
input vector is I(A, B, C, D) and the output
vector is O(P, Q, R, S). The outputs are
3 BASIC REVERSIBLE GATES defined by P=A, Q=A xor B, R= A xor B xor C
and S= ((A xor B) C xor AB xor D) The full
adder using peres gate is obtained with C=0 and
3.1 Feynman Gate: Fig.1 shows a 2 x 2 Feynman D = Cin and its quantum cost is calculated to be
gate [17]. The input vector is I(A, B) and the equal to 6 from its quantum realization [1, 12]
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shown in Fig.5. consists of 16 partial product bits of the X and Y in‐
puts as indicated in Fig 8. This can be extended to
any other n x n reversible multiplier. Here each par‐
tial product is generated by using 3 x 3 Toffoli gate
[20]. In addition to the product, the gate also passes
the two inputs A and B directly to the output. In‐
stead of using separate gate to provide fan out, this
gate can be used for the generation of partial product
Fig 4 Peres full adder gate
as well as a fan out circuit with the quantum cost of
only five. Thus both partial products and fan‐out are
produced at the gate cost of 16, garbage output of 8,
16 constant inputs and quantum cost of 80.
Fig 5 PFAG gate as full adder
To implement an n operand addition circuit, a carry
save adder (CSA) [15] is used. The four to two CSA
tree [7] reduces the four operands to two. PFAG is
very useful to realize full adder as its quantum cost Fig 7 Reversible Multiplier
is very low; which is 6. Realization of four to two
CSA using PFAG [1, 12] is shown in Fig. 6. This re‐
quires two PFAG gates with two constant inputs and
four garbage output bits.
Fig 6 Four-to-two reversible CSA using PFAG gates
II: Addition of partial products to generate final product terms
Fig 9 proposed 4 x 4 reversible multiplier
In the implimentation of this reversible multiplier, garbage bits when compared with other designs.
partial products are generated by using sixteen Table 1 indicates the comparison between differ‐
3 x 3 Toffoli gates[20]. The addition is performed ent multiplier designs for partial product genera‐
as indicated in Fig 9. The proposed circuit uses tion in terms of number of gates, garbage outputs,
five reversible full adders constructed by using constant inputs and quantum cost.
PFAG gates[1,12], five half adder gates
constructed by using NTG gates[3,10], one four to Table 1: Partial product generation
two CSA[15] gate which is constructed as shown Partial No of No of No of Quan
in Fig 6 and one reversible xor gate constructed Product gates Constant Garbage tum
by using Feynman gate[17]. genera- N Inputs CI Outputs Cost
tion GO QC