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8255 (PPI) Programmable Peripheral Interface. Any microcontroller or a micropr
ocessor has a limited number of I/O ports, which restricts the number of I/O dev
ices accessed by or interfaced to the IC.
Need ?????? Intel introduced an IC called Programmable Peripheral Interface (PPI
) to check this drawback of ICs.
It is compatible to Intel and other microcontrollers or microprocessors It has
3 I/O ports (24 pins) Features of PPI or 8255 It programmable i.e. can be contro
lled by a program running on 8051 Thus 3 I/O ports can be accessed on the expens
e of two. Pin Diagram
1. PA(0-7): Port A is an I/O port. Its an 8- bit data output latch/buffer and
an 8-bit data input latch. Pin Description RD: Read Control is an Active low inp
ut pin. RD is LOW when CPU (8051) reads data. 3. CS: Chip Select is an Active lo
w input pin. A LOW on this pin selects 8255. 2.
GND: This provides the ground for the IC 4. Pin Description 5. A0,A1: These pin
s along with RD,WR, CS pins control the operation of 8255. User needs to use the
se 5 pins to program 8255.
Accessing these pins is in the following way
PC(0-7): Port C is an 8-bit I/O port. Its
lower 4-bits can be programmed
to work in conjunction with PortB
and the upper 4-bits can be
programmed to work in
conjunction with Port A
separately.
6. Pin Description 7. PB(0-7): Port B is an 8-bit I/O port used for 8-bit output
data latch/buffer or input data buffer.
9. 7. Vcc: +5V power supply. 8. D7-D0: Data bus, bidirectional, tristate lines
connected to system (8051) data lines Pin Description RESET: Reset is an input p
in which sets the PPI to its default state. 10. WR: Write Enable is an active lo
w input pin. 11. NC: Pin numbers 1,12,23,24 on a PLCC package are left unconnect
ed.
Pin Description (Accessing 8255 using A0, A1 ,RD ,WR ,CS pins)
 Data Bus Buffer is a 3-state bidirectional 8-bit buffer used to interface with
system data bus. Functional Description Read/Write and Control Logic controls a
ll of the internal and external transfer of both data and control or status word
s.
Ports A, B, and C are each 8-bit ports which can be configured by software. Thes
e also offer a wide range of characteristics to the system software.
8255 can be operated in three modes Mode 0(Basic Input Output). Operational Des
cription Mode 1(Strobed Input Output). Mode 2(Bi-Directional Bus). Any of the 8-
bits of port C can be set or reset. This feature supports control based software
requirements.
Mode 0: Two 8-bit ports, two 4-bit ports Operational Description Output ports a
re latched, input ports are not Any port can be input or output 16 different inp
ut output configurations are possible
Mode 1 Three ports are available as two groups. Operational Description Each po
rt contains one 8- bit data port and one 4- bit control port. Both the data port
s can either be input or output. Both the input or output are latched. The 4-bit
port can be used as both control or status port.
Mode 2: Used in group A only. Operational Description 8-bit, bidirectional bus
port (port A) and 5-bit control port (port C). Both inputs and outputs are latch
ed. The 5-bit control port (port C) is used for control or status for the 8-bit,
bidirectional bus (port A)
Schematic +5V +5V +5V +5V U6 7404 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A1 Y1 A2 Y
2 A3 Y3
Gnd A4 Y4 A5 Y5 A6 Y6
Vcc U1 8255 34 33 32 31
30
29
28
275
3698 35 6 432140 39 38 37
18 19 20 21 22 23
24 25 14 15 16 17 13 12 11
10 267 D0 D1 D2 D3 D4 D5 D6
D7 RD WR A0 A1 RESET CS PA0 PA1 PA2
PA3 PA4 PA5 PA6 PA7
PB0 PB1 PB2 PB3
PB4 PB5 PB6 PB7
PC0 PC1 PC2 PC3 PC4
PC5 PC6 PC7
VCCGND C3 10 uFd C2 33 pFd C133 pFd R1 10K U2 AT89C51 9 18 19 20 29 30 31 40 123
45678 21 22 23 24
25 26 27 28
10 11 12 13 14 15
16 17 39 38 37 36 35 34 33
32 RST XTAL2 XTAL1 GND PSEN ALE/PROG EA/VPP VCC P1.0 P1.1 P1.2 P1.3 P1.4
P1.5 P1.6 P1.7
P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14
P2.7/A15 P3.0/RXD P3.1/TXD P3.2/INTO P3.3/INT1 P3.4/TO P3.5/T1 P3.6/WR P3.7/RD P
0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4
P0.5/AD5 P0.6/AD6 P0.7/AD7
Y1 11.0592 MHz U3 74LS373/LCC 3478 13 14 17
18 1 11 256912 15 16 19
20 10 D0 D1 D2 D3 D4
D5 D6 D7
OC G Q0 Q1 Q2 Q3 Q4 Q5 Q6
Q7 VCC GND P3.6 P3.7 Inverter Latch PPI Microcontroller
ORG 00h MOV DPTR,#4003h ;Base address of the the Control Word Register of 8255
MOV A,#90h ;PA->input, PB->output, PC->output Assembly Language Program for 8255
Data Transfer MOVX @DPTR,A ;Instructing Control register with Control Word BACK
:MOV DPTR,#4001h ;Base address of Port B MOV A,#055h MOVX @DPTR,A ;PB=0x55
ACALL DELAY ;Delay to check the o/p MOV DPTR,#4002h ;Base Address of Port C MOV
A,#0AAh MOVX @DPTR,A ;PC=0xaa MOV DPTR,#4001h MOV A,#0AAh MOVX @DPTR,A MOV D
,#4002h
MOVX @DPTR,A MOV A,#055h ACALL DELAY ;Toggling the outputs SJMP BACK ;Keep togg
ling the outputs Cont
DELAY: MOV R0,#0 FF h LOOP3:MOV R1,#0 FF h LOOP2:MOV R2,#0 FF h ;to create a de
lay of 128*128*128*8 machine cycles LOOP1: DJNZ R2,LOOP1 DJNZ R1,LOOP2 DJNZ R0,L
OOP3 END ;may not reach here....
8255 (PPI) Programmable Peripheral Interface.
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