UNIT 1

Objective questions

1. What type of language is VHDL?

2. What is the basic building unit of a VHDL design?
3. What do all VHDL designs begin with?
4. Which block describes a design's interface?
5. Which block describes a design's behavior?
6. What is the difference between simulation and synthesis?
7. VHDL is a ____________ typed language.
8. Which data type defines a single logic signal?
9. Which data type describes a bus?
10. What two ways can a vector's range be described?
11. What are the IEEE STD_LOGIC_1164 data types for single logic signals and
buses?
12. Why is it desirable to use IEEE STD_LOGIC_1164 data typing?
13. What are the only two values for a Boolean type?
14. What are the numerical data types?
15. What is SUBTYPING used for?
16. What is the purpose of a SIGNAL declaration?

Subjective questions

Draw state transition diagram for SR latch

Draw state transition diagram for JK ff
1. Write a VHDL code for JK FF
2. Write a VHDL code for barrel shifter
3. Write a VHDL code for 24-bit up/down counter
4. Write a VHDL code for Moore type FSM that produce an output of 1 if input
sequences it detects either 110 or 001 patterns. Overlapping sequence should be
detected
5. Write a VHDL code for FSM described in above problem
6. Write a VHDL code for 4 bit up counter
7. Write a VHDL code for gated D latch
8. Write a VHDL code for D FF with synchronous reset
9. Write a VHDL code for D FF with asynchronous reset
10. Write a VHDL code for n bit register with asynchronous clear
11. Write a VHDL code for four-bit register
12. Write a VHDL code for four-bit shift register
13. Write a VHDL code for 4 to 1 multiplexer
14. Write a VHDL code for 4 to 16 decoder
 UNIT 2.

Objective questions

1. What type is use to create a user data type?

2. What reserved word is used to declare a user data type?
3. Create the use data type DAYS and assign it the values: MON, TUE, WED, THU,
FRI, SAT and SUN.
4. Which data type is used for a string of ASCII characters? Which data type
includes time units as values?
5. Create the entity block for a three input XOR gate.
6. Which symbol is used to end all VHDL statements?
7. What part of a port declaration defines a signal in or out direction?
8. Which VHDL construct is used to define a literal constant in an entity block?
9. Create the integer constant included in an entity block, called BUS_SIZE and
assign it a value of 32.
10. Which symbols are used as an assignment operator to assign a literal to an
identifier name?
11. What are the two primary ways to describe a logic circuits function within an
architecture block?
12. Create the architecture block for the 3-input XOR gate
13. Which symbols are used to assign an expression's result to an output interface
signal?
14. What are the rules used to define an identifier name?
15. What symbols define a comment line?
16. Write the statements that will allow a design to access all the contents of the IEEE
ARITH library.

Subjective questions

1. Write a VHDL code for 4 to 2 binary encoder

2. Write a VHDL code for BCD to 7 –segment display code converter
3. Write a VHDL code for 4-bit comparator circuit
4. Write a VHDL code for 2 to 1 multiplexer
5. Write a VHDL code for 2 to 4 binary decoder
6. Write a VHDL code for 16 to 1 MUX
7. Write a VHDL code for priority encoder
8. Write a VHDL code for 4 to 16 binary decoder
9. Write a VHDL code for 4 to 1 multiplexer using generate statement
10. Write a VHDL code for D FF
11. What is case statement? Illustrate with examples
12. What is inertial delay?
13. What is time delay?
14. Explain delta delay with examples
15. Explain generate statement
16. What is package body?
17. Write a package declaration called OPERATOR to hold the following items:
a. type op_code ( ADD, SUB, MULT, NULL);
b. constant word_count : integer := 0;
c. constant op_start : op_code := null;
 UNIT 3

Objective questions

1. Add a 25 ns inertial delay to the XOR assignment statement

2. Make the delay in question 33 transport rather than inertial.
3. How does a transport delay differ from an inertial delay?
4. Where are SIGNAL declarations placed in the design?
5. Write an assignment statement that assigns the contents of s (5) to t (2).
6. Write an assignment statement that copies all the states of data_bus to data_in.
They are both 8-bit buses.
7. Statements in an architecture block are executed ________________.
8. Statements in a process block are executed ______________.
9. What is the purpose of a process' sensitivity list?
10. Under what conditions is a process run?
11. What is an EVENT?
12. What is the difference between event and non-event driven process execution?
13. Write a process block that keeps a running tally of each time an interrupt (INT)
signal is asserted high.
14. Which symbols are used to differentiate between logic 1 and an integer 1?
15. Which symbols are used to differentiate between logic 1011 and an integer 1,011?
16. What are the results of using CLK'event as a condition in the if statement of the
DEF example?

Subjective questions

1. What is package declaration?

2. What are the signal drivers in VHDL?
3. What is mean by LFSR?
4. Write a VHDL code for full adder using gates
5. Write a VHDL loop statement
6. Discuss design flow for VHDL
7. What is FPGA?
8. List design units in VHDL
9. Explain the exit statement in VHDL along with example
10. Implement a 16:1Mux by using 4:1 Mux & write VHDL code
11. Write a short note on data types in VHDL
12. What are signals?
13. Write a VHDL code for serial adder
14. What is the difference between dynamic & static hazards?
15. Explain critical races with examples
16. A design for my_mux has three architecture blocks: mux2bit, mux8bit, and
mux16bit. The my_mux design is part of the my_ics library. Write the library
and use statements to use the 8-bit mux architecture in a component declaration of
my_mux.
 UNIT 4

Objective questions

1. In an if..then..else construct, which statements are executed if the condition is

TRUE and which if it is FALSE?
2. What reserved word is used to nest if..then..else statements?
3. Write the process block that separately tallies positive and negative transitions of
the signal TIME_OUT.
4. What is the purpose of a for loop?
5. What are the requirements for a for loop?
6. Write a process block that uses a for loop to set a zero flag high if all the bits in a
sixteen (16) bit word are low (zero).
7. What is the basic building element of a structure design?
8. Write the component declaration for the XOR gate in question 21.
9. Instantiate two copies of the XOR gate in question 57. Gate X1 has inputs Ain
and Bin and output I1. Gate X2 has inputs Cin and I1 and output XOR3.
10. Write the declaration for interconnecting signal I1 in question 58.
11. Instantiate XOR gate X1 in question 58 using direct association.
12. Write is the general rule for component declarations?
13. What is meant by instantiating a component?
14. How do signal declarations differ from port interface declarations?
15. What is the prime use of signals?
16. What is a module?

Subjective questions

1. Write a short note on concurrency

2. Compare ROM, PAL & PLA.
3. Write a short note on 4*4 keyboard scanner
4. What is the role of synchronizers in digital logic design?
5. What are the attributes in VHDL? Implement MOORE machine sequence to
detect “1011”
6. What do you mean by subprogram?
7. What is operator overloading?
8. Write a VHDL code to convert BYTE to INTEGER using FUNCTION
9. Write a VHDL code for INTEGER to BYTE conversion using procedure
10. Implement BCD counter by using EPROM & D-FF
11. Explain IOB of MAX 7000 CPLD
12. Draw state transition diagram for master slave JK FF
Write a program for BCD to 7 SEG decoder using case statement
13. Define clock skew & race condition
14. Comment on variable assignment statement & signal assignment statement
15. The following PROCESS is part of a VHDL description. Assume that you have
registers and combinational logic blocks like multiplexers, decoders and others
available. Q has been defined to be a four-bit vector. Sketch the hardware implied
by this description defining any logic blocks that you use.

PROCESS (ck, clr)

BEGIN
IF clr = '0' THEN
Q <= “0000”;
ELSIF (ck'EVENT AND ck = '1') THEN
IF EN = '1' THEN
Q <= Q + 1;
ELSE
Q <= Q;
END IF;
END IF;
END PROCESS;
 UNIT 5

Objective questions

1. Where do modules get their functions and interface signals?

2. How many parameters can be passed into a function?
3. How many results can be returned from a function?
4. Write a function that returns the sum of two 8-bit words.
5. How are functions called?
6. Write a function call for the function in question 69 that adds FIRST to SECOND
7. How do procedures differ from functions?
8. Write a procedure that produces the sum, difference, and product of two integers,
WORD1 and WORD2
9. Write the statement that calls the procedure in question 73 using A_WORD and
B_WORD as inputs and TOTAL, DIFF, and TIMES as outputs.
10. Which standard library does not require a library or use statement?
11. Write the statements to access all the contents of the my_gates section of the
my_design library.
12. What is a PACKAGE?
13. When is a PACKAGE BODY used?
14. What is the name of the library used by the current design to store compiled
results?
15. Which standard library is used to access the keyboard and monitor screen?
16. Write the statement to access all of the contents of the package in question 81
from the current design library.
17. Which is the default architecture block in a multiple architecture design?

Subjective questions

1. Explain CLB of XC 9500

2. Write a short note on gate arrays
3. Write a short note on generic PAL device
4. Explain the advantages of place & route process
5. Write a VHDL code for T FF
6. Write a VHDL code for ring counters
7. Define clock skew & race condition
8. Write a program for 1 bit full adder using mix modeling
9. Write a program for 2*4 decoder using behavioral modeling
10. Define metastability
11. What is clock skew?
12. What is race round condition?
13. Write a short note on MOORE finite state machine
14. Write a short note on MEALY finite state machine
15. Draw MEALY type FSM for serial adder
16. Draw MOORE type FSM for serial adder
17. What is CPLD? Explain with diagram
 UNIT 6

Objective questions

1. What is the difference between PAL & PAL

2. State the applications of FPGA
3. What is Setup time?
4. Moore machine with 5 inputs, 6 state flip-flops and 12 outputs. The maximum
number of transition arrows that can leave a state is---------
5. TRUE or FALSE: A Moore machine normally has fewer states than an equivalent
Mealy machine.
6. TRUE or FALSE: The problem with a standard Mealy machine is that its TF
output changes are not synchronized to the changes in the clock.
7. Assuming that the input values are stable, how soon after a clock edge will the
output OUT become valid
8. Consider a medium performance processor implemented with a single-phase
clock. Which of the binary storage elements is best for implementing the data
registers?
9. Who is Xilinx?
10. How many macrocells are there in XC9500
11. What is the special feature of XC4000
12. What are the essential steps for synthesis?
13. Which type of finite state machine, Moore or Mealy, is simple?
14. There are several reasons for adding assert statements to your VHDL code. Name the
most important reason.
15. State the applications of CPLD
16. TRUE or FALSE: signal is not a VHDL data object.

Subjective questions

1. Implement serial adder by using FSM

2. Write a brief introduction to CPLD Xilinx
3. Discuss CPLD Altera
4. Give the advantages of VHDL over others
5. Give the hierarchy of VHDLs
6. Explain CLB of XC 4000
7. Write a short note on PLDs
8. Draw and explain Io block of XC 9500
9. Draw and explain Io block of XC 4000
10. Draw and explain Io block of XC 7000
11. Write down simulation steps of VHDL code
12. Write down code for accumulator circuit
13. Discuss place & route process
14. Write a short note on ROM
15. What is PLA?
16. Write a short note on PAL
17. Sketch an ASM chart for the mechanical arm’s controller.