2nd US-Korea NanoForum, LA

Fabrication and Characterization

of bulk FinFETs for Future Nano-
Scale CMOS Technology

Jong-Ho Lee
Jongho@ee.knu.ac.kr
School of EECS and National Education Center for Semiconductor Technology
Kyungpook National University, Daegu, 702-701 Korea

2nd US-Korea NanoForum, LA Jong-Ho Lee

Contents
Introduction
Simulation Study

Fabrication of Bulk FinFETs

by Spacer Technology
by Selective Si3N4 Recess

Device and SRAM Cell Characteristics

Summary

2nd US-Korea NanoForum, LA Jong-Ho Lee

 Introduction: Technology Roadmap Beyond Bulk LDD CMOS

TG
TG G
S/D S/D
Double/Triple-Gate BG
BG S/D S/D
S/D
Performance

Double-Gate CMOS Fin Double/Triple-Gate FET

Si G
G
SOI/SiGe S/D SiGe S/D
SOI PD/FD CMOS SiGe CMOS (high mobility)

Halo G
Bulk
Bulk LDD CMOS (Halo)

2004 2006 2008 2010 Time

2nd US-Korea NanoForum, LA Jong-Ho Lee

 Introduction

‹ Driving Force of CMOS Scaling-down:

Æ High Performance and High Integration Density

‹ A Promising Device Structure

Æ Double/Triple-Gate MOSFETs (or FinFETs)

‹ Why Double/Triple-Gate Transistor?

G
Æ Robustness against SCE
Æ Higher Current Drivability S D

Æ Good Subthreshold Swing Si film G

2nd US-Korea NanoForum, LA Jong-Ho Lee

 Introduction: Types of Double-Gate Transistors
Z Current- Carrying

Current- Carrying
Plane Z
Y

Plane
Y
X Top Gate D
Left Gate
X
current
S D direction Right Gate
Bottom Gate S
Silicon Wafer Silicon Wafer
(a) Type I (b) Type II

S current
direction
Right Gate
D
Z
Current- Left Y
Carrying Gate Process technology of FinFET is
Plane easy and compatible with
X
conventional fabrication process
Silicon Wafer
(c) Type III
∗ H. P. Wong et al., IBM, vol. 87, no. 4, p.537, 1999, Proceedings of the IEEE
2nd US-Korea NanoForum, LA Jong-Ho Lee
 Types of Double/Triple-Gate Transistors

Type
Type I Type II
Type III
(Planar DG (Vertical DG (Triple-Gate
Key (FinFETs)
FETs) FETs) MOSFETs)
Geometry

Gate Left/Right (or

Top/Bottom Left/Right Left/Right/Top
Position Cylinder)

Body
Horizontal Vertical Vertical Vertical
Shape
Current
Horizontal
Carrying Side Surfaces Side Surfaces Side Surfaces
Surfaces
Plane
Current
Flow Horizontal Vertical Horizontal Horizontal
Direction

2nd US-Korea NanoForum, LA Jong-Ho Lee

Double-Gate Transistor (SOI FinFET)
‹ FinFET
à simple, self-aligned double-gates
à good process compatibility
Ä thickness control of fin body
Ä RIE damage on the channel, high S/D resistance

∗ D. Hisamoto et al., UC Berkeley, p.1032, IEDM 1998

2nd US-Korea NanoForum, LA Jong-Ho Lee

Body-Tied Double/Triple-Gate MOSFET Using
Bulk Wafer (Bulk FinFET)

‹ Low wafer cost

S/D a te ‹ Low defect density
G 0

‹ Less back-bias effect

S/D HFin
xj ‹ High heat transfer rate
to substrate
Body

WFin
Ox ‹ Good process compatibility
Si ide
Su TFOX
bs
t ra
t e World 1st Cost-Effective
Double/Triple-Gate MOSFETs
Schematic 3-D View
∗ J.-H. Lee., Korea/Japan/USA patent

2nd US-Korea NanoForum, LA Jong-Ho Lee

Cross-Sectional Views (Body Structure) for 3-
Dimensional Device Simulation

Gate Fin body Gate Fin body

SiO2 SiO2

Si sub Si sub

SOI FinFET Bulk FinFET

2nd US-Korea NanoForum, LA Jong-Ho Lee

3-D Simulation Results
0.5 180 100
LG=25 nm LG=25 nm

Subthreshold Swing (mV/dec)

150 95
TOX=1.5 nm TOX=1.5 nm
0.4
VDS=0.9 V
120 90

DIBL (mV/0.9V)
Bulk
VT (V)

0.3 SOI 90 85
VDS=0.05 V Bulk
SOI
19 -3
60 80
0.2 Na=1x10 cm
HFin=70 nm 30 75 HFin=70 nm
xj,S/D=66 nm 19
Na=1x10 cm
-3
xj,S/D=66 nm
0.1 0 70
10 20 30 40 50 10 20 30 40 50
Fin Width (nm) Fin Width (nm)
VT and DIBL versus Fin Width Subthreshold Swing versus Fin Width
qN sub t b
V T = Φ MS + 2φ B + for fully depleted body
2 C ox
∗ J.-H. Lee et al., KNU, p. 102, Si Nanoelectronics Workshop 2003

2nd US-Korea NanoForum, LA Jong-Ho Lee

3-D Simulation Results

475
substrate electrode
LG=30 nm @ temperature=300 K
450

Device Temperature (K)

S/D ate 425 TOX=1.5 nm
G 0 SOI
400 VDS=0.9 V
HFin
S/D xj 375
Body

∆T~130 °C
WFin
350
Ox
Si ide 325 Bulk
TFOX
Su
bs 300
tra
te Heat 0.0 0.2 0.4 0.6 0.8 1.0
Gate Voltage (V)

3-D Schematic View of Heat Device Temperature versus Gate

Transfer from Body to Substrate Voltage

∗ J.-H. Lee et al., KNU, p. 102, Si Nanoelectronics Workshop 2003

2nd US-Korea NanoForum, LA Jong-Ho Lee

Fabrication Steps by Using Spacer Technology
SiN 80 nm
SiO2 30 nm
SiN 25 nm
SiO2 30 nm

Si

4 Stack Layer Growth and Deposition SiN Removal Using Phosphoric Acid

Poly-Si Spacer
30 nm
Poly-Si Spacer

Si
Photo Lithography, SiN Etching,
Poly-Si Depo., and Dry Etching

2nd US-Korea NanoForum, LA Jong-Ho Lee

Fabrication Steps

SiO2, SiN, and SiO2 Dry Etching Fin Dry Etching

Top Si Width 25 nm
Bottom Si Width 100 nm
Si Fin Height 230 nm
Fin body

2nd US-Korea NanoForum, LA Jong-Ho Lee

Fabrication Steps

SiO2

Wet Etch-back
Thin Ox., Filling, and Densification
Field Oxide Thickness 80 nm

SiO2

Chemical Mechanical Polishing (CMP)

2nd US-Korea NanoForum, LA Jong-Ho Lee / 27

First Body-Tied Triple-Gate MOFET (Bulk
FinFET)

As+, 20 keV 3x1015/cm2, 2 Fin

-7 V DS = 0.1 V
10

Drain Current (A)

Gate Poly-Si Etching
25 nm
-8
10
40 nm
50 nm

-9
10 Vbs = 0 V
Poly-Si Vbs = -1 V 40 nm
Vbs = -2 V
-10
10
-0.5 0.0 0.5 1.0 1.5
Gate Voltage (V)
ID-VGS Characteristics of 40 nm bulk NFiNFET

∗ T. Park et al., SNU/KNU, Nanomes03 2003

∗ T. Park et al., SNU/KNU, Physica E19, p.6, 2003

2nd US-Korea NanoForum, LA Jong-Ho Lee

Modified Structure of Bulk FinFET
Thick SiN liner formation &
CMP and SiN liner only recessed
partial etch-back
Top Si Width 25 nm
Bottom Si Width 100 nm e
d
Si Fin Height 230 nm unclear tr o
Elec
t e
Oxide Ga
SiO
2
Si

Fin
SiO
2

SiN

ra te
st
S ub
‹ Clear Sidewall Open S i

‹ Planarization of the Top Surface of Poly-Si Gate

ƒ Easy nano-scale patterning of gate poly-Si
∗ E. Yoon, J.-H. Lee, and T. park, Korea/Japan/USA/Germany patent

2nd US-Korea NanoForum, LA Jong-Ho Lee

Key Process Steps of Modified Bulk FinFET

2nd US-Korea NanoForum, LA Jong-Ho Lee

SEM Views of Key Process Steps

Gate

Active Fin

SiN
SiO2
SiN

Si Substrate
Si Substrate

SiN Liner Deposition SiN Recess Etch

2nd US-Korea NanoForum, LA Jong-Ho Lee

SEM Views of Key Process Steps

Gate Etch Profiles

Mask SiN Width = 70 nm, Poly-Si Neck Width = 47 nm

Poly-Si Bottom Width = 64 nm

SiN
Gate Stack
Gate Stack

Poly-Si
SiO2
SiN

Fins
Si Substrate
Si Substrate

Along Gate Line Across Gate Line

∗ T. Park et al., Samung/SNU/KNU, Symp. on VLSI Tech., 2003

2nd US-Korea NanoForum, LA Jong-Ho Lee

SEM and TEM Views of Key Process Steps

30 nm Si Fin
SiN Liner Deposition
Gate P
99 nm oly-Si
82˚ fin
Poly-Si
61 nm

SiO2
SiN

181 nm

SiN
Si Substrate

Along Gate Line 12 nm fin body

∗ T. Park et al., Samung/SNU/KNU, IEDM., 2003

2nd US-Korea NanoForum, LA Jong-Ho Lee

 Bulk FinFET Measurement
ID-VGS plot: ID, DIBL, SS, and Isub
-4 -4
10 10
-5 -1 V VBS = 0 V 1V -5
10 10
10
-6 VDS=-0.05 V VDS=0.05 V 10-6 ‹ Measured ID-VGS of N
10
-7
10
-7 and P type bulk FinFETs
LG=100 nm
|ID |, |ISUB| (A)

10
-8
W Fin=25 nm 10
-8 with drain bias
TOx,top=1.8 nm
10
-9
HFin=100 nm 10
-9 ƒ high Ion(~200 µA/µm
ID TOx,top=5.5 nm
-10
10 ISUB
-10
10 @ VGS=1.5 V) compared
-11 ISUB -11
to that of first lot devices
10 VDS=1 V 10
VDS=-1 V
-12
10 10
-12
ƒ low Ioff (<0.2 nA/µm
-13
10
-0.05 V 0.05 V 10
-13
@ VDS=1.0 V)
-14
10 10
-14
ƒ Isub/ID < ~10-7
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0
Gate Voltage (V)

2nd US-Korea NanoForum, LA Jong-Ho Lee

Static Noise Margin (SNM)
Bulk FinFET

Planar MOSFET

Pass
Load

Pull-Down
2nd US-Korea NanoForum, LA
W/L
Load: 35 nm/90 nm
Pass: 35 nm/90 nm
Pull-Down: 50 nm/90 nm
Jong-Ho Lee
Summary
™ Briefly introduced key features of double/triple-gate
FinFETs

™ Bulk FinFETs were compared with SOI FinFETs

ƒ Nearly the same device scalability
ƒ Better wafer quality
ƒ Better characteristics regarding the body connected to sub.

™ Bulk FinFETs have been demonstrated experimentally

ƒ First nano-scale bulk FinFET realized by using spacer technology
ƒ Modified bulk FinFETs realized by adopting selective Si3N4 recess

™ Good device characteristics were achieved and SNM of

280 mV was obtained from SRAM cell at VCC of 1.2 V

2nd US-Korea NanoForum, LA Jong-Ho Lee

3-D Device Structure for Simulation

Gate LG=25 nm TOX=1.5 nm

S/D

S/D
S/D S/D

SiO2 body

Si substrate
Si substrate
body

2nd US-Korea NanoForum, LA Jong-Ho Lee

Key Process Steps for Thinning of the Fin Body

2nd US-Korea NanoForum, LA Jong-Ho Lee