S.R.

MOS DIFFERENTIAL PAIR-1

Common Mode and differential Mode inputs
Ramesh
August 16, 2008

EC o4 405 Electronics circuit 2

rameshpkd@gmail.com
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 MOS DIFFERENTIAL PAIR-1
Common Mode and differential Mode inputs

The fig shows the basic MOS differential pair configuration. Q1 and Q2, matched transistors, are biased by a
constant current source. Assume the current source is ideal and that it has high input impedance.

1. Operation with a Common mode input voltage;

Vdd
Consider the circuit below, here the two gate terminals +V

are joined together and connected to a voltage

Vg1=Vg2=Vicm. Rd Rd
- +
Since Q1 and Q2 are matched Vo
Vd2
Vd1
iD1 iD2
(1) Q1 Q2
+
Vcm I/2
(2) I/2
-

(3)

That is the differential pair does not respond to a common I

mode input signal.
- Vss

2. Operation with a Differential input voltage.

Vdd
+V
Here we are going to consider two cases
1. Let the , which means that there is a
Rd Rd
small difference between the two inputs.
- +
In this case Vo
Vd2
MOS DIFFERENTIAL PAIR-1 | August 16, 2008

Vd1
iD1 iD2
Q1 Q2
2. When +
Vid 0
I
-

From the above it is clear that the differential pair responds to

difference mode or differential i/p signal between the two drains.
I

By adjusting the value of Vid, we can make any one of the transistor
- Vss
ON (OFF) and the other OFF (ON). i.e. the causes the entire
bias current I to flow in one of the two transistors.
{ That is when the id s will be and the
corresponding o/p will be
, and (4)

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Or, } (5)

This property is known as current steering.

(6)

To use the differential pair as a linear amplifier, we keep the differential input signal small .i.e. when is
very small, so that
(7)
and (8)
Thus,

(9)
Since , (10)

MOS DIFFERENTIAL PAIR-1 | August 16, 2008

Ref: Sedra/Smith: Micro electronic circuits: 5th edition

By

Ramesh.K

rameshpkd@gmail.com

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 S.R.K

MOS DIFFERENTIAL PAIR

LARGE SIGNAL ANALYSIS
Ramesh
August 14, 2008

EC o4 405 Electronics circuit 2

rameshpkd@gmail.com
www.edutalks.org
 MOS DIFFERENTIAL PAIR
LARGE SIGNAL ANALYSIS

The fig shows a MOS differential pair. Here Q1 and Q2 are two
+V Vdd
matched transistors, biased by a common current source I, with
identical drain resistances Rd s.
Rd Rd
Vg1 and Vg2 are two input voltages applied at the gates G1 and - +
Vo
G2.
Q2
Q1
(1) + +
Vg1 Vg2

-
(2) -

Let Vid be the differential i/p voltage,

I

(3)
- Vss
The drain current of a MOSFET is given by the relation
(4)

Where W=the width of the Channel,

L= the length of the Channel,
The threshold voltage,
= the process trans-conductance parameter

Hence the currents and can be written as follows

(5)

(6)
MOS DIFFERENTIAL PAIR | August 14, 2008

Taking square root on both side we get, (7)

(8)

(7)-(8), gives (9)

(10)

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(11)

(12)

= (13)

(14)

Using (13),

Squaring both sides of (15) (15)

(16)

Or, (17)

But we have is positive, hence >

(18)

From (18) & (13) (19)

MOS DIFFERENTIAL PAIR | August 14, 2008

At the bias(quiescent) point (20)

Correspondingly, (21)

(22)

(23)

(25)

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 Substituting (25) in (18) and (19),

(26)

(27)

Normalized plots for currents in MOS Differential Pair.

0.5

-1.4 0 1.4

, and .
, and
Because of the square term in the above equations of the transfer characteristics are non-linear.
To get a linear relation ship (or amplification) from the DP, keep
Small signal approximation
MOS DIFFERENTIAL PAIR | August 14, 2008

(28)

(29)

From (29), When the differential (30)

current.

When a small signal , (31)

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where is the signal current. Comparing,(29)and(31) (32)

We have the trans-conductance, (33)

From (33) and (32) (34)

Here the represents the trans-conductance of the differential pair (Q1 and Q2), (35)

This is because divides equally between the two devices.

MOS DIFFERENTIAL PAIR | August 14, 2008

Ref: Micro Electronic Circuits; Sedra/Smith. 5th Edition

By

Ramesh.K

rameshpkd@gmail.com

www.edutalks.org
4