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DEPARTMENT OF ECE
TWO MARK
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Selvam College of technology
Department of Electronics and Communication Engineering
Microcontroller And RISC Architecture
Unit-1
8051 ARCHITECTURE
1. Features of 8051microcontroller.
• 8 bit controller operating on bit and byte.
• 256 bytes internal RAM and 4 kb internal RAM
• 64/60 kb external program memory address space
• 64 kb external data memory address space
• 4 numbers of 8 bit parallel ports.
3.
Access times for memory and Less access time
i/o devices are more. required.
4.
Microprocessor based system Less flexible in design
is more flexible in design point of view.
point of view.
5.
Less no of pins are multi More no of pins are
functioned mutlifunctioned
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3. State the functions of RS1 and RS0 bit in the flag register
It is used to select the register banks
RR A RRC A
Rotate accumulator right Rotate accumulator right through carry
flag
The 8 bits in the accumulator are The 8 bits in the accumulator and the
rotated 1 bit to the right.bit 0 is rotated carry flag together rotated 1 bit to the
in to the bit 7 position. No flags are right.bit 0 is moves in to the bit carry
affected. flag; the original value of the flag
moves in to the bit 7 position. No flags
are affected.
B7 B6 B5 B4 B3 B2 B1 B0
CY AC F0 RS1 RS0 OF - P
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9. List the addressing modes supported by 8051.
• Register addressing
• Direct byte addressing
• Register indirect
• Immediate
• Register specific
• Index
• The 8051 LIFO .Stack can reside anywhere in the internal RAM
• it has 8 bit stack pointer to indicate the top if stack. This can be accessed by
PUSH and POP instructions.
• During PUSH the SP is incremented by 1 and during POP the SP is
decremented by 1.
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15. Explain the interrupts of 8051 microcontroller.
The interrupts are:
Vector address
Serial Interrupt
The program counter keeps track of program execution. To execute a program the
starting address of the program is loaded in program counter. The PC sends out an
address to fetch a byte of instruction from memory and increments its content
automatically.
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Selvam College of technology
Department of Electronics and Communication Engineering
Microcontroller And RISC Architecture
Unit-2
8051Assembly language programming
2. How to estimate the time taken to execute the instruction in 8031/8051 controller
• It is obtained by multiplying the time to execute machine cycle by the number of
machine cycles of the instruction. The time to execute a machine time is 12 clock
periods.
• Time to execute an instruction=C *12* T=C *12 *1/F.
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MOV DPTR,#5000
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12. Write about the jump statement.
In this mode serial enters &exits through RXD, TXD outputs the shift clock.8 bits
are transmitted/received: 8 data bits (LSB first).The baud rate is fixed at 1/12 the oscillator
frequency.
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18. Explain the mode3 of 8051 serial ports.
In all the four modes, transmission is initiated by any instruction that uses SBUF
as a destination register. Reception is initiated in Mode0 by the condition
RI=0&REN=1.Reception is initiated in other modes by the incoming start bit if REN=1.
MOV A, #data
SWAP A
20. Write a program to subtract two 8-bit numbers &exchange the digits using
8051.
MOV A,#9F
MOV R0,#40
SUBB A,R0
SWAP A
21. Write a program to subtract the contents of R1 of Bank 0from the contents of R0
of Bank 2 using 8051.
MOV PSW,#10
MOV A,R0
MOV PSW,#00
SUBB A,R1
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Selvam College of technology
Department of Electronics and Communication Engineering
Microcontroller and RISC architecture
Unit-3
8051 Real World Interfacing
2 MARK QUESTIONS & ANSWERS
1. Give the M/IO used for interfacing technique.
M/IO=1; microprocessor communicating with memory system.
M/IO=0; microprocessor communicating with IO system.
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9. What are the parameters needed to interface memory?
Address to output delay (tACC)
CE to output delay (tCE)
Output enable to output delay (tOE).
10. What is meant by SRAM and its applications?
Static RAM or SRAM is a type of RAM that uses a flip-flop as its basic storage
element.
Application: To avoid inserting WAIT states, most high speed micro computer systems
require a cache memory subsystem. These systems are normally designed using SRAM.
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Selvam College of Technology
Department of Electronics and communication Engineering
Microcontroller and RISC architecture
Unit-4
The ARM RISC Architecture
1. Give the difference between RISC and CISC processor
• A fixed (32-bit) instruction size with few formats; CISC processors typically had
Variable length instruction sets with many formats.
• A load-store architecture where instructions that process data operate only on registers and
are separate from instructions that access memory; CISC processors typically allowed values in
memory to be used as operands in data processing instructions.
• A large register bank of thirty-two 32-bit registers, all of which could be used for
any purpose, to allow the load-store architecture to operate efficiently; CISC
register sets were getting larger, but none was this large and most had different
registers for different purposes (for example, the data and address registers on the
Motorola MC68000).
5. What are the factors determine the CMOS circuit power consumption?
• Switching power
• Short circuit power
• Leakage current
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7. What are the features used in the ARM processor?
• a load-store architecture;
• fixed-length 32-bit instructions;
• 3-address instruction formats.
• N: Negative; the last ALU operation which changed the flags produced a negative
result (the top bit of the 32-bit result was a one).
• Z: Zero; the last ALU operation which changed the flags produced a zero result
(every bit of the 32-bit result was zero).
• C: Carry; the last ALU operation which changed the flags generated a carry-out,
either as a result of an arithmetic operation in the ALU or from the shifter.
• V: overflow; the last arithmetic ALU operation which changed the flags generated
an overflow into the sign bit
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Cycle. In this stage the instruction 'owns' the decode logic but not the datapath.
• Execute;
The instruction 'owns' the datapath; the register bank is read, an operand shifted,
the ALU result generated and written back into a destination register.
14. What are the ways to find the breaks in the pipeline?
The simplest way to view breaks in the ARM pipeline is to observe that:
• All instructions occupy the data path for one or more adjacent cycles.
• For each cycle that an instruction occupies the data path, it occupies the decode
logic in the immediately preceding cycle.
• During the first data path cycle each instruction issues a fetch for the next instruction but one.
• Branch instructions flush and refill the instruction pipeline.
15. What are the ways to improve the performance of 5 stage pipeline?
Increase the clock rate, fclk.
• Reduce the average number of clock cycles per instruction, CPI.
• Fetch;
The instruction is fetched from memory and placed in the instruction pipeline.
• Decode;
The instruction is decoded and register operands read from the register file. There are
three operand read ports in the register file, so most ARM instructions can source all their
operands in one cycle.
• Execute;
An operand is shifted and the ALU result generated. If the instruction is a load or store
the memory address is computed in the ALU.
• Buffer/data;
Data memory is accessed if required. Otherwise the ALU result is simply buffered for
one clock cycle to give the same pipeline flow for all instructions.
• Write-back;
The results generated by the instruction are written back to the register file,including any
data loaded from memory.
17. What are the factors determines the minimum cycle time ?
The minimum datapath cycle time is therefore the sum of:
• the register read time;
• the shifter delay;
• the ALU delay;
• the register write set-up time;
• the phase 2 to phase 1 non-overlap time.
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18. What the features are of ARM 7 processor?
• The ARM7, a 3 volt compatible rework of the ARM6 32-bit integer core, with the Thumb 16-
bit compressed instruction set;
• on-chip Debug support, enabling the processor to halt in response to a debug request;
• an enhanced Multiplier, with higher performance than its predecessors and yielding a full 64-bit
result;
• EmbeddedlCE hardware to give on-chip breakpoint and watch point support.
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Selvam College of Technology
Department of Electronics and communication Engineering
Microcontroller And RISC Architecture
Unit-5
The ARM Instruction And Assembly Language Programming
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These instructions are available on ARM chips which support the Thumb (16-bit) instruction set,
and are a mechanism for switching the processor to execute Thumb instructions or for returning
symmetrically to ARM and Thumb calling routines.
11. Explain about single word and unsigned byte data transfer instruction.
These instructions are the most flexible way to transfer single bytes or words of data between
ARM's registers and memory. Transferring large blocks of data is usually better done using the
multiple register transfer instructions, and recent ARM processors also support instructions for
transferring half-words and signed bytes.
12. Explain about half word and signed byte data transfer.
These instructions are not supported by some early ARM processors. As a result of their late
addition to the architecture they are somewhat 'shoe-horned' into the instruction space as
indicated by the split immediate field.
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15. What are the data types supported by ARM?
• Signed and unsigned characters of at least eight bits.
• Signed and unsigned short integers of at least 16 bits.
• Signed and unsigned integers of at least 16 bits.
• Signed and unsigned long integers of at least 32 bits.
• Floating-point, double and long double floating-point numbers.
• Enumerated types.
• Bitfields.
The ARM C compiler adopts the minimum sizes for each of these types except the standard
integer.
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