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ALGORITM:
Step1: Define the specifications and initialize the design.
Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VERILOG.
Step4: Check the syntax and debug the errors if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the place and route report.
LOGIC DIAGRAM:
A B Y=AB
0 0 0 A B Y=A+B
0 1 0
0 0 0
1 0 0
NOT GATE: 0 1 1
1 1 1
NAND GATE: 1 0 1
LOGIC DIAGRAM: TRUTH TABLE: LOGICDIAGRAM 1 1 1
TRUTH TABLE
A B Y=(AB)’
A Y=A’
0 0 1
0 1
1 0 0 1 1
1 0 1
1 1 0
NOR GATE: XOR GATE:
LOGIC DIAGRAM: TRUTH TABLE: LOGICDIAGRAM TRUTH TABLE
A B Y=(A+B)’ A B
XNOR GATE:
0 0 1 0 0 0
LOGIC DIAGRAM: 0 1 0 TRUTH 0 1 1
TABLE: 1 0 0 1 0 1
1 1 0 A B 1 1 0
0 0 1
0 1 0
1 0 0
1 1 1
entity logicgates is
Port ( a : in std_logic;
b : in std_logic;
c : out std_logic_vector(6 downto 0));
end logicgates;
begin
c(0)<= a and b;
c(1)<= a or b;
c(2)<= a nand b;
c(3)<= a nor b;
c(4)<= a xor b;
c(5)<= a xnor b;
c(6)<= not a;
end dataflow;
endmodule
TEST BENCH(VHDL):
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY logicgatestest_vhd IS
END logicgatestest_vhd;
BEGIN
tb : PROCESS
BEGIN
END PROCESS;
END testbench;
Simulation output:
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : logicgates.ngr
Top Level Output File Name : logicgates
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs :9
Cell Usage :
# BELS :7
# INV :1
# LUT2 :6
# IO Buffers :9
# IBUF :2
# OBUF :7
=========================================================================
TIMING REPORT
Clock Information:
------------------
No clock signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 13 / 7
-------------------------------------------------------------------------
Delay: 7.985ns (Levels of Logic = 3)
Source: a (PAD)
Destination: c<5> (PAD)
=========================================================================
CPU : 3.03 / 3.27 s | Elapsed : 3.00 / 4.00 s
RESULT:
Thus the outputs of Basic Logic Gates are verified by simulating and synthesizing the VHDL and
VERILOG code.
ALGORITM:
Step1: Define the specifications and initialize the design.
Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VERILOG.
Step4: Check the syntax and debug the errors if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the place and route report.
HALF ADDER:
A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Dataflow Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hadd is
Port ( a : in std_logic;
b : in std_logic;
sum : out std_logic;
carry : out std_logic);
end hadd;
architecture dataflow of hadd is
begin
sum <= a xor b;
carry <= a and b;
end dataflow;
Behavioral Modeling:
Structural Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity haddstructural is
Port ( a : in std_logic;
b : in std_logic;
sum : out std_logic;
carry : out std_logic);
end haddstructural;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity and2 is
Port ( a : in std_logic;
b : in std_logic;
z : out std_logic);
end and2;
architecture dataflow of and2 is
begin
z<= a and b;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity xor2 is
Port ( a : in std_logic;
b : in std_logic;
z : out std_logic);
end xor2;
architecture dataflow of xor2 is
begin
z<= a xor b;
end dataflow;
Dataflow Modeling:
Behavioral Modeling:
Structural Modeling:
ENTITY test_bench_vhd IS
END test_bench_vhd;
COMPONENT hadd
PORT(
a : IN std_logic;
b : IN std_logic;
sum : OUT std_logic;
carry : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL a : std_logic := '0';
SIGNAL b : std_logic := '0';
--Outputs
SIGNAL sum : std_logic;
SIGNAL carry : std_logic;
BEGIN
tb : PROCESS
BEGIN
END PROCESS;
END;
Simulation output:
Timing Summary:
---------------
Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.824ns
HALF SUBSTRACTOR:
A B DIFFERENCE BORROW
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hsub_dataflow is
Port ( a : in std_logic;
b : in std_logic;
diff : out std_logic;
borrow : out std_logic);
end hsub_dataflow;
architecture dataflow of hsub_dataflow is
begin
diff <= a xor b;
borrow <= not a and b;
end dataflow;
Behavioral Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hsub_behv is
Port ( a : in std_logic;
b : in std_logic;
diff : out std_logic;
borrow : out std_logic);
end hsub_behv;
architecture Behavioral of hsub_behv is
begin
p1:process(a,b)
variable abar:std_logic;
begin
abar:= not a;
diff<=a xor b;
borrow<=abar and b;
end process p1;
end Behavioral;
Structural Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hsub_structural is
Port ( a : in std_logic;
b : in std_logic;
diff : out std_logic;
borrow : out std_logic);
end hsub_structural;
architecture structural of hsub_structural is
component xor2
port(a,b:in std_logic;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity and2 is
Port ( a : in std_logic;
b : in std_logic;
z : out std_logic);
end and2;
architecture dataflow of and2 is
begin
z<= a and b;
end dataflow;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity xor2 is
Port ( a : in std_logic;
b : in std_logic;
z : out std_logic);
end xor2;
architecture dataflow of xor2 is
begin
z<= a xor b;
end dataflow;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity not1 is
Port ( a : in std_logic;
z : out std_logic);
end not1;
architecture dataflow of not1 is
Dataflow Modeling:
Behavioral Modeling:
Structural Modeling:
TEST BENCH(VHDL):
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY test_vhd IS
END test_vhd;
--Inputs
SIGNAL a : std_logic := '0';
SIGNAL b : std_logic := '0';
--Outputs
SIGNAL diff : std_logic;
SIGNAL borrow : std_logic;
BEGIN
tb : PROCESS
BEGIN
END PROCESS;
END;
Simulation output:
=========================================================================
TIMING REPORT
Clock Information:
------------------
No clock signals found in this design
Timing Summary:
---------------
Speed Grade: -5
FULL ADDER:
A B C SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Dataflow Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fadd_dataflow is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
sum : out std_logic;
carry : out std_logic);
end fadd_dataflow;
architecture dataflow of fadd_dataflow is
signal p,q,r,s:std_logic;
begin
p<= a xor b;
q<= a and b;
r<= b and c;
s<= c and a;
sum<= p xor c;
carry<= q or r or s;
end dataflow;
Behavioral Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fadd_behv is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
sum : out std_logic;
carry : out std_logic);
end fadd_behv;
architecture Behavioral of fadd_behv is
Structural Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fadd_structural is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
sum : out std_logic;
carry : out std_logic);
end fadd_structural;
architecture structural of fadd_structural is
component xor2
port(a,b:in std_logic;
z:out std_logic);
end component;
component and2
port(a,b:in std_logic;
z:out std_logic);
end component;
component or3
port(a,b,c:in std_logic;
z:out std_logic);
end component;
signal p,q,r,s:std_logic;
begin
x1: xor2 port map (a,b,p);
x2: xor2 port map (p,c,sum);
a1: and2 port map (a,b,q);
a2: and2 port map (b,c,r);
a3: and2 port map (c,a,s);
o1: or3 port map (q,r,s,carry);
end structural;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity and2 is
Port ( a : in std_logic;
b : in std_logic;
z : out std_logic);
end and2;
architecture dataflow of and2 is
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity or3 is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
z : out std_logic);
end or3;
architecture dataflow of or3 is
begin
z<= a or b or c;
end dataflow;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity xor2 is
Port ( a : in std_logic;
b : in std_logic;
z : out std_logic);
end xor2;
architecture dataflow of xor2 is
begin
z<= a xor b;
end dataflow;
Dataflow Modeling:
Behavioral Modeling:
Structural Modeling:
TEST BENCH(VHDL):
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY test1_vhd IS
END test1_vhd;
--Inputs
SIGNAL a : std_logic := '0';
SIGNAL b : std_logic := '0';
SIGNAL c : std_logic := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: fadd_dataflow PORT MAP(
a => a,
b => b,
c => c,
sum => sum,
carry => carry
);
tb : PROCESS
BEGIN
Simulation output:
Synthesis report:
=========================================================================
=========================================================================
TIMING REPORT
Clock Information:
------------------
No clock signals found in this design
Timing Summary:
---------------
Speed Grade: -5
FULL SUBSTRACTOR:
Dataflow Modeling:
Behavioral Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fsub_behv is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
diff : out std_logic;
borrow : out std_logic);
end fsub_behv;
architecture Behavioral of fsub_behv is
begin
p1:process(a,b,c)
variable abar,r,s,t:std_logic;
begin
abar:=not a;
r:=abar and b;
s:=b and c;
t:=c and abar;
diff<=a xor b xor c;
borrow<=r or s or t;
end process p1;
end Behavioral;
Structural Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fsub_structural is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
diff : out std_logic;
borrow : out std_logic);
end fsub_structural;
architecture structural of fsub_structural is
Dataflow Modeling:
endmodule
Behavioral Modeling:
Structural Modeling:
TEST BENCH(VHDL):
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY tst_vhd IS
END tst_vhd;
--Inputs
SIGNAL a : std_logic := '0';
SIGNAL b : std_logic := '0';
SIGNAL c : std_logic := '0';
--Outputs
SIGNAL diff : std_logic;
SIGNAL borrow : std_logic;
BEGIN
tb : PROCESS
BEGIN
a<='0'; b<='0'; c<='0'; wait for 100 ps;
a<='0'; b<='0'; c<='1'; wait for 100 ps;
a<='0'; b<='1'; c<='0'; wait for 100 ps;
a<='0'; b<='1'; c<='1'; wait for 100 ps;
a<='1'; b<='0'; c<='0'; wait for 100 ps;
a<='1'; b<='0'; c<='1'; wait for 100 ps;
a<='1'; b<='1'; c<='0'; wait for 100 ps;
a<='1'; b<='1'; c<='1'; wait for 100 ps;
END PROCESS;
END;
Simulation output:
=========================================================================
TIMING REPORT
Clock Information:
------------------
No clock signals found in this design
Timing Summary:
---------------
Speed Grade: -5
A B C SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Structural Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fadd2 is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
sum : out std_logic;
carry : out std_logic);
end fadd2;
architecture structural of fadd2 is
component hadd
port(a,b:in std_logic;
sum,carry:out std_logic);
end component;
component or2
port(a,b:in std_logic;
z:out std_logic);
end component;
signal p,q,r:std_logic;
begin
h1:hadd port map (a,b,p,q);
h2:hadd port map (p,c,sum,r);
o1:or2 port map (r,q,carry);
end structural;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hadd is
Port ( a : in std_logic;
b : in std_logic;
sum : out std_logic;
carry : out std_logic);
end hadd;
architecture dataflow of hadd is
begin
sum <= a xor b;
carry <= a and b;
end dataflow;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity or2 is
Port ( a : in std_logic;
b : in std_logic;
z : out std_logic);
end or2;
architecture dataflow of or2 is
begin
z<= a or b;
end dataflow;
Structural Modeling:
TEST BENCH(VHDL):
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY tst_vhd IS
END tst_vhd;
--Inputs
SIGNAL a : std_logic := '0';
SIGNAL b : std_logic := '0';
SIGNAL c : std_logic := '0';
--Outputs
SIGNAL sum : std_logic;
SIGNAL carry : std_logic;
BEGIN
tb : PROCESS
BEGIN
a<='0'; b<='0'; c<='0'; wait for 100 ps;
a<='0'; b<='0'; c<='1'; wait for 100 ps;
a<='0'; b<='1'; c<='0'; wait for 100 ps;
a<='0'; b<='1'; c<='1'; wait for 100 ps;
a<='1'; b<='0'; c<='0'; wait for 100 ps;
a<='1'; b<='0'; c<='1'; wait for 100 ps;
a<='1'; b<='1'; c<='0'; wait for 100 ps;
a<='1'; b<='1'; c<='1'; wait for 100 ps;
END PROCESS;
END;
Simulation output:
Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------
=========================================================================
TIMING REPORT
Clock Information:
------------------
No clock signals found in this design
Timing Summary:
---------------
Speed Grade: -5
A B C DIFFERENCE BORROW
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Structural Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fsub2 is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
diff : out std_logic;
borrow : out std_logic);
end fsub2;
architecture structural of fsub2 is
component hsub_dataflow
port(a,b:in std_logic;
diff,borrow:out std_logic);
end component;
component or2
port(a,b:in std_logic;
z:out std_logic);
end component;
signal p,q,r:std_logic;
begin
h1:hsub_dataflow port map (a,b,p,q);
h2:hsub_dataflow port map (p,c,diff,r);
o1:or2 port map (r,q,borrow);
end structural;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Structural Modeling:
TEST BENCH(VHDL):
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY tst_vhd IS
END tst_vhd;
--Inputs
SIGNAL a : std_logic := '0';
SIGNAL b : std_logic := '0';
SIGNAL c : std_logic := '0';
--Outputs
SIGNAL diff : std_logic;
SIGNAL borrow : std_logic;
BEGIN
tb : PROCESS
BEGIN
a<='0'; b<='0'; c<='0'; wait for 100 ps;
a<='0'; b<='0'; c<='1'; wait for 100 ps;
a<='0'; b<='1'; c<='0'; wait for 100 ps;
a<='0'; b<='1'; c<='1'; wait for 100 ps;
a<='1'; b<='0'; c<='0'; wait for 100 ps;
a<='1'; b<='0'; c<='1'; wait for 100 ps;
a<='1'; b<='1'; c<='0'; wait for 100 ps;
a<='1'; b<='1'; c<='1'; wait for 100 ps;
END PROCESS;
END;
Simulation output:
=========================================================================
TIMING REPORT
Clock Information:
------------------
No clock signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Cin
Structural Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity rca is
Port ( a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
c : in std_logic;
s : out std_logic_vector(3 downto 0);
cout : out std_logic);
end rca;
architecture structural of rca is
component fadd_behv
port(a,b,c:in std_logic;
sum,carry:out std_logic);
end component;
signal c0,c1,c2:std_logic;
begin
f1:fadd_behv port map (a(0),b(0),c,s(0),c0);
f2:fadd_behv port map (a(1),b(1),c0,s(1),c1);
f3:fadd_behv port map (a(2),b(2),c1,s(2),c2);
f4:fadd_behv port map (a(3),b(3),c2,s(3),cout);
end structural;
Structural Modeling:
module rcastructural(a, b, c, s, cout);
input [3:0] a;
input [3:0] b;
input c;
output [3:0] s;
output cout;
wire c1,c2,c3;
fulladddataflow
f1(a[0],b[0],c,s[0],c1),
f2(a[1],b[1],c1,s[1],c2),
f3(a[2],b[2],c2,s[2],c3),
f4(a[3],b[3],c3,s[3],cout);
endmodule
FULL ADDER SOURCE CODE:
TEST BENCH(VHDL):
ENTITY test_vhd IS
END test_vhd;
BEGIN
tb : PROCESS
BEGIN
a<="0010";b<="1001";c<='1'; wait for 200 ps;
a<="1100";b<="0101";c<='0'; wait for 200 ps;
a<="1111";b<="0100";c<='1'; wait for 200 ps;
END PROCESS;
END;
Simulation output:
Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
--------------------------
Selected Device : 3s400tq144-5
Number of Slices: 5 out of 3584 0%
Number of 4 input LUTs: 9 out of 7168 0%
Number of bonded IOBs: 14 out of 97 14%
=========================================================================
TIMING REPORT
Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 11.747ns
LOGIC DIAGRAM:
Structural Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity csa is
Port ( a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
c : in std_logic;
su : inout std_logic_vector(3 downto 0);
sd : inout std_logic_vector(3 downto 0);
s : out std_logic_vector(7 downto 0);
cout : out std_logic);
end csa;
architecture structural of csa is
component rca
port(a,b:in std_logic_vector(3 downto 0);
c:in std_logic;
s:out std_logic_vector(3 downto 0);
cout:out std_logic);
end component;
component mux2
port(a,b,s:in std_logic;
z:out std_logic);
end component;
signal c1,c2,c3:std_logic;
begin
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity rca is
Port ( a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
c : in std_logic;
s : out std_logic_vector(3 downto 0);
cout : out std_logic);
end rca;
architecture structural of rca is
component fadd_behv
port(a,b,c:in std_logic;
sum,carry:out std_logic);
end component;
signal c0,c1,c2:std_logic;
begin
f1:fadd_behv port map (a(0),b(0),c,s(0),c0);
f2:fadd_behv port map (a(1),b(1),c0,s(1),c1);
f3:fadd_behv port map (a(2),b(2),c1,s(2),c2);
f4:fadd_behv port map (a(3),b(3),c2,s(3),cout);
end structural;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux2 is
Port ( a : in std_logic;
b : in std_logic;
s : in std_logic;
z : out std_logic);
end mux2;
architecture behv of mux2 is
begin
process(a,b,s)
begin
if (s='0') then
z<=a;
else
z<=b;
end if;
end process;
end behv;
Structural Modeling:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY test_vhd IS
END test_vhd;
--Inputs
SIGNAL c : std_logic := '0';
SIGNAL a : std_logic_vector(7 downto 0) := (others=>'0');
SIGNAL b : std_logic_vector(7 downto 0) := (others=>'0');
--BiDirs
SIGNAL su : std_logic_vector(3 downto 0);
SIGNAL sd : std_logic_vector(3 downto 0);
--Outputs
SIGNAL s : std_logic_vector(7 downto 0);
SIGNAL cout : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: csa PORT MAP(
a => a,
b => b,
c => c,
su => su,
sd => sd,
s => s,
cout => cout
);
tb : PROCESS
BEGIN
a<="11111010";b<="10101011";c<='1'; wait for 200ps;
a<="11001011";b<="11100011";c<='0'; wait for 200ps;
END PROCESS;
END;
=========================================================================
TIMING REPORT
Clock Information:
------------------
No clock signals found in this design
Timing Summary:
---------------
Speed Grade: -5
LOGIC DIAGRAM:
Structural Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cskadd is
Port ( a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
c : in std_logic;
s : out std_logic_vector(7 downto 0);
cout : out std_logic);
end cskadd;
architecture structural of cskadd is
component rca
port(a,b:in std_logic_vector(3 downto 0);
c:in std_logic;
s:out std_logic_vector(3 downto 0);
cout:out std_logic);
end component;
component skip
port(a,b:in std_logic_vector(3 downto 0);
c:in std_logic;
z:out std_logic);
end component;
component or2
port(a,b:in std_logic;
z:out std_logic);
end component;
signal c1,c2,c3,x1,x2:std_logic;
begin
r1:rca port map (a(3 downto 0),b(3 downto 0),c,s(3 downto 0),c1);
r2:rca port map (a(7 downto 4),b(7 downto 4),c2,s(7 downto 4),c3);
s1:skip port map (a(3 downto 0),b(3 downto 0),c,x1);
s2:skip port map (a(7 downto 4),b(7 downto 4),c2,x2);
o1:or2 port map (c1,x1,c2);
o2:or2 port map (c3,x2,cout);
end structural;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity rca is
Port ( a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
c : in std_logic;
s : out std_logic_vector(3 downto 0);
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity or2 is
Port ( a : in std_logic;
b : in std_logic;
z : out std_logic);
end or2;
architecture dataflow of or2 is
begin
z<= a or b;
end dataflow;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity skip is
Port ( a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
c : in std_logic;
z : out std_logic);
end skip;
architecture dataflow of skip is
begin
z<=(a(0) xor b(0)) and (a(1) xor b(1)) and (a(2) xor b(2)) and (a(3) xor b(3)) and c;
end dataflow;
Structural Modeling:
TEST BENCH(VHDL):
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY test_vhd IS
END test_vhd;
Simulation output:
Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------
=========================================================================
TIMING REPORT
Clock Information:
------------------
No clock signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Structural Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity calkadd is
Port ( a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
c : in std_logic;
s : out std_logic_vector(7 downto 0);
cout : out std_logic);
end calkadd;
architecture structural of calkadd is
component fulladd
port(a,b,c:in std_logic;
s,ca:out std_logic);
end component;
signal c0,c1,c2,c3,c4,c5,c6:std_logic;
begin
f1:fulladd port map (a(0),b(0),c,s(0),c0);
f2:fulladd port map (a(1),b(1),c0,s(1),c1);
f3:fulladd port map (a(2),b(2),c1,s(2),c2);
f4:fulladd port map (a(3),b(3),c2,s(3),c3);
f5:fulladd port map (a(4),b(4),c3,s(4),c4);
f6:fulladd port map (a(5),b(5),c4,s(5),c5);
f7:fulladd port map (a(6),b(6),c5,s(6),c6);
f8:fulladd port map (a(7),b(7),c6,s(7),cout);
end structural;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fulladd is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
s : out std_logic;
ca : out std_logic);
end fulladd;
architecture dataflow of fulladd is
signal l,m,g,p:std_logic;
begin
l<=a xor b;
m<=p and c;
g<=a and b;
p<=a or b;
s<=c xor l;
ca<=g or m;
end dataflow;
Structural Modeling:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY test_vhd IS
END test_vhd;
--Inputs
SIGNAL c : std_logic := '0';
SIGNAL a : std_logic_vector(7 downto 0) := (others=>'0');
SIGNAL b : std_logic_vector(7 downto 0) := (others=>'0');
--Outputs
SIGNAL s : std_logic_vector(7 downto 0);
SIGNAL cout : std_logic;
BEGIN
tb : PROCESS
BEGIN
a<="11111010";b<="10101011";c<='1'; wait for 200ps;
a<="11001011";b<="11100011";c<='0'; wait for 200ps;
END PROCESS;
END;
Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------
Clock Information:
------------------
No clock signals found in this design
Timing Summary:
---------------
Speed Grade: -5
RESULT:
Thus the OUTPUT’s of Adders,Subtractors and Fast Adders are verified by synthesizing and simulating the
VHDL and VERILOG code.
ALGORITM:
ENCODER:
D0 D1 D2 D3 D4 D5 D6 D7 X Y Z
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
--Design : ENCODER
--Description : To implement ENCODER
--Author : AMRUTHA V
--Reg no : 2882101
--Version : Xilinx- 7.1i
Dataflow Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity encoder_dataflow is
Port ( d : in std_logic_vector(7 downto 0);
z : out std_logic_vector(2 downto 0));
end encoder_dataflow;
architecture dataflow of encoder_dataflow is
begin
z(2)<= d(4) or d(5) or d(6) or d(7);
z(1)<= d(2) or d(3) or d(6) or d(7);
z(0)<= d(1) or d(3) or d(5) or d(7);
end dataflow;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity encoder_behv is
Port ( d : in std_logic_vector(7 downto 0);
e : in std_logic;
z : out std_logic_vector(2 downto 0));
end encoder_behv;
architecture Behavioral of encoder_behv is
begin
p1:process(d,e)
begin
if (e='1') then
case d is
when "10000000"=>z<="000";
when "01000000"=>z<="001";
when "00100000"=>z<="010";
when "00010000"=>z<="011";
when "00001000"=>z<="100";
when "00000100"=>z<="101";
when "00000010"=>z<="110";
when "00000001"=>z<="111";
when others=>z<="ZZZ";
end case;
else
z<="XXX";
end if;
end process p1;
end Behavioral;
Structural Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity encoder_struct is
Port ( d : in std_logic_vector(7 downto 0);
z : out std_logic_vector(2 downto 0));
end encoder_struct;
architecture structural of encoder_struct is
component or4
port(a,b,c,d:in std_logic;
z:out std_logic);
end component;
begin
o1:or4 port map (d(4),d(5),d(6),d(7),z(0));
o2:or4 port map (d(2),d(3),d(6),d(7),z(1));
o3:or4 port map (d(1),d(3),d(5),d(7),z(2));
end structural;
Dataflow Modeling:
Behavioral Modeling:
Structural Modeling:
ENTITY test_vhd IS
END test_vhd;
BEGIN
tb : PROCESS
BEGIN
d<="10000000"; wait for 100ps;
d<="00010000"; wait for 100ps;
d<="00100000"; wait for 100ps;
END PROCESS;
END;
Simulation output:
Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------
=========================================================================
TIMING REPORT
Clock Information:
------------------
No clock signals found in this design
Timing Summary:
---------------
Speed Grade: -5
0 0 1 0 1 1 1
0 1 1 1 0 1 1
1 0 1 1 1 0 1
1 1 1 1 1 1 0
--Design : DECODER
--Description : To implement DECODER
--Author : AMRUTHA V
--Reg no : 2882101
--Version : Xilinx- 7.1i
Dataflow Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder_dataflow is
Port ( a : in std_logic;
b : in std_logic;
e : in std_logic;
z : out std_logic_vector(3 downto 0));
end decoder_dataflow;
architecture dataflow of decoder_dataflow is
signal abar,bbar:std_logic;
begin
abar<= not a;
bbar<= not b;
z(0)<= not (abar and bbar and e);
z(1)<= not (abar and b and e);
z(2)<= not (a and bbar and e);
z(3)<= not (a and b and e);
end dataflow;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder_behv is
Port ( a : in std_logic;
b : in std_logic;
e : in std_logic;
z : out std_logic_vector(3 downto 0));
end decoder_behv;
architecture Behavioral of decoder_behv is
begin
p1:process(a,b)
begin
if (e='1') then
z(0)<= not a and not b ;
z(1)<= not a and b;
z(2)<= a and not b;
z(3)<= a and b;
else
z<="1111";
end if;
end process p1;
end Behavioral;
Structural Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder_struct is
Port ( a : in std_logic;
b : in std_logic;
e : in std_logic;
z : out std_logic_vector(3 downto 0));
end decoder_struct;
architecture structural of decoder_struct is
component nand3
port(a,b,c:in std_logic;
z:out std_logic);
end component;
component not1
port(a:in std_logic;
z:out std_logic);
end component;
signal abar,bbar:std_logic;
begin
n1:not1 port map (a,abar);
n2:not1 port map (b,bbar);
a1:nand3 port map (abar,bbar,e,z(0));
a2:nand3 port map (abar,b,e,z(1));
a3:nand3 port map (a,bbar,e,z(2));
a4:nand3 port map (a,b,e,z(3));
end structural;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity not1 is
Port ( a : in std_logic;
z : out std_logic);
end not1;
architecture dataflow of not1 is
begin
z<= not a;
end dataflow;
Dataflow Modeling:
Behavioral Modeling:
reg [3:0] z;
end
endmodule
Structural Modeling:
TEST BENCH(VHDL):
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY test_vhd IS
END test_vhd;
--Inputs
SIGNAL a : std_logic := '0';
SIGNAL b : std_logic := '0';
SIGNAL e : std_logic := '0';
--Outputs
SIGNAL z : std_logic_vector(3 downto 0);
BEGIN
tb : PROCESS
BEGIN
a<='0';b<='0';e<='0'; wait for 100ps;
a<='0';b<='0';e<='1'; wait for 100ps;
a<='0';b<='1';e<='1'; wait for 100ps;
a<='1';b<='0';e<='1'; wait for 100ps;
a<='1';b<='1';e<='1'; wait for 100ps;
END PROCESS;
END;
Simulation output:
Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------
=========================================================================
Clock Information:
------------------
No clock signals found in this design
Timing Summary:
---------------
Speed Grade: -5
RESULT:
Thus the OUTPUT’s of Encoder and Decoder are verified by synthesizing and simulating the VHDL and
VERILOG code.
ALGORITM:
MULTIPLEXER:
LOGIC DIAGRAM:
TRUTH TABLE:
1
D0 2 9
8
4
1 Y S1 S0 Y
5
0 0 D0
1
D2 2 9
8
1
0 1 D1
D3 2 9
1 0 D2
8
2
1 1 D3
1
S1 S0
--Design : MULTIPLEXER
--Description : To implement MULTIPLEXER
--Author : AMRUTHA V
--Reg no : 2882101
--Version : Xilinx- 7.1i
Dataflow Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux_dataflow is
Port ( d : in std_logic_vector(3 downto 0);
s : in std_logic_vector(1 downto 0);
y : out std_logic);
end mux_dataflow;
architecture dataflow of mux_dataflow is
signal s0bar,s1bar,p,q,r,st:std_logic;
begin
p<= d(0) and s0bar and s1bar;
Behavioral Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux_behv is
Port ( d : in std_logic_vector(3 downto 0);
s : in std_logic_vector(1 downto 0);
y : out std_logic);
end mux_behv;
architecture Behavioral of mux_behv is
begin
p1:process(d,s)
begin
if (s(0)<='0' and s(1)<='0') then
y<=d(0);
elsif (s(0)<='0' and s(1)<='1') then
y<=d(1);
elsif (s(0)<='1' and s(1)<='0') then
y<=d(2);
else
y<=d(3);
end if;
end process p1;
end Behavioral;
Structural Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux_struct is
Port ( d : in std_logic_vector(3 downto 0);
s : in std_logic_vector(1 downto 0);
y : out std_logic);
end mux_struct;
architecture structural of mux_struct is
component not1
port(a:in std_logic;
z:out std_logic);
end component;
component and3
port(a,b,c:in std_logic;
z:out std_logic);
end component;
component or4
port(a,b,c,d:in std_logic;
z:out std_logic);
end component;
signal s0bar,s1bar,p,q,r,st:std_logic;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity and3 is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
z : out std_logic);
end and3;
architecture dataflow of and3 is
begin
z<=a and b and c;
end dataflow;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity not1 is
Port ( a : in std_logic;
z : out std_logic);
end not1;
architecture dataflow of not1 is
begin
z<= not a;
end dataflow;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity or4 is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
z : out std_logic);
end or4;
architecture dataflow of or4 is
begin
z<=a or b or c or d;
end dataflow;
Dataflow Modeling:
Behavioral Modeling:
Structural Modeling:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY test_vhd IS
END test_vhd;
--Inputs
SIGNAL d : std_logic_vector(3 downto 0) := (others=>'0');
SIGNAL s : std_logic_vector(1 downto 0) := (others=>'0');
--Outputs
SIGNAL y : std_logic;
BEGIN
tb : PROCESS
BEGIN
d<="0101";s<="00"; wait for 100ps;
d<="0011";s<="01"; wait for 100ps;
d<="1110";s<="10"; wait for 100ps;
END PROCESS;
END;
Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------
=========================================================================
TIMING REPORT
Clock Information:
------------------
No clock signals found in this design
Timing Summary:
DEMULTIPLEXER:
LOGIC DIAGRAM: `
TRUTH TABLE:
S1 S0
INPUT OUTPUT
D S0 S1 Y0 Y1 Y2 Y3
1 0 0 1 0 0 0
1
1 0 1 0 1 0 0
1 1 0 0 0 1 0
2
Din 2
3 1 1 1 0 0 0 1
1
4 Y0
5
2
3
1
4 Y1
5
2
3
1
4 Y2
5
2
3
1
4 Y3
5
Enable
--Design : DEMULTIPLEXER
--Description : To implement DEMULTIPLEXER
--Author : AMRUTHA V
--Reg no : 2882101
--Version : Xilinx- 7.1i
Dataflow Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity demux_dataflow is
Port ( d : in std_logic;
s : in std_logic_vector(1 downto 0);
z : out std_logic_vector(3 downto 0));
end demux_dataflow;
architecture dataflow of demux_dataflow is
signal s0bar,s1bar:std_logic;
begin
s0bar<= not s(0);
Behavioral Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity demux_behv is
Port ( d : in std_logic;
s : in std_logic_vector(1 downto 0);
z : out std_logic_vector(3 downto 0));
end demux_behv;
architecture Behavioral of demux_behv is
begin
p1:process(d,s)
begin
if (s(0)<='0' and s(1)<='0') then
z(0)<=d;
z(1)<='Z';
z(2)<='Z';
z(3)<='Z';
elsif (s(0)<='0' and s(1)<='1') then
z(0)<='Z';
z(1)<=d;
z(2)<='Z';
z(3)<='Z';
elsif (s(0)<='1' and s(1)<='0') then
z(0)<='Z';
z(1)<='Z';
z(2)<=d;
z(3)<='Z';
else
z(0)<='Z';
z(1)<='Z';
z(2)<='Z';
z(3)<=d;
end if;
end process p1;
end Behavioral;
Structural Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity demux_struct is
Port ( d : in std_logic;
s : in std_logic_vector(1 downto 0);
z : out std_logic_vector(3 downto 0));
end demux_struct;
architecture structural of demux_struct is
component not1
port(a:in std_logic;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity and3 is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
z : out std_logic);
end and3;
architecture dataflow of and3 is
begin
z<=a and b and c;
end dataflow;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity not1 is
Port ( a : in std_logic;
z : out std_logic);
end not1;
architecture dataflow of not1 is
begin
z<= not a;
end dataflow;
Dataflow Modeling:
module demuxdataflow(s0,s1,i,y);
input s0,s1,i;
output [3:0] y;
wire s2,s3;
assign #2 s2=~s0;
assign #2 s3=~s1;
assign #3 y[0]=i&s2&s3;
assign #3 y[1]=i&s2&s1;
Behavioral Modeling:
Structural Modeling:
TEST BENCH(VHDL):
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY test_vhd IS
END test_vhd;
--Inputs
SIGNAL d : std_logic := '0';
SIGNAL s : std_logic_vector(1 downto 0) := (others=>'0');
--Outputs
SIGNAL z : std_logic_vector(3 downto 0);
BEGIN
tb : PROCESS
BEGIN
d<='1'; s<="00"; wait for 100ps;
d<='0'; s<="01"; wait for 100ps;
d<='1'; s<="10"; wait for 100ps;
END PROCESS;
END;
Simulation output:
=========================================================================
TIMING REPORT
Clock Information:
------------------
No clock signals found in this design
Timing Summary:
---------------
Speed Grade: -5
RESULT:
Thus the OUTPUT’s of Multiplexers and Demultiplexers are verified by synthesizing and simulating the
VHDL and VERILOG code.
ALGORITHM:
LOGIC DIAGRAM:
TRUTH TABLE:
BCD GRAY
0000 0000
0001 0001
0010 0011
0011 0010
0100 0110
0101 0111
0110 0101
0111 0100
1000 1100
1001 1101
VHDL SOURCE CODE:
Dataflow Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity b2g_dataflow is
Port ( b : in std_logic_vector(3 downto 0);
g : out std_logic_vector(3 downto 0));
end b2g_dataflow;
architecture dataflow of b2g_dataflow is
begin
g(0)<=b(0) xor b(1);
g(1)<=b(1) xor b(2);
Behavioral Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity b2g_behv is
Port ( b : in std_logic_vector(3 downto 0);
g : out std_logic_vector(3 downto 0));
end b2g_behv;
architecture Behavioral of b2g_behv is
begin
p1:process(b)
begin
g(3)<=b(3);
g(2)<=b(3) xor b(2);
g(1)<=b(2) xor b(1);
g(0)<=b(1) xor b(0);
end process p1;
end Behavioral;
Structural Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity b2g_struct is
Port ( b : in std_logic_vector(3 downto 0);
g : out std_logic_vector(3 downto 0));
end b2g_struct;
architecture structural of b2g_struct is
component xor2
port(a,b:in std_logic;
z:out std_logic);
end component;
component not1
port(a:in std_logic;
z:out std_logic);
end component;
signal p:std_logic;
begin
x1:xor2 port map (b(0),b(1),g(0));
x2:xor2 port map (b(1),b(2),g(1));
x3:xor2 port map (b(2),b(3),g(2));
n1:not1 port map (b(3),p);
n2:not1 port map (p,g(3));
end structural;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity not1 is
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity xor2 is
Port ( a : in std_logic;
b : in std_logic;
z : out std_logic);
end xor2;
architecture dataflow of xor2 is
begin
z<= a xor b;
end dataflow;
Dataflow Modeling:
Behavioral Modeling:
Structural Modeling:
TEST BENCH(VHDL):
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY test_vhd IS
END test_vhd;
tb : PROCESS
BEGIN
b<="0000"; wait for 100ps;
b<="0100"; wait for 100ps;
b<="1000"; wait for 100ps;
END PROCESS;
END;
Simulation output:
=========================================================================
TIMING REPORT
Clock Information:
------------------
No clock signals found in this design
Timing Summary:
---------------
Speed Grade: -5
LOGIC DIAGRAM
TRUTH TABLE:
BCD EXCESS 3
0000 0011
0001 0100
0010 0101
BCD EXCESS 3 0011 0110
0100 0111
0101 1000
0110 1001
VHDL SOURCE CODE: 0111 1010
1000 1011
--Design : BCD TO EXCESS 3 CONVERTER
--Description : To implement BCD TO EXCESS 1001 1100
3CONVERTER
--Author : AMRUTHA V
--Reg no : 2882101
--Version : Xilinx- 7.1i
Dataflow Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bcd2excess_data is
Port ( b : in std_logic_vector(3 downto 0);
e : out std_logic_vector(3 downto 0));
end bcd2excess_data;
architecture dataflow of bcd2excess_data is
signal b0bar,b1bar,b2bar,b3bar,p,q,r,s,t : std_logic;
begin
b0bar<=not b(0);
b1bar<=not b(1);
b2bar<=not b(2);
b3bar<=not b(3);
e(0)<= b0bar ;
e(1)<= b(0) xnor b(1);
p<=b1bar and b0bar;
q<=p and b(2);
r<= b(0) or b(1);
s<= r and b2bar;
e(2)<= q or s;
t<= r and b(2);
e(3)<= t or b(3);
end dataflow;
Behavioral Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bcd2excess_behv is
Structural Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bcd2excess_struct is
Port ( b : in std_logic_vector(3 downto 0);
e : out std_logic_vector(3 downto 0));
end bcd2excess_struct;
architecture structural of bcd2excess_struct is
component not1 is
port(a:in std_logic;z:out std_logic);
end component;
component and2 is
port(a,b:in std_logic;z:out std_logic);
end component;
component or2 is
port(a,b:in std_logic;z:out std_logic);
end component;
component xnor2 is
port(a,b:in std_logic;z:out std_logic);
end component;
signal b0bar,b1bar,b2bar,b3bar,p,q,r,s,t:std_logic;
begin
n1:not1 port map(b(0),b0bar);
n2:not1 port map(b(1),b1bar);
n3:not1 port map(b(2),b2bar);
n4:not1 port map(b(3),b3bar);
e(0)<=b0bar;
x1:xnor2 port map (b(0),b(1),e(1));
a1:and2 port map (b0bar,b1bar,p);
a2:and2 port map (b(2),p,q);
o1:or2 port map(b(0),b(1),r);
a3:and2 port map(r,b2bar,s);
o2:or2 port map (q,s,e(2));
a4:and2 port map (r,b(2),t);
o3:or2 port map(b(3),t,e(3));
end structural;
Dataflow Modeling:
Behavioral Modeling:
Structural Modeling:
TEST BENCH(VHDL):
ENTITY test_vhd IS
END test_vhd;
--Inputs
SIGNAL b : std_logic_vector(3 downto 0) := (others=>'0');
--Outputs
SIGNAL e : std_logic_vector(3 downto 0);
BEGIN
tb : PROCESS
BEGIN
b<="0000"; wait for 100ps;
b<="0101"; wait for 100ps;
b<="1000"; wait for 100ps;
END PROCESS;
END;
Simulation output:
=========================================================================
TIMING REPORT
Clock Information:
------------------
No clock signals found in this design
Timing Summary:
---------------
Speed Grade: -4
4 BIT COMPARATOR:
Behavioral Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity comparator_behv is
Port ( a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
x : out std_logic;
y : out std_logic;
z : out std_logic);
end comparator_behv;
architecture Behavioral of comparator_behv is
begin
p1:process(a,b)
begin
if (a<b) then
x<='1';
y<='0';
z<='0';
elsif (a=b) then
x<='0';
y<='1';
z<='0';
else
x<='0';
y<='0';
z<='1';
end if;
end process p1;
end Behavioral;
Behavioral Modeling:
TEST BENCH(VHDL):
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY test_vhd IS
END test_vhd;
END;
Simulation output:
Synthesis report:
=========================================================================
* Final Report *
========================================================================
=========================================================================
TIMING REPORT
Clock Information:
------------------
No clock signals found in this design
Timing Summary:
---------------
Speed Grade: -5
RESULT:
Thus the OUTPUT’s of Code converters and comparator are verified by synthesizing and simulating the
VHDL and VERILOG code.
ALGORITHM:
Step1: Define the specifications and initialize the design.
Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VERILOG.
Step4: Check the syntax and debug the errors if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the place and route report.
SR FLIPFLOP:
1
Q(t) S R Q(t+1)
S 3 1
2 3 0 0 0 0
2 Q
0 0 1 0
0 1 0 1
CP 0 1 1 X
1 0 0 1
1
1 3
1 0 1 0
3 2 Q 1 1 0 1
2
R 1 1 1 X
Behavioral Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity srff is
Port ( s : in std_logic;
r : in std_logic;
clk : in std_logic;
rst : in std_logic;
q : inout std_logic;
qbar : inout std_logic);
end srff;
architecture Behavioral of srff is
begin
process(s,r,clk,rst,q,qbar)
begin
Behavioral Modeling:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
ENTITY test_vhd IS
END test_vhd;
--Inputs
SIGNAL s : std_logic := '0';
SIGNAL r : std_logic := '0';
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '0';
--BiDirs
SIGNAL q : std_logic;
SIGNAL qbar : std_logic;
BEGIN
tb : PROCESS
BEGIN
clk<='0'; wait for 50ps;
clk<='1'; wait for 50ps;
end process;
rst<='1','0' after 200ps;
tb1:process
begin
s<= '1' , '0' after 400ps;
r<= '1' , '0' after 300ps , '1' after 500ps;
wait for 1ns;
END PROCESS;
END;
Simulation output:
Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : srff.ngr
Top Level Output File Name : srff
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs :6
Macro Statistics :
# Registers :2
# 1-bit register :2
Cell Usage :
# BELS :3
# LUT2 :3
# FlipFlops/Latches :2
# FDCE :1
# FDPE :1
# Clock Buffers :1
# BUFGP :1
=========================================================================
TIMING REPORT
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |2 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -5
JK FLIPFLOP:
1
Q(t) J K Q(t+1)
K 2 9 1
8
2
3
Q 0 0 0 0
0 0 1 0
CP
0 1 0 1
0 1 1 1
1
1
3
1 0 0 1
J
2
8
9 2 Q 1 0 1 0
1 1 0 1
1 1 1 0
Behavioral Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity jkff is
Port ( j : in std_logic;
k : in std_logic;
clk : in std_logic;
rst : in std_logic;
q : inout std_logic;
qbar : inout std_logic);
end jkff;
architecture Behavioral of jkff is
begin
process(j,k,clk,rst,q,qbar)
begin
if (rst='1') then
q<='0';
qbar<='1';
elsif (clk='1' and clk'event) then
if (j='0' and k='0') then
q<=q;
qbar<=qbar;
elsif (j='0' and k='1') then
q<='0';
qbar<='1';
elsif (j='1' and k='0') then
q<='1';
qbar<='0';
else
q<=not q;
qbar<=not qbar;
end if;
end if;
end process;
end Behavioral;
Behavioral Modeling:
TEST BENCH(VHDL):
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY test_vhd IS
END test_vhd;
--Inputs
SIGNAL j : std_logic := '0';
SIGNAL k : std_logic := '0';
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '0';
BEGIN
tb : PROCESS
BEGIN
clk<='0'; wait for 50ps;
clk<='1'; wait for 50ps;
end process;
rst<='1','0' after 200ps;
tb1:process
begin
j<= '1' , '0' after 400ps;
k<= '1' , '0' after 300ps , '1' after 500ps;
wait for 1ns;
END PROCESS;
END;
Simulation output:
Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------
=========================================================================
TIMING REPORT
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |2 |
-----------------------------------+------------------------+-------+
D FLIPFLOP:
CP
0 0 0
1
0 1 1
1
3 2
3
Q 1 0 0
3
1 1 1
Behavioral Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dff is
Port ( d : in std_logic;
clk : in std_logic;
rst : in std_logic;
q : inout std_logic;
qbar : inout std_logic);
end dff;
architecture Behavioral of dff is
begin
process(d,clk,rst,q,qbar)
begin
if (rst='1') then
q<='0';
qbar<='1';
elsif (clk='1' and clk'event) then
if (d='0') then
q<='0';
qbar<='1';
else
q<='1';
qbar<='0';
end if;
end if;
end process;
Behavioral Modeling:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY test_vhd IS
END test_vhd;
--Inputs
SIGNAL d : std_logic := '0';
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '0';
--BiDirs
SIGNAL q : std_logic;
BEGIN
tb : PROCESS
BEGIN
clk<='0'; wait for 50ps;
clk<='1'; wait for 50ps;
end process;
rst<='1','0' after 200ps;
tb1:process
begin
d<= '1' , '0' after 400ps;
wait for 1ns;
END PROCESS;
END;
Simulation output:
Synthesis report:
=========================================================================
* Final Report *
=========================================================================
TIMING REPORT
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |2 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -5
T FLIPFLOP:
Q(t) T Q(t+1)
1
T 2 9 1
8 3
2 Q
0 0 0
CP 0 1 1
1
1
3
1 0 1
2 9 2 Q
8
1 1 0
Behavioral Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tff is
Port ( t : in std_logic;
clk : in std_logic;
rst : in std_logic;
q : inout std_logic;
qbar : inout std_logic);
end tff;
architecture Behavioral of tff is
begin
process(t,clk,rst,q,qbar)
begin
if (rst='1') then
q<='0';
qbar<='1';
elsif (clk='1' and clk'event) then
if (t='0') then
q<=q;
qbar<=qbar;
else
q<=not q;
qbar<=not qbar;
end if;
end if;
end process;
end Behavioral;
VERILOG SOURCE CODE:
Behavioral Modeling:
end
else
begin
q=~q; qbar=~qbar;
end
end
endmodule
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY test_vhd IS
END test_vhd;
--Inputs
SIGNAL t : std_logic := '0';
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '0';
--BiDirs
SIGNAL q : std_logic;
SIGNAL qbar : std_logic;
BEGIN
tb : PROCESS
BEGIN
clk<='0'; wait for 50ps;
clk<='1'; wait for 50ps;
end process;
rst<='1','0' after 200ps;
tb1:process
begin
t<= '1','0' after 400ps;
wait for 1ns;
END PROCESS;
END;
Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------
=========================================================================
TIMING REPORT
Clock Information:
Timing Summary:
---------------
Speed Grade: -5
MASTER-SLAVE SR FLIP-FLOP:
LOGIC DIAGRAM:
Structural Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sr_ms is
Port ( s : in std_logic;
r : in std_logic;
clk : in std_logic;
rst : in std_logic;
q : inout std_logic;
qbar : inout std_logic);
end sr_ms;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity srff is
Port ( s : in std_logic;
r : in std_logic;
clk : in std_logic;
rst : in std_logic;
q : inout std_logic;
qbar : inout std_logic);
end srff;
architecture Behavioral of srff is
begin
process(s,r,clk,rst,q,qbar)
begin
if (rst='1') then
q<='0';
qbar<='1';
elsif (clk='1' and clk'event) then
if (s='0' and r='0') then
q<=q;
qbar<=qbar;
elsif (s='0' and r='1') then
q<='0';
qbar<='1';
elsif (s='1' and r='0') then
q<='1';
qbar<='0';
else
q<='X';
qbar<='X';
end if;
end if;
end process;
end Behavioral;
Structurl modeling:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY test_vhd IS
END test_vhd;
Simulation output:
Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------
=========================================================================
TIMING REPORT
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |4 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -5
RESULT:
Thus the OUTPUT’s of Flip Flops are verified by synthesizing and simulating the VHDL and VERILOG
code.
ALGORITHM:
LOGIC DIAGRAM:
Behavioral Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity reguff is
Port ( d : in std_logic_vector(7 downto 0);
clk : in std_logic;
rst : in std_logic;
q : inout std_logic_vector(7 downto 0);
qbar : inout std_logic_vector(7 downto 0));
end reguff;
architecture Behavioral of reguff is
begin
process(d,clk,rst)
begin
if (clk='1' and clk'event) then
if (rst='1') then
q<="00000000";
qbar<="11111111";
else
Behavioral Modeling:
TEST BENCH(VHDL):
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY test_vhd IS
END test_vhd;
--BiDirs
SIGNAL q : std_logic_vector(7 downto 0);
SIGNAL qbar : std_logic_vector(7 downto 0);
BEGIN
tb : PROCESS
BEGIN
clk <='0'; wait for 50 ps;
clk <='1'; wait for 50 ps;
END PROCESS;
rst <='1','0' after 200 ps;
d<="00010001","00001111" after 400 ps,"11110000" after 600 ps,"11111111" after 800 ps;
END;
Simulation output:
=========================================================================
TIMING REPORT
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 16 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -5
LOGIC DIAGRAM:
Behavioral Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity regulat is
Port ( d : in std_logic_vector(7 downto 0);
rst : in std_logic;
en : in std_logic;
q : inout std_logic_vector(7 downto 0);
qbar : inout std_logic_vector(7 downto 0));
end regulat;
architecture Behavioral of regulat is
begin
process(d,rst,en)
begin
if (rst='1') then
q<="00000000";
qbar<="11111111";
elsif (en='1') then
q<=d;
qbar<=not d;
end if;
end process;
end Behavioral;
Behavioral Modeling:
TEST BENCH(VHDL):
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY test_vhd IS
END test_vhd;
--Inputs
SIGNAL rst : std_logic := '0';
SIGNAL en : std_logic := '0';
SIGNAL d : std_logic_vector(7 downto 0) := (others=>'0');
--BiDirs
SIGNAL q : std_logic_vector(7 downto 0);
SIGNAL qbar : std_logic_vector(7 downto 0);
BEGIN
tb : PROCESS
BEGIN
wait for 1 ns;
END PROCESS;
en<='1','0' after 200 ps, '1' after 300 ps, '0' after 400 ps;
rst<='1','0' after 100 ps;
d<="01010101","11110000" after 100 ps,"11111111" after 200 ps,"00001111" after 300 ps;
END;
Simulation output:
Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
=========================================================================
TIMING REPORT
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
en | BUFGP | 16 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -5
RESULT:
Thus the OUTPUT’s of 8-bit register using flip flops and latches are verified by synthesizing and
simulating the VHDL and VERILOG code.
ALGORITM:
LOGIC DIAGRAM :
Behavioral Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity siso is
Port ( d : in std_logic;
clk : in std_logic;
rst : in std_logic;
q : out std_logic);
end siso;
architecture Behavioral of siso is
signal x:std_logic_vector(7 downto 0);
begin
process(d,clk,rst)
begin
if (rst='1') then
q<='X';
elsif (clk='1' and clk'event) then
x(0)<=d;
x(1)<=x(0);
x(2)<=x(1);
x(3)<=x(2);
Behavioral Modeling:
TEST BENCH(VHDL):
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY test_vhd IS
END test_vhd;
--Inputs
SIGNAL d : std_logic := '0';
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '0';
--Outputs
BEGIN
tb : PROCESS
BEGIN
clk<='1'; wait for 50ps;
clk<='0'; wait for 50ps;
END PROCESS;
rst<='1','0' after 200ps;
d<='1','0' after 1 ns;
END;
Simulation output:
Synthesis Report
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : siso.ngr
Top Level Output File Name : siso
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs :4
Cell Usage :
# BELS :3
# GND :1
# INV :1
# VCC :1
# FlipFlops/Latches :2
# FD :1
# FDE :1
# Shifters :1
# SRL16E :1
# Clock Buffers :1
# BUFGP :1
# IO Buffers :3
# IBUF :2
# OBUF :1
=========================================================================
=========================================================================
TIMING REPORT
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |3 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -5
=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 3.637ns (frequency: 274.963MHz)
Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Delay: 3.637ns (Levels of Logic = 0)
Source: Mshreg_x<7>_srl_0 (FF)
Destination: Mshreg_x<7>_0 (FF)
Source Clock: clk rising
Destination Clock: clk rising
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 3 / 3
-------------------------------------------------------------------------
Offset: 3.144ns (Levels of Logic = 2)
Source: rst (PAD)
Destination: Mshreg_x<7>_0 (FF)
Destination Clock: clk rising
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 6.216ns (Levels of Logic = 1)
Source: q (FF)
Destination: q (PAD)
Source Clock: clk rising
Data Path: q to q
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 1 0.626 0.681 q (q_OBUF)
OBUF:I->O 4.909 q_OBUF (q)
=========================================================================
CPU : 6.88 / 7.56 s | Elapsed : 7.00 / 8.00 s
-->
Place&Route Report
Starting Placer
Phase 1.1
Phase 1.1 (Checksum:989691) REAL time: 3 secs
Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 3 secs
Phase 3.2
.
Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 3 secs
Phase 6.8
.
Phase 6.8 (Checksum:989b6b) REAL time: 3 secs
Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 3 secs
Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 3 secs
Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 3 secs
Starting Router
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| clk_BUFGP | BUFGMUX6| No | 2 | 0.035 | 0.936 |
+---------------------+--------------+------+------+------------+-------------+
INFO:Par:340 -
The Delay report will not be generated when running non-timing driven PAR
with effort level Standard or Medium. If a delay report is required please do
one of the following: 1) use effort level High, 2) use the following
environment variable "XIL_PAR_GENERATE_DLY_REPORT", 3) create Timing
constraints for the design.
Generating Pad Report.
PAR done!
LOGIC DIAGRAM :
Behavioral Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sipo is
Port ( d : in std_logic;
clk : in std_logic;
rst : in std_logic;
q : inout std_logic_vector(7 downto 0));
end sipo;
architecture Behavioral of sipo is
begin
process(d,clk,rst)
begin
if (rst='1') then
Behavioral Modeling:
TEST BENCH(VHDL):
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY test_vhd IS
END test_vhd;
Simulation output:
Synthesis report:
=========================================================================
=========================================================================
TIMING REPORT
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |8 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -5
Behavioral Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pipo is
Port ( d : in std_logic_vector(7 downto 0);
clk : in std_logic;
rst : in std_logic;
q : out std_logic_vector(7 downto 0));
end pipo;
architecture Behavioral of pipo is
begin
process(d,clk,rst)
begin
if (rst='1') then
q<="ZZZZZZZZ";
elsif (clk='1' and clk'event) then
q(0)<=d(0);
q(1)<=d(1);
q(2)<=d(2);
q(3)<=d(3);
q(4)<=d(4);
q(5)<=d(5);
q(6)<=d(6);
q(7)<=d(7);
end if;
end process;
end Behavioral;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY test_vhd IS
END test_vhd;
Simulation output:
Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------
=========================================================================
TIMING REPORT
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
Timing Summary:
---------------
Speed Grade: -5
LOGIC DIAGRAM :
Behavioral Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity piso is
Port ( d : in std_logic_vector(7 downto 0);
clk : in std_logic;
rst : in std_logic;
load : in std_logic;
q : out std_logic);
end piso;
architecture Behavioral of piso is
begin
process(d,clk,rst,load)
variable x:std_logic_vector(7 downto 0);
begin
if (clk='1' and clk'event) then
if (rst='1') then
q<='Z';
else
if (load='0') then
Behavioral Modeling:
TEST BENCH(VHDL):
ENTITY test_vhd IS
END test_vhd;
--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '0';
SIGNAL load : std_logic := '0';
SIGNAL d : std_logic_vector(7 downto 0) := (others=>'0');
--Outputs
SIGNAL q : std_logic;
BEGIN
Simulation output:
Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 11 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -5
RESULT:
Thus the OUTPUT’s of 8-bit shift register are verified by synthesizing and simulating the VHDL and
VERILOG code.
AIM:
To develop the source code for synchronous and asynchronous counter by using VHDL/VERILOG and
obtain the simulation, synthesis, place and route and implement into FPGA.
ALGORITM:
SYNCHRONOUS COUNTER:
LOGIC DIAGRAM:
Structural Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity syncounter is
Port ( clk : in std_logic;
rst : in std_logic;
q : inout std_logic_vector(3 downto 0));
end syncounter;
architecture structural of syncounter is
component tff
port(t,clk,rst:in std_logic;
q,qbar:inout std_logic);
end component;
component and2
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tff is
Port ( t : in std_logic;
clk : in std_logic;
rst : in std_logic;
q : inout std_logic;
qbar : inout std_logic);
end tff;
architecture Behavioral of tff is
begin
process(t,clk,rst,q,qbar)
begin
if (rst='1') then
q<='0';
qbar<='1';
elsif (clk='1' and clk'event) then
if (t='0') then
q<=q;
qbar<=qbar;
else
q<=not q;
qbar<=not qbar;
end if;
end if;
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity and2 is
Port ( a : in std_logic;
b : in std_logic;
z : out std_logic);
end and2;
architecture dataflow of and2 is
begin
z<=a and b;
Behavioral Modeling:
TEST BENCH(VHDL):
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY test_vhd IS
END test_vhd;
--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '0';
--BiDirs
SIGNAL q : std_logic_vector(3 downto 0);
BEGIN
tb : PROCESS
BEGIN
clk<='1'; wait for 50ps;
clk<='0'; wait for 50ps;
END PROCESS;
rst<='1','0' after 100ps;
END;
Simulation output:
Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------
=========================================================================
TIMING REPORT
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |4 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -5
ASYNCHRONOUS COUNTER:
LOGIC DIAGRAM:
Structural Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity asyncounter is
Port ( clk : in std_logic;
rst : in std_logic;
q : inout std_logic_vector(3 downto 0));
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tff is
Port ( t : in std_logic;
clk : in std_logic;
rst : in std_logic;
q : inout std_logic;
qbar : inout std_logic);
end tff;
architecture Behavioral of tff is
begin
process(t,clk,rst,q,qbar)
begin
if (rst='1') then
q<='0';
qbar<='1';
elsif (clk='1' and clk'event) then
if (t='0') then
q<=q;
qbar<=qbar;
else
q<=not q;
qbar<=not qbar;
end if;
end if;
end process;
end Behavioral;
Behavioral Modeling:
TEST BENCH(VHDL):
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY test_vhd IS
END test_vhd;
--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '0';
--BiDirs
SIGNAL q : std_logic_vector(3 downto 0);
BEGIN
tb : PROCESS
BEGIN
clk<='1'; wait for 50ps;
clk<='0'; wait for 50ps;
END PROCESS;
rst<='1','0' after 100ps;
END;
Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------
=========================================================================
TIMING REPORT
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
Timing Summary:
---------------
Speed Grade: -5
RESULT:
Thus the OUTPUT’s of Synchronous and Asynchronous counter are verified by synthesizing and
simulating the VHDL and VERILOG code.
ALGORITM:
MOORE FSM:
LOGIC DIAGRAM:
Behavioral Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity moorefsm is
Port ( a : in std_logic;
clk : in std_logic;
z : out std_logic);
end moorefsm;
architecture Behavioral of moorefsm is
type state_type is (st0,st1,st2,st3);
signal moore_state:state_type;
begin
process(clk)
begin
if (clk='0') then
case moore_state is
when st1=>
z<='0';
if (a='1') then
moore_state<=st3;
end if;
when st2=>
z<='0';
if (a='0') then
moore_state<=st1;
else
moore_state<=st3;
end if;
when st3=>
z<='1';
if (a='1') then
moore_state<=st0;
end if;
end case;
end if;
end process;
end Behavioral;
Behavioral Modeling:
module moorefsm(a,clk,z);
input a;
input clk;
output z;
reg z;
parameter st0=0,st1=1,st2=2,st3=3;
reg[0:1]moore_state;
initial
begin
moore_state=st0;
end
always @ (posedge(clk))
case(moore_state)
st0:
begin
z=1;
if(a)
moore_state=st2;
end
st1:
begin
z=0;
if(a)
st2:
begin
z=0;
if(~a)
moore_state=st1;
else
moore_state=st3;
end
st3:
begin
z=1;
if(a)
moore_state=st0;
end
endcase
endmodule
TEST BENCH(VHDL):
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY test_vhd IS
END test_vhd;
tb : PROCESS
BEGIN
clk<='1'; wait for 50 ps;
clk<='0'; wait for 50 ps;
END PROCESS;
a<='1','0' after 1 ns;
Simulation output:
Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------
=========================================================================
TIMING REPORT
Clock Information:
------------------
Timing Summary:
---------------
Speed Grade: -5
MEALY FSM:
TRUTH TABLE:
Behavioral Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mealyfsm is
Port ( a : in std_logic;
clk : in std_logic;
z : out std_logic);
end mealyfsm;
architecture Behavioral of mealyfsm is
type mealy_type is (st0,st1,st2,st3);
signal pst,nst:mealy_type;
begin
process(clk)
begin
if (clk='0') then
pst<=nst;
when st0=>
if (a='1') then
z<='1';
nst<=st3;
else
z<='0';
end if;
when st1=>
if (a='1') then
z<='0';
nst<=st0;
else
z<='1';
end if;
when st2=>
if (a='1') then
z<='1';
nst<=st1;
else
z<='0';
end if;
when st3=>
z<='0';
if (a='0') then
nst<=st2;
else
nst<=st1;
end if;
end case;
end process p1;
end Behavioral;
Behavioral Modeling:
parameter st0=0,st1=1,st2=2,st3=3;
reg[0:1]mealy_state;
initial
begin
mealy_state=st0;
end
always @ (posedge(clk))
case(mealy_state)
st1:
begin
if(a) begin
z=0;
mealy_state=st0; end
else
z=1;
end
st2:
begin
if(a) begin
z=1;
mealy_state=st1; end
else
z=0;
end
st3:
begin
z=0;
if(a) begin
mealy_state=st1; end
else
mealy_state=st2;
end
endcase
endmodule
TEST BENCH(VHDL):
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY test_vhd IS
END test_vhd;
BEGIN
tb : PROCESS
BEGIN
clk<='1'; wait for 50ps;
clk<='0'; wait for 50ps;
END PROCESS;
a<='1','0' after 1ns;
END;
Simulation output:
=========================================================================
TIMING REPORT
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
_n0009(_n00091:O) | NONE(*)(nst_3) |4 |
clk | BUFGP |4 |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR
resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent
skew problems.
Timing Summary:
---------------
Speed Grade: -5
RESULT:
Thus the OUTPUT’s of Moore and Mealy fsm are verified by synthesizing and simulating the VHDL and
VERILOG code.
ALGORITHM:
Behavioral Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity static_rolling is
Port ( clk : in std_logic;
rst : in std_logic;
a1,a2,a3 : in std_logic_vector(7 downto 0);
stat_roll : in std_logic;
a_out : out std_logic_vector(23 downto 0));
end static_rolling;
architecture Behavioral of static_rolling is
signal count:integer;
begin
process(clk,rst,a1,a2,a3,count)
begin
if(clk='1' and clk'event) then
if(rst='1')then
a_out<=(others=>'0');
count<=0;
else
if(stat_roll='0')then
a_out<=a1 & a2 & a3;
else
count<=count+1;
if(count=3)then
count<=0;
end if;
case count is
when 0=>a_out<=a1&a2&a3;
when 1=>a_out<=a2&a3&a1;
when 2=>a_out<=a3&a1&a2;
Behavioral Modeling:
TEST BENCH(VERILOG):
module static_test_v;
// OUTPUT:s
wire [23:0] a_out;
initial
begin
// Initialize Inputs
clk = 1'b0;rst=1'b1;a_in1=8'haa;a_in2=8'hff;a_in3=8'h00;stat_roll=1'b1;
#15 rst = 1'b0;
#25 stat_roll = 1'b0;
#20 stat_roll = 1'b1;
#15 stat_roll = 1'b0;
// Wait 100 ns for global reset to finish
end
endmodule
Simulation output:
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 58 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -5
RESULT:
Thus the OUTPUT’s of Static and Rolling display are verified by synthesizing and simulating the VHDL
and VERILOG code.
EXP NO: 12 DATE: 18-03-09
ALGORITHM:
LOGIC DIAGRAM:
Behavioral Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity freqdiv1 is
Port (x: in integer range 1 to 31;
clk,rst : in std_logic;
freq_out : inout std_logic);
end freqdiv1;
end Behavioral;
Behavioral Modeling:
TEST BENCH(VERILOG):
module freqdiv_test_v;
// Inputs
reg [3:0] x;
reg clk;
reg rst;
// OUTPUT:s
wire freq_out;
initial begin
rst=1'b1;x=4'd5;clk=1'b0;
#10 rst=1'b0;
#200 x=4'd2;
#100 x = 4'd3;
end
endmodule
Simulation output:
=========================================================================
TIMING REPORT
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 32 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -5
RESULT:
Thus the OUTPUT’s of Frequency Divider are verified by synthesizing and simulating the VHDL and
VERILOG code.
ALGORITM:
LOGIC DIAGRAM:
TRUTH TABLE:
--Design : ALU
--Description : To implement ALU
--Author : AMRUTHA V
--Roll no : 2882101
--Version : Xilinx- 7.1i
Structural Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity alu is
Port ( a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
c : in std_logic;
s : in std_logic_vector(3 downto 0);
y : out std_logic_vector(7 downto 0));
end alu;
architecture structural of alu is
component arith
port(a,b:in std_logic_vector(7 downto 0);
c:in std_logic;
s:in std_logic_vector(2 downto 0);
x:out std_logic_vector(7 downto 0));
end component;
component logic
port(a,b:in std_logic_vector(7 downto 0);
s:in std_logic_vector(2 downto 0);
x:out std_logic_vector(7 downto 0));
end component;
component mux1
port(a,b:in std_logic_vector(7 downto 0);
s:in std_logic;
x:out std_logic_vector(7 downto 0));
end component;
signal x1,x2:std_logic_vector(7 downto 0);
begin
a1:arith port map (a(7 downto 0),b(7 downto 0),c,s(2 downto 0),x1(7 downto 0));
l1:logic port map (a(7 downto 0),b(7 downto 0),s(2 downto 0),x2(7 downto 0));
m1:mux1 port map (x1(7 downto 0),x2(7 downto 0),s(3),y(7 downto 0));
end structural;
Behavioral Modeling:
always @ (a or b or s)
begin
case(s)
4'b0000: y=a;
4'b0001: y=a+1;
4'b0010: y=a-1;
4'b0011: y=b;
4'b0100: y=b+1;
4'b0101: y=b-1;
4'b0110: y=a+b;
4'b0111: y=a+b+cin;
4'b1000: y=~a;
4'b1001: y=~b;
4'b1010: y=a&b;
4'b1011: y=a|b;
4'b1100: y=~(a&b);
4'b1101: y=~(a|b);
4'b1110: y=a^b;
4'b1111: y=~(a^b);
endcase
end
endmodule
TEST BENCH(VHDL)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY test_vhd IS
END test_vhd;
--Inputs
SIGNAL c : std_logic := '0';
SIGNAL a : std_logic_vector(7 downto 0) := (others=>'0');
SIGNAL b : std_logic_vector(7 downto 0) := (others=>'0');
SIGNAL s : std_logic_vector(3 downto 0) := (others=>'0');
--Outputs
SIGNAL y : std_logic_vector(7 downto 0);
BEGIN
tb : PROCESS
BEGIN
a<="10101010";b<="11001100";c<='1';s<="1010"; wait for 300ps;
a<="10101010";b<="11001100";c<='1';s<="1100"; wait for 300ps;
END PROCESS;
END;
Simulation output:
=========================================================================
TIMING REPORT
Clock Information:
------------------
No clock signals found in this design
Timing Summary:
---------------
Speed Grade: -5
RESULT:
Thus the OUTPUT’s of Arithmetic Logic Unit are verified by synthesizing and simulating the VHDL and
VERILOG code.
BARREL SHIFTER
AIM:
To develop the source code for barrel shifter by using VHDL/VERILOG and obtain the simulation,
synthesis, place and route and implement into FPGA.
ALGORITM:
LOGICAL DIAGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bar_shftr is
generic ( n : positive := 7 );
Behavioral Modeling:
if (rst )
aout = 8'd0;
else
begin
if (lr)
aout = a << sft;
else
aout = a >> sft;
end
end
endmodule
TEST BENCH(VERILOG):
module test_v;
// Inputs
reg clk;
reg rst;
reg [7:0] a;
reg [2:0] sft;
reg lr;
// Outputs
wire [7:0] aout;
// Instantiate the Unit Under Test (UUT)
barrel uut (
.aout(aout),
.clk(clk),
.rst(rst),
.a(a),
.sft(sft),
.lr(lr)
Simulation output:
=========================================================================
TIMING REPORT
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |8 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -4
RESULT:
Thus the OUTPUT’s of Barrel Shifter are verified by synthesizing and simulating the VHDL and
VERILOG code.
AIM:
To develop the source code for traffic light controller by using VHDL/VEILOG and obtain the simulation,
place and route and implementation into FPGA.
ALGORITHM:
LOGIC DIAGRAM:
Behavioral Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tflc is
Port ( clk : in std_logic;
rst : in std_logic;
g1,g2,g3,g4 : out std_logic_vector(1 downto 0);
r1,r2,r3,r4 : out std_logic;
y1,y2,y3,y4 : out std_logic);
end tflc;
architecture Behavioral of tflc is
type state is (s1,s2,s3,s4);
signal pst:state;
signal count:integer:=0;
begin
process(clk,rst)
begin
if (clk='1' and clk'event) then
if (rst='1') then
pst<=s1;
else
case pst is
when s1=>
if (count=4) then
y1<='1';y2<='0';y3<='0';y4<='0';
count<=0;
pst<=s2;
else
g1<="11";g2<="00";g3<="00";g4<="10";
r1<='0';r2<='1';r3<='1';r4<='1';
y1<='0';y2<='0';y3<='0';y4<='0';
pst<=s1;
count<=count+1;
end if;
when s2=>
if (count=4) then
y1<='0';y2<='1';y3<='0';y4<='0';
count<=0;
pst<=s3;
else
g1<="10";g2<="11";g3<="00";g4<="00";
r1<='1';r2<='0';r3<='1';r4<='1';
y1<='0';y2<='0';y3<='0';y4<='0';
pst<=s2;
count<=count+1;
end if;
when s3=>
when s4=>
if (count=4) then
y1<='0';y2<='0';y3<='0';y4<='1';
count<=0;
pst<=s1;
else
g1<="00";g2<="00";g3<="10";g4<="11";
r1<='1';r2<='1';r3<='1';r4<='0';
y1<='0';y2<='0';y3<='0';y4<='0';
pst<=s4;
count<=count+1;
end if;
end case;
end if;
end if;
end process;
end Behavioral;
Behavioral Modeling:
module tflc(g1,g2,g3,g4,r1,r2,r3,r4,y1,y2,y3,y4,clk,rst);
output [1:0] g1,g2,g3,g4;
output r1,r2,r3,r4,y1,y2,y3,y4;
input clk;
input rst;
reg [1:0] g1,g2,g3,g4;
reg r1,r2,r3,r4,y1,y2,y3,y4;
parameter st1=0,st2=1,st3=2,st4=3;
reg [0:1] pst;
reg [2:0]count=0;
initial
begin
pst=st1;
end
always @ (posedge(clk) or posedge(rst))
begin
if (rst==1'b1)
pst=st1;
else
case(pst)
st1:
if (count==3'b110) begin
y1=1'b1;y2=1'b0;y3=1'b0;y4=1'b0;
count=3'b000;
pst=st2;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY test_vhd IS
END test_vhd;
tb : PROCESS
BEGIN
clk<='1'; wait for 50ps;
clk<='0'; wait for 50ps;
END PROCESS;
rst<='1','0' after 200ps;
END;
Simulation output:
=========================================================================
TIMING REPORT
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 50 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -5
RESULT:
Thus the OUTPUT’s of Traffic Light Controller are verified by synthesizing and simulating the VHDL and
VERILOG code.
AIM:
To develop the source code for memories by using VHDL/VEILOG and obtain the simulation, place and
route and implementation into FPGA.
ALGORITHM:
BLOCK DIAGRAM:
Behavioral Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity rom is
generic ( bits : integer := 8;
words : integer := 8);
Port ( adder : in integer range o to words-1;
data : out std_logic_vector(bits-1 downto 0));
end rom;
architecture Behavioral of rom is
type vector_array is array(0 to words-1) of std_logic_vector(bits-1 downto 0);
constant memory : vector_array := ("00000000",
"00000010",
"00000100",
"00001000",
"00010000",
"00100000",
"01000000",
"10000000");
begin
data <= memory(addr);
end Behavioral;
Behavioral Modeling:
Simulation output:
Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------
=========================================================================
TIMING REPORT
Clock Information:
------------------
No clock signals found in this design
Timing Summary:
Behavioral Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ram is
generic( bits:integer:=8;
words:integer:=16);
Port ( wr_ena : in std_logic;
clk : in std_logic;
addr : in integer range 0 to words-1;
data_in : in std_logic_vector(bits-1 downto 0);
data_out : out std_logic_vector(bits-1 downto 0));
end ram;
architecture Behavioral of ram is
type vector_array is array (0 to words-1) of std_logic_vector(bits-1 downto 0);
signal memory : vector_array;
begin
process(clk,wr_ena)
begin
if (clk='1' and clk'event) then
if (wr_ena='1') then
memory(addr)<=data_in;
else
data_out<=memory(addr);
end if;
end if;
end process;
end Behavioral;
Behavioral Modeling:
TEST BENCH(VERILOG):
module tst_v;
// Inputs
reg clk;
reg wr_en;
reg [7:0] data_in;
reg [3:0] addr;
// Outputs
wire [7:0] data_out;
// Instantiate the Unit Under Test (UUT)
ram uut (
.clk(clk),
.wr_en(wr_en),
.data_in(data_in),
.addr(addr),
.data_out(data_out)
);
always
#5 clk=~clk;
initial
begin
// Initialize Inputs
clk = 1'b1;
data_in = 8'ha0;
addr = 5'd0;
wr_en = 1'b1;
#10 wr_en=1'b0;
end
endmodule
Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Device utilization summary:
---------------------------
Clock Information:
-----------------------------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |1 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -5
RESULT:
Thus the OUTPUT’s of ROM and RAM are verified by synthesizing and simulating the VHDL and
VERILOG code.
ALGORITHM
BLOCK DIAGRAM:
--Design : MAC
--Description : To implement MAC
--Author : AMRUTHA V
--Roll no : 2882101
--Version : Xilinx- 7.1i
Behavioral Modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL
entity mac is
Port ( a : in integer range 0 to 7 ;
begin
process(rst,clk)
begin
if(rst='1') then
addr<=0;
elsif (clk='1' and clk'event) then
areg<=integer(a);
breg<=integer(b);
prod<=areg*breg;
addr<=addr + prod;
end if;
end process;
acc<=integer(addr);
end Behavioral;
Behavioral Modeling:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY testmac_vhd IS
END testmac_vhd;
--Inputs
SIGNAL rst : std_logic := '0';
SIGNAL clk : std_logic := '0';
SIGNAL a : integer range 0 to 7;
SIGNAL b : integer range 0 to 7;
--Outputs
SIGNAL acc : integer range 0 to 50;
BEGIN
tb : PROCESS
BEGIN
clk<='1'; wait for 5 ns;
clk<='0'; wait for 5 ns;
-- Wait 100 ns for global reset to finish
--wait for 100 ns;
Synthesis report
=========================================================================
* Final Report *
=========================================================================
=========================================================================
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 13 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -5
RESULT:
Thus the OUTPUT’s of MAC Unit are verified by synthesizing and simulating the VHDL and VERILOG
code.
ALGORITM:
INVERTER:
LOGIC DIAGRAM:
TRUTH TABLE:
A Y=A’
0 1
1 0
--Design : INVERTER
--Description : To implement INVERTER
--Author : AMRUTHA V
--Roll no : 2882101
--Version : Xilinx- 7.1i
Simulation output:
LOGIC DIAGRAM:
TRUTH TABLE:
A B Y=(A+B)’
0 0 1
0 1 0
1 0 0
1 1 0
OR GATE:
A B Y=(A+B)
0 0 0
0 1 1
1 0 1
1 1 1
--Design : OR GATE
--Description : To implement OR GATE
--Author : AMRUTHA V
--Roll no : 2882101
--Version : Xilinx- 7.1i
Simulation output:
NAND GATE:
LOGIC DIAGRAM:
TRUTH TABLE:
A B Y=(AB)’
0 0 1
0 1 1
1 0 1
1 1 0
Simulation output:
AND GATE:
LOGIC DIAGRAM:
TRUTH TABLE:
A B Y=AB
0 0 0
0 1 0
1 0 0
1 1 1
Simulation output:
XOR GATE:
A B
0 0 0
0 1 1
1 0 1
1 1 0
Simulation output:
HALF ADDER:
LOGIC DIAGRAM:
TRUTH TABLE:
A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Simulation output:
HALF SUBTRACTOR:
A B DIFFERENCE BORROW
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Simulation output:
A B C SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Simulation output:
LOGIC DIAGRAM:
TRUTH TABLE:
A B C DIFFERENCE BORROW
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Simulation output:
RESULT:
Thus the OUTPUT’s of switchlevel design basic logic gates, adders and substractors are verified and
simulated using the VERILOG code.