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AF4001

AF4001 OC-3/STM-1 EoE1oSDH Framer-Mapper

Rev. 1.0 – Sep 2010 Preliminary Short Data Sheet

GENERAL DESCRIPTION
The AF4001 provides a Ethernet over E1 over SONET/SDH mapping. The 63 E1s frame can be mapped to VT2/TU12 to SONET/SDH transport.
The chip supports a Dual OC-3/STM-1 SONET/SDH interface with 1+1/1:1 Linear APS protection or UPSR/SNCP protection. On the Ethernet
side, the chip provides 2 (1+1 protection) Ethernet/Fast Ethernets via SMII/SS-SMII interface. The AF4001 supports PPP/HDLC/LAPS and GFP
encapsulation with up to 63 channels. A MAC-Learning/Aging Engine using Hash Table to do forwarding function for packets received from
Ethernet lines.

KEY FEATURES APPLICATIONS


 Two 10/100Mpbs Ethernet ports via SMII/SS-SMII  Ethernet over E1 over SONET/SDH Pizza Box with E/FE/GE Interface
 Dual OC-3/STM-1 ports with on-chip CDR  Ethernet over E1 over SONET/SDH Line Card with E/FE/GE
 Ethernet MAC controller with flow control as 802.3x Interface
 OAM and statistical counters: Byte counters and Frame
counters Per Port and Queue
 PPP/HDLC/ LAPS and GFP encapsulation
 63 E1 unframe, basic frame or CRC-4 multi-frame
SONET/SDH SMII/
framers Dual SFP CDR Interface SS-SMII Ethernet 2x10/100
Ethernet
 Mapping of 63 E1 to SONET/SDH OC-3/
STM-1
Optical
AF4001
PHY
Module
 2x16Mx16 DDR2 SDRAM for packet buffer UPSR, 1+1

 FPGA package size 23x23mm 484-Pin FBGA


 Power consumption less than 3.5W

Packet
DDR2
SDRAM

AF4004 BLOCK DIAGRAM


BITS Timing 1-Wire Host CPU Bus JTAG

Clock Key uP JTAG


Synthesizer Management interface Interface

2 x Serial 2 x Rx 2xSTS-3
155.52Mbps OC-3/STM-1 HO/LO
SerDes Two Pointer Processor
SONET/SDH
63
Framer Alarm 63
E1 E1
Monitor TU12/VC12
Tx/Rx Alarm
Transport Map/DeMap
Framer
Overhead
2 x Tx Processor 2xSTS-3
2 x Serial
155.52Mbps OC-3/STM-1 HO/LO
SerDes Pointer Generator
STS/AU PDH Sub-system
VT/TU
Multi-Level
Path Cross-Connect
1+1/1:1 UPSR BER 63
Overhead MAC
HW-APS HW-APS Monitor PPP/HDLC 2xE/FE
Termination Learning/ MAC SMII/
LAPS/GFP 10/100Mbps
Aging Controller SS-SMII
Encapsulation 1+1
APS Processor POH Processor Processor
SONET/SDH Sub-system

Packet
RMON
OH CMF/OAM DDR2 MDIO
Data Link Statistic
Drop/Insert Buffer SDRAM Interface
Controller Counters
Bus Controller
Packet Sub-system

OH Access Data Link Access


2x16-Bit@DDR2
SDRAM

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AF4001
AF4001 OC-3/STM-1 EoE1oSDH Framer-Mapper

Rev. 1.0 – Sep 2010 Preliminary Short Data Sheet

FEATURES SUMMARY
Ethernet MAC SONET/SDH
 Provide up to 2 MAC Controllers for Ethernet/Fast Ethernet  Built-in 2 OC-3/STM-1 Framers
framing in compliant with IEEE 802.3  Full SONET/SDH Section/Line Overhead processing
 Support port-based flow control as 802.3x. The received flow  Hardware based APS processing for Linear and UPSR
control frame from Ethernet line is bypassed/discarded to SONET  Full Hi-order and Lo-order Path monitoring/termination
transparently
 Full SONET/SDH Line 10-3 to 10-9 hardware BER detection
 Rate limiting based Rx Ethernet FIFO
 Full Hi-order and Lo-order with 10-3 to 10-9 hardware BER
 Jumbo frame support up to 9Kbyte detection
 MAC Counters for Ethernet Statistics as RFC2819
 Optional FCS Insertion at Transmit Ethernet MAC
STS/AU/VT/TU Cross Connect
 Full non-blocking Cross-connect for STS-1/VC-3/VT/TU
 Ethernet serial loop back out and/or parallel loop back in for
diagnostic
MAC-Learning & Management
 Support 512 MAC address table PDH Features
 Automatic SA based learning using Hash function  Integrates 63 E1 framers source from VT/TU Map/DeMap
 Automatic Aging. Aging enable/disable by microprocessor  Provide unframe, basic and CRC-4 framing mode
 Forwarding packet to SONET/SDH based on MAC DA  Provide full error, alarm and performance counters for E1
 Support up to 8 collision MAC address per Hash key maintenance
 Support multicast/broadcast for MAC learning only  Implements bit asynchronous mapping of 63 E1 to VT2/TU12
 Support MAC filter for remote loop back applications  Asynchronous E1 to VT/TU Map with Jitter Attenuation
 Provide up to 126 queues for data packet  Extraction/Insertion Sa bits for Data Link processor
 Support performance counters per queue as RFC2819  Support local line loop back and remote line loop back for
diagnostic
Data Encapsulation System Clock Synthesizer
 PPP/HDLC/LAPS and GFP simultaneously, full-duplex 63 channels
 Accepts the multiple of 8KHz input reference clock and monitor
 PPP/HDLC/LAPS and GFP mapping to E1 in compliance with clock
G.8040, RFC1638, X.86
 Complies with ITU-T G.7041 (GFP), RFC-1619/1662/2615 (PPP),
 Accepts an 8KHz or 1.544MHz/2.048MHz input reference clock
and an 8KHz or 1.544MHz/2.048MHz input monitored clock
ITU-T X.86 (LAPS) mapping standards
 Core HEC and packet FCS checker/generator and 1-bit Core HEC
 Selectable clock reference and clock monitoring from SONET/SDH
Line or Hi-order or Lo-order path
error correction
 Aborted sequence detection/generation
 Supports Free-run, Locked, and Holdover modes of operation
 Packet Payload scrambling/de-scrambling
 Supports working/protection clock synchronization with multi-
frame phase accuracy of 6.43ns
 Bit stuffing and byte stuffing on PPP
 Supports rate adaptation for LAPS/PPP Datalink Controller
 Extraction and insertion header field support  64 standard HDLC channels
 Supports frame extraction and Insertion  E1 FDL from PDH framers
 DCC bytes from SONET/SDH framers
 Bit-oriented Message and Facility Data Link from PDH framers
 Flexible datalink buffer setup and management significantly
offloading host processor from real time demands from the large
channel count
Please contact sales@arrivetechnologies.com for further information

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