`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:43:54 04/08/11
// Design Name:
// Module Name: april81
// Project Name:
// Target Device:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////

module april81(finalop1,finalop2,finalop3,op,C,Z,S,P,clk0,wr,iren,rst0,address,d
atain,
enb,ip1,ip);

output [63:0] finalop1;

output [63:0] finalop2;
output [1:0] finalop3;
output C,Z,S,P;
output op;
input clk0,wr,iren,rst0;
input [11:0] address;
input [63:0] datain;
input enb;
input [39:0] ip1;
input ip;

wire [63:0] memout,memout1,memout2;

wire [39:0] out1;
wire [11:0] out2,out3;
wire [63:0] op1;
wire [63:0] ot1,op2;
wire read1,read2;

assign finalop1 = ot1;

assign finalop2 = op2;
assign finalop3 = op;

control_unit control(//input
.clock(clk0),
.reset(rst0),
.OpCode(ip1),
.Grant(ip),
//output
 .NextState(op),
.IRInEn(iren),
.wr(wrt),
.read1(read1),
.read2(read2),
.en(enb)
);
IR instruction_register (//input
.clock(clk0),
.reset(rst0),
.irinen(iren),
.irdatain(memou
t),
//output
.opcodeout(out1
),
.operandout1(ou
t2),
.operandout2(ou
t3)
);
memsite memory (//input
.clk(clk0),
.we(wr),
.addr(address),
.din(datain),
//output
.dout(memout));
memsite memory1 (//input
.clk(clk0),
.we(read1),
.addr(out2),
.din(datain),
//output
.dout(memout1));
memsite memory2 (//input
.clk(clk0),
.we(read2),
.addr(out3),
.din(datain),
//output
.dout(memout2));

alu40 arithmetic_logic (//input

.clock_f(clk0),
.selection(out1)
,
.reset_f(rst0),
.enable_f(enb),
.in1(memout1),
.in2(memout2),
//output
.out1(op1),
.out2(op2),
 .carry(C),
.zero(Z),
.parity(P),
.sign(S))
;
acc accumulator (//input
.clock(clk0),
.reset(rst0),
.accdatain(op1),
.accen(enb),
//output
.accdataout(ot1));
//PC program_counter (//input
// .clock(clk0),
// .reset(rst0),
// .pcinen(pcin),
// .pcdatain(out2),
// //output
// .pcdataout(out)
// );

endmodule

module memsite (
input clk,
input we,
input [11:0] addr,
input [63:0] din,
output reg [63:0] dout
);
reg [63:0] ram0 [0:4095];
parameter B=12'b000000000000;
parameter C=12'b111111111111;
//parameter D=12'b111111111101;
reg we_r;
reg [11:0] addr_r;
reg [63:0] din_r, dout_r0, dout_r1;
//assign dout = dout_r1;
always @(posedge clk) begin
we_r <= we;
addr_r <= addr;
din_r <= din;
dout <= dout_r1;
end
always @(posedge clk) begin
if (we_r) begin //write data
ram0[addr_r] <= din_r;
 //dout_r1 <= din_r;
end
else //read data
dout_r0 <= ram0[addr_r];
dout_r1 <= dout_r0;
end
always @ (posedge clk)
begin
ram0[B] <= 64'b111111111111111111111111111111_000000000000000000000000000000_111
1;
ram0[C] <= 64'b000000000000000000000000000000_111111111111111111111111111111_000
0;
end
endmodule

module IR(clock,reset,irdatain,irinen,operandout1,operandout2,opcodeout);
parameter datawidth=64;
parameter addrwidth=12;
parameter opcodewidth=40;
output [addrwidth-1:0] operandout1;
output [addrwidth-1:0] operandout2;
output [opcodewidth-1:0] opcodeout;
input clock,reset,irinen;
input [datawidth-1:0] irdatain;
reg [addrwidth-1:0] operandout1;
reg [addrwidth-1:0] operandout2;
reg [opcodewidth-1:0] opcodeout;

always @ (posedge reset, negedge clock)

begin
if (reset==1'b1)
begin
operandout1<=12'b0;
operandout2<=12'b0;
opcodeout<=40'b0;
end
else if (irinen==1'b1)
begin
opcodeout<=irdatain[39:0];
operandout1<=irdatain[51:40];
operandout2<=irdatain[63:52];
end
else
begin
operandout1<=operandout1;
operandout2<=operandout2;
opcodeout<=opcodeout;
end
end
endmodule
module alu40 (out1,out2,carry,zero,parity,sign,mantissa,exponent,clock_f,selecti
on,enable_f,reset_f,in1,in2);

output [63:0] out1,out2;

output carry,zero,sign,parity;
output [55:0] mantissa;
output [10:0] exponent;
input [63:0] in1,in2;
input clock_f,enable_f,reset_f;
input [39:0] selection;

top a1 (.z(out1),.m(out2),.c1(carry),.z1(zero),.p1(parity),.sign_f(sign),.mantis
sa_f(mantissa),.exponent_f(exponent),.clock(clock_f),.s(selection),.enable(enabl
e_f),.reset(reset_f),.x(in1),.y(in2));
endmodule
module top (z,m,c1,z1,p1,sign_f,mantissa_f,exponent_f,clock,s,enable,reset,x,y);

output [63:0] z,m;

output c1;
output z1,p1;
output sign_f;
output [55:0] mantissa_f;
output [10:0] exponent_f;
input [63:0] x,y;
input clock,enable,reset;
input [39:0] s;
reg [39:0] s_reg;
reg [63:0] opa_reg,opb_reg,z,m;
wire [63:0] and_out,or_out,xor_out,sl_out,sr_out,inc_out,dec_out,rrc_out,
rlc_out,comp_out,lxi_out1,lxi_out2,mov_out,mvi_out,rr_out,
rl_out;
wire carry1,carry2,carry3,carry4,carry5,carry6,zero1,zero2,carry7,zero3;
reg sign_f;
reg [55:0] mantissa_f;
reg [10:0] exponent_f;
reg z1;
reg c1,p1;
wire sign,sign1,sign2;
wire [55:0] mantissa,mantissa1,mantissa2;
wire [10:0] exponent,exponent1,exponent2;
 always @ (posedge clock)
begin
if(reset)
begin
opa_reg <= 0;
opb_reg <= 0;
s_reg <= 0;
end
else if (enable)
begin
opa_reg <= x;
opb_reg <= y;
s_reg <= s;
end
end

always @ (clock)
begin
case(s_reg)
40'b0000000000_0000000000_0000000000_0000000000 : z<= and_out;
40'b0000000000_0000000000_0000000000_0000000001 : z<= or_out;
40'b0000000000_0000000000_0000000000_0000000010 : z<= xor_out;
40'b0000000000_0000000000_0000000000_0000000011 : z<= sl_out;
40'b0000000000_0000000000_0000000000_0000000100 : z<= sr_out;
40'b0000000000_0000000000_0000000000_0000000101 : z<= inc_out;
40'b0000000000_0000000000_0000000000_0000000110 : z<= dec_out;
40'b0000000000_0000000000_0000000000_0000000111 : z<= rrc_out;
40'b0000000000_0000000000_0000000000_0000001000 : z<= rlc_out;
40'b0000000000_0000000000_0000000000_0000001001 : z<= comp_out;
40'b0000000000_0000000000_0000000000_0000010000 : z<= lxi_out1;
40'b0000000000_0000000000_0000000000_0000010001 : z<= mov_out;
40'b0000000000_0000000000_0000000000_0000010010 : z<= mvi_out;
40'b0000000000_0000000000_0000000000_0000010111 : z<= rr_out;
40'b0000000000_0000000000_0000000000_0000011000 : z<= rl_out;
//default : z<=64'b0;
endcase
end

always @ (clock)
begin
case(s_reg)
40'b0000000000_0000000000_0000000000_0000010000 : m<= lxi_out2;
40'b0000000000_0000000000_0000000000_0000010010 : m<= mvi_out;
default : m<= 64'b0;
endcase
end
always @ (clock)
begin
case(s_reg)
 40'b0000000000_0000000000_0000000000_0000000101 : c1<= carry1;
40'b0000000000_0000000000_0000000000_0000000111 : c1<= carry2;
40'b0000000000_0000000000_0000000000_0000001000 : c1<= carry3;
40'b0000000000_0000000000_0000000000_0000001010 : c1<= carry4;
//5'b01011 : c1<= carry5;
40'b0000000000_0000000000_0000000000_0000001100 : c1<= carry6;
40'b0000000000_0000000000_0000000000_0000001111 : c1<= carry7;
//default : c1<=1'b0;
endcase
end

//always @ (clock)
//begin
//case(s_reg)
//5'b01101 : z1<= zero1;
//5'b01110 : z1<= zero2;
//5'b01111 : z1<= zero3;
//default : z1<= 1'b0;
//endcase
//end

always @ (clock)
begin
case(s_reg)
40'b0000000000_0000000000_0000000000_0000010101 : mantissa_f<= mantissa;
40'b0000000000_0000000000_0000000000_0000010110 : mantissa_f<= mantissa1;
40'b0000000000_0000000000_0000000000_0000011001 : mantissa_f<= mantissa2;
endcase
end
always @ (clock)
begin
case(s_reg)
40'b0000000000_0000000000_0000000000_0000010101 : exponent_f <=exponent;
40'b0000000000_0000000000_0000000000_0000010110 : exponent_f <=exponent1;
40'b0000000000_0000000000_0000000000_0000011001 : exponent_f <=exponent2;
endcase
end
//parity
always @ (s_reg)
begin
p1=^~z;
end
//zero flag
always @ (s_reg)
begin
if(z==64'b0)
z1<=1'b1;
else
z1<=1'b0;
end
//sign flag
always @ (clock)
 begin
case(s_reg)
40'b0000000000_0000000000_0000000000_0000000000 : sign_f<= and_out[63];
40'b0000000000_0000000000_0000000000_0000000001 : sign_f<= or_out[63];
40'b0000000000_0000000000_0000000000_0000000010 : sign_f<= xor_out[63];
40'b0000000000_0000000000_0000000000_0000000011 : sign_f<= sl_out[63];
40'b0000000000_0000000000_0000000000_0000000100 : sign_f<= sr_out[63];
40'b0000000000_0000000000_0000000000_0000000101 : sign_f<= inc_out[63];
40'b0000000000_0000000000_0000000000_0000000110 : sign_f<= dec_out[63];
40'b0000000000_0000000000_0000000000_0000000111 : sign_f<= rrc_out[63];
40'b0000000000_0000000000_0000000000_0000001000 : sign_f<= rlc_out[63];
40'b0000000000_0000000000_0000000000_0000001001 : sign_f<= comp_out[63];
//5'b01010 : sign_f<= setc_out[63];
//5'b01011 : sign_f<= [63];
//5'b01101 : sign_f<= z[63];
//5'b01110 : sign_f<= z[63];
//5'b01111 : sign_f<= z[63];
40'b0000000000_0000000000_0000000000_0000010000 : sign_f<= lxi_out1[63];
40'b0000000000_0000000000_0000000000_0000010001 : sign_f<= mov_out[63];
40'b0000000000_0000000000_0000000000_0000010010 : sign_f<= mvi_out[63];
//5'b10011 : sign_f<= z[63];
//5'b10100 : sign_f<= z[63];
40'b0000000000_0000000000_0000000000_0000010101 : sign_f<= sign;
40'b0000000000_0000000000_0000000000_0000010110 : sign_f<= sign1;
40'b0000000000_0000000000_0000000000_0000010111 : sign_f<= rr_out[63];
40'b0000000000_0000000000_0000000000_0000011000 : sign_f<= rl_out[63];
40'b0000000000_0000000000_0000000000_0000011001 : sign_f<= sign2;
endcase
end

AND r1 (.c(and_out),.a(opa_reg),.b(opb_reg));
OR r2 (.c(or_out),.a(opa_reg),.b(opb_reg));
XOR r3 (.c(xor_out),.a(opa_reg),.b(opb_reg));
SL r4 (.c(sl_out),.a(opa_reg),.b(opb_reg));
SR r5 (.c(sr_out),.a(opa_reg),.b(opb_reg));
INC r6 (.c(inc_out),.carry(carry1),.a(opa_reg));
DEC r7 (.c(dec_out),.a(opa_reg));
RRC r8 (.c(rrc_out),.carry(carry2),.a(opa_reg));
RLC r9 (.c(rlc_out),.carry(carry3),.a(opa_reg));
COMP r10 (.c(comp_out),.a(opa_reg));
SETC r11 (.carry(carry4),.clock(clock));
//COMPC r12 (.carry(carry5),.clock(clock));
RESETC r13 (.carry(carry6),.clock(clock));
RESETZ r14 (.zero(zero1),.clock(clock));
SETZ r15 (.zero(zero2),.clock(clock));
CAMP r16 (.carry(carry7),.zero(zero3),.a(opa_reg),.b(opb_reg));
LXI r17 (.c(lxi_out1),.d(lxi_out2),.a(opa_reg),.b(opb_reg),.clock(clock));
MOV r18 (.c(mov_out),.clock(clock),.a(opa_reg));
MVI r19 (.d(mvi_out),.clock(clock),.a(opa_reg));
//NOPE r20 (.clock(clock));
//HALTE r21 (.clock(clock));
ADD r22 (.sign1(sign),.sum_2(mantissa),.exponent_2(exponent),.clock(clock),.rese
t(reset),.enable(enable),.opa(opa_reg),.opb(opb_reg));
SUB r23 (.clock(clock),.reset(reset),.enable(enable),.opa(opa_reg),.opb(opb_reg)
,.sign2(sign1),.diff_3(mantissa1),.exponent_3(exponent1));
RR r24 (.c(rr_out),.a(opa_reg));
RL r25 (.c(rl_out),.a(opa_reg));
MUL r26 (.clk(clock),.rst(reset),.enable(enable),.opa(opa_reg),.opb(opb_reg),.si
gn(sign2),.product_7(mantissa2),.exponent_5(exponent2));
endmodule

// [1] and operation

module AND(c,a,b);
output [63:0] c;
input [63:0] a,b;
assign c = a & b;
endmodule

// [2] or operation
module OR (c,a,b);
output [63:0] c;
input [63:0] a,b;
assign c = a | b;
endmodule

//[3] xor operation

module XOR (c,a,b);
output [63:0] c;
input [63:0] a,b;
assign c = a ^ b;
endmodule

//[4] shift left

module SL(c,a,b);
output [63:0] c;
input [63:0] a,b;
reg [63:0] c;
always @ (a,b)
begin
c = a<<1;
end
endmodule

// [5] right shift

module SR(c,a,b);
output [63:0] c;
input [63:0] a,b;
reg [63:0] c;
always @ (a,b)
begin
c = a>>1;
end
endmodule

// [6] inc by 1
module INC (c,carry,a);
output [63:0] c;
input [63:0] a;
output carry;
reg carry;
reg [64:0] d;
reg [63:0] c;
always @ (a)
begin
d = a+1;
carry <= d[64];
c<=d[63:0];
end
endmodule

// [7] dec by 1
module DEC(c,a);
output [63:0] c;
input [63:0] a;
assign c = a-1;
endmodule

// // [8] rotate right with 1

module RRC (c,carry,a);
output [63:0] c;
input [63:0] a;
reg [63:0] c,d;
output carry;
reg carry;

always @ (a)
begin
carry <= a[0];
c[63]=a[0];
d=a>>1;
c[62:0]=d[62:0];
end
endmodule
// [9] rotate left with 1
module RLC (c,carry,a);
output [63:0] c;
output carry;
input [63:0] a;
reg [63:0] c,d;
reg carry;

always @ (a)
begin
carry <= a[63];
c[0] = a[63];
d =a<<1;
c[63:1]=d[63:1];
end
endmodule

// [10] complement accumulator

module COMP (c,a);
output [63:0] c;
input [63:0] a;
assign c = ~ a;
endmodule

// [11] set carry

module SETC (carry,clock);
input clock;
inout carry;
assign carry = 1'b1;
endmodule

// // [12] complement carry

//module COMPC (carry,clock);
//input clock;
//output carry;
//reg carry;
//always @ (posedge clock)
//begin
//assign carry = ~ carry;
//end
//endmodule
//[13] reset carry
module RESETC (carry,clock);
input clock;
inout carry;
assign carry = 1'b0;
endmodule

//
// //[14] reset zero
module RESETZ (zero,clock);
input clock;
inout zero;
assign zero = 1'b0;
endmodule

//[15] set zero

module SETZ (zero,clock);
input clock;
inout zero;
assign zero = 1'b1;
endmodule

//
//
//
//
//
// // [16] compare with accumulator
module CAMP (carry,zero,a,b);
input [63:0] a;
input [63:0] b;
output zero,carry;
reg zero,carry;
always @ (a)
begin
if (b>a)
begin
carry=0;
zero=0;
end
else if (b==a)
begin
carry=0;
zero=1;
end
else
begin
carry=1;
zero=0;
end
end
endmodule

//
//// [16] lxi instruction(load register pair immediately)
module LXI (c,d,a,b,clock);
input [63:0] a,b;
output [63:0] c,d;
reg [63:0] c,d;
input clock;
always @ (a,b)
begin
c<=a;
d<=b;
end
endmodule

//
//
//// [17] mov operation-copy from source to destination
module MOV (c,clock,a);
output [63:0] c;
reg [63:0] c;
input clock;
input [63:0] a;
always @ (posedge clock)
begin
c=a;
end
endmodule

//
// // [18] mvi operation-copydirect data to reg
module MVI (d,clock,a);
output [63:0] d;
reg [63:0] d;
input [63:0] a;
input clock;
always @ (posedge clock)
begin
d=a;
end
endmodule

//// [19] no operation

//module NOPE (clock);
//input clock;

//always @ (posedge clock)

//begin
//end
//endmodule

// [20] halt operation

//module HALTE (clock);
//input clock;
//always @ (posedge clock)
//begin
//$display("HALT OPERATION");
//end
//endmodule

// // [21] addition
//
module ADD ( clock, reset, enable, opa, opb, sign1, sum_2, exponent_2);
input clock;
input reset;
input enable;
input [63:0] opa, opb;
output sign1;
output [55:0] sum_2;
output [10:0] exponent_2;
reg sign1;
reg [10:0] exponent_a;
reg [10:0] exponent_b;
reg [51:0] mantissa_a;
reg [51:0] mantissa_b;
reg expa_gt_expb;
reg [10:0] exponent_small;
reg [10:0] exponent_large;
reg [51:0] mantissa_small;
reg [51:0] mantissa_large;
reg small_is_denorm;
reg large_is_denorm;
reg large_norm_small_denorm;
reg [10:0] exponent_diff;
reg [55:0] large_add;
reg [55:0] small_add;
reg [55:0] small_shift;
wire small_shift_nonzero = |small_shift[55:0];
wire small_is_nonzero = (exponent_small > 0) | |mantissa_small[51:0];
wire small_fraction_enable = small_is_nonzero & !small_shift_nonzero;
wire [55:0] small_shift_2 = { 55'b0, 1'b1 };
reg [55:0] small_shift_3;
reg [55:0] sum;
wire sum_overflow = sum[55]; // sum[55] will be 0 if there was no carry from a
dding the 2 numbers
reg [55:0] sum_2;
reg [10:0] exponent;
wire sum_leading_one = sum_2[54]; // this is where the leading one resides, un
less denorm
reg denorm_to_norm;
reg [10:0] exponent_2;
always @(posedge clock)
begin
if (reset) begin
sign1 <= 0;
exponent_a <= 0;
exponent_b <= 0;
mantissa_a <= 0;
mantissa_b <= 0;
expa_gt_expb <= 0;
exponent_small <= 0;
exponent_large <= 0;
mantissa_small <= 0;
mantissa_large <= 0;
small_is_denorm <= 0;
large_is_denorm <= 0;
large_norm_small_denorm <= 0;
exponent_diff <= 0;
large_add <= 0;
small_add <= 0;
small_shift <= 0;
small_shift_3 <= 0;
sum <= 0;
sum_2 <= 0;
exponent <= 0;
denorm_to_norm <= 0;
exponent_2 <= 0;
end
else if (enable) begin
sign1 <= opa[63];
exponent_a <= opa[62:52];
exponent_b <= opb[62:52];
mantissa_a <= opa[51:0];
mantissa_b <= opb[51:0];
expa_gt_expb <= exponent_a > exponent_b;
exponent_small <= expa_gt_expb ? exponent_b : exponent_a;
exponent_large <= expa_gt_expb ? exponent_a : exponent_b;
mantissa_small <= expa_gt_expb ? mantissa_b : mantissa_a;
mantissa_large <= expa_gt_expb ? mantissa_a : mantissa_b;
small_is_denorm <= !(exponent_small > 0);
large_is_denorm <= !(exponent_large > 0);
large_norm_small_denorm <= (small_is_denorm && !large_is_denorm);
exponent_diff <= exponent_large - exponent_small - large_norm_small_
denorm;
large_add <= { 1'b0, !large_is_denorm, mantissa_large, 2'b0 };
small_add <= { 1'b0, !small_is_denorm, mantissa_small, 2'b0 };
small_shift <= small_add >> exponent_diff;
small_shift_3 <= small_fraction_enable ? small_shift_2 : small_shift
;
sum <= large_add + small_shift_3;
sum_2 <= sum_overflow ? sum >> 1 : sum;
exponent <= sum_overflow ? exponent_large + 1: exponent_large;
denorm_to_norm <= sum_leading_one & large_is_denorm;
exponent_2 <= denorm_to_norm ? exponent + 1 : exponent;
end
end
endmodule

//
//
// // [21] subtraction
//
module SUB ( clock, reset, enable, opa, opb, sign2, diff_3, exponent_3);
input clock;
input reset;
input enable;
input [63:0] opa, opb;
output sign2;
output [55:0] diff_3;
output [10:0] exponent_3;
reg [6:0] diff_shift;
reg [6:0] diff_shift_2;

reg [10:0] exponent_a;

reg [10:0] exponent_b;
reg [51:0] mantissa_a;
reg [51:0] mantissa_b;
reg expa_gt_expb;
reg expa_et_expb;
reg mana_gtet_manb;
reg a_gtet_b;
reg sign2;
reg [10:0] exponent_small;
reg [10:0] exponent_large;
reg [51:0] mantissa_small;
reg [51:0] mantissa_large;
reg small_is_denorm;
reg large_is_denorm;
reg large_norm_small_denorm;
reg small_is_nonzero;
reg [10:0] exponent_diff;
reg [54:0] minuend;
reg [54:0] subtrahend;
reg [54:0] subtra_shift;
wire subtra_shift_nonzero = |subtra_shift[54:0];
wire subtra_fraction_enable = small_is_nonzero & !subtra_shift_nonzero;
wire [54:0] subtra_shift_2 = { 54'b0, 1'b1 };
reg [54:0] subtra_shift_3;
reg [54:0] diff;
reg diffshift_gt_exponent;
reg diffshift_et_55; // when the difference = 0
reg [54:0] diff_1;
reg [10:0] exponent;
reg [10:0] exponent_3;
wire in_norm_out_denorm = (exponent_large > 0) & (exponent== 0);
reg [55:0] diff_3;

always @(posedge clock)

begin
if (reset) begin
exponent_a <= 0;
exponent_b <= 0;
mantissa_a <= 0;
mantissa_b <= 0;
expa_gt_expb <= 0;
expa_et_expb <= 0;
mana_gtet_manb <= 0;
a_gtet_b <= 0;
sign2 <= 0;
exponent_small <= 0;
exponent_large <= 0;
mantissa_small <= 0;
mantissa_large <= 0;
small_is_denorm <= 0;
large_is_denorm <= 0;
large_norm_small_denorm <= 0;
small_is_nonzero <= 0;
exponent_diff <= 0;
minuend <= 0;
subtrahend <= 0;
subtra_shift <= 0;
subtra_shift_3 <= 0;
diff_shift_2 <= 0;
diff <= 0;
diffshift_gt_exponent <= 0;
diffshift_et_55 <= 0;
diff_1 <= 0;
exponent <= 0;
exponent_3 <= 0;
diff_3 <= 0;
end
else if (enable) begin
exponent_a <= opa[62:52];
exponent_b <= opb[62:52];
mantissa_a <= opa[51:0];
mantissa_b <= opb[51:0];
expa_gt_expb <= exponent_a > exponent_b;
expa_et_expb <= exponent_a == exponent_b;
mana_gtet_manb <= mantissa_a >= mantissa_b;
a_gtet_b <= expa_gt_expb | (expa_et_expb & mana_gtet_manb);
sign2 <= a_gtet_b ? opa[63] :!opb[63];
exponent_small <= a_gtet_b ? exponent_b : exponent_a;
exponent_large <= a_gtet_b ? exponent_a : exponent_b;
mantissa_small <= a_gtet_b ? mantissa_b : mantissa_a;
mantissa_large <= a_gtet_b ? mantissa_a : mantissa_b;
small_is_denorm <= !(exponent_small > 0);
large_is_denorm <= !(exponent_large > 0);
large_norm_small_denorm <= (small_is_denorm == 1 && large_is_denorm == 0
);
small_is_nonzero <= (exponent_small > 0) | |mantissa_small[51:0];
 exponent_diff <= exponent_large - exponent_small - large_norm_small_deno
rm;
minuend <= { !large_is_denorm, mantissa_large, 2'b00 };
subtrahend <= { !small_is_denorm, mantissa_small, 2'b00 };
subtra_shift <= subtrahend >> exponent_diff;
subtra_shift_3 <= subtra_fraction_enable ? subtra_shift_2 : subtra_shift
;
diff_shift_2 <= diff_shift;
diff <= minuend - subtra_shift_3;
diffshift_gt_exponent <= diff_shift_2 > exponent_large;
diffshift_et_55 <= diff_shift_2 == 55;
diff_1 <= diffshift_gt_exponent ? diff << exponent_large : diff << diff_
shift_2;
exponent <= diffshift_gt_exponent ? 0 : (exponent_large - diff_shift_2);
exponent_3 <= diffshift_et_55 ? 0 : exponent;
diff_3 <= in_norm_out_denorm ? { 1'b0, diff_1 >> 1} : {1'b0, diff_1};
end
end

always @(diff)
casex(diff)
55'b1??????????????????????????????????????????????????????: diff_shift <=
0;
55'b01?????????????????????????????????????????????????????: diff_shift <=
1;
55'b001????????????????????????????????????????????????????: diff_shift <=
2;
55'b0001???????????????????????????????????????????????????: diff_shift <=
3;
55'b00001??????????????????????????????????????????????????: diff_shift <=
4;
55'b000001?????????????????????????????????????????????????: diff_shift <=
5;
55'b0000001????????????????????????????????????????????????: diff_shift <=
6;
55'b00000001???????????????????????????????????????????????: diff_shift <=
7;
55'b000000001??????????????????????????????????????????????: diff_shift <=
8;
55'b0000000001?????????????????????????????????????????????: diff_shift <=
9;
55'b00000000001????????????????????????????????????????????: diff_shift <=
10;
55'b000000000001???????????????????????????????????????????: diff_shift <=
11;
55'b0000000000001??????????????????????????????????????????: diff_shift <=
12;
55'b00000000000001?????????????????????????????????????????: diff_shift <=
13;
55'b000000000000001????????????????????????????????????????: diff_shift <=
14;
55'b0000000000000001???????????????????????????????????????: diff_shift <=
15;
55'b00000000000000001??????????????????????????????????????: diff_shift <=
16;
55'b000000000000000001?????????????????????????????????????: diff_shift <=
17;
55'b0000000000000000001????????????????????????????????????: diff_shift <=
18;
55'b00000000000000000001???????????????????????????????????: diff_shift <=
19;
55'b000000000000000000001??????????????????????????????????: diff_shift <=
20;
55'b0000000000000000000001?????????????????????????????????: diff_shift <=
21;
55'b00000000000000000000001????????????????????????????????: diff_shift <=
22;
55'b000000000000000000000001???????????????????????????????: diff_shift <=
23;
55'b0000000000000000000000001??????????????????????????????: diff_shift <=
24;
55'b00000000000000000000000001?????????????????????????????: diff_shift <=
25;
55'b000000000000000000000000001????????????????????????????: diff_shift <=
26;
55'b0000000000000000000000000001???????????????????????????: diff_shift <=
27;
55'b00000000000000000000000000001??????????????????????????: diff_shift <=
28;
55'b000000000000000000000000000001?????????????????????????: diff_shift <=
29;
55'b0000000000000000000000000000001????????????????????????: diff_shift <=
30;
55'b00000000000000000000000000000001???????????????????????: diff_shift <=
31;
55'b000000000000000000000000000000001??????????????????????: diff_shift <=
32;
55'b0000000000000000000000000000000001?????????????????????: diff_shift <=
33;
55'b00000000000000000000000000000000001????????????????????: diff_shift <=
34;
55'b000000000000000000000000000000000001???????????????????: diff_shift <=
35;
55'b0000000000000000000000000000000000001??????????????????: diff_shift <=
36;
55'b00000000000000000000000000000000000001?????????????????: diff_shift <=
37;
55'b000000000000000000000000000000000000001????????????????: diff_shift <=
38;
55'b0000000000000000000000000000000000000001???????????????: diff_shift <=
39;
55'b00000000000000000000000000000000000000001??????????????: diff_shift <=
40;
55'b000000000000000000000000000000000000000001?????????????: diff_shift <=
41;
55'b0000000000000000000000000000000000000000001????????????: diff_shift <=
42;
55'b00000000000000000000000000000000000000000001???????????: diff_shift <=
43;
55'b000000000000000000000000000000000000000000001??????????: diff_shift <=
44;
55'b0000000000000000000000000000000000000000000001?????????: diff_shift <=
45;
55'b00000000000000000000000000000000000000000000001????????: diff_shift <=
46;
55'b000000000000000000000000000000000000000000000001???????: diff_shift <=
47;
55'b0000000000000000000000000000000000000000000000001??????: diff_shift <=
48;
55'b00000000000000000000000000000000000000000000000001?????: diff_shift <=
49;
55'b000000000000000000000000000000000000000000000000001????: diff_shift <=
50;
55'b0000000000000000000000000000000000000000000000000001???: diff_shift <=
51;
55'b00000000000000000000000000000000000000000000000000001??: diff_shift <=
52;
55'b000000000000000000000000000000000000000000000000000001?: diff_shift <=
53;
55'b0000000000000000000000000000000000000000000000000000001: diff_shift <=
54;
55'b0000000000000000000000000000000000000000000000000000000: diff_shift <=
55;
endcase

endmodule

//[22] rotate right

module RR (c,a);
output [63:0] c;
input [63:0] a;
reg [63:0] c;
reg d;
reg [63:0] e;

always @ (a)
begin
d<= a[0];
e=a>>1;
c[63]= a[0];
c[62:0]=a[63:1];
end
endmodule

//[23] rotate left

module RL (c,a);
output [63:0] c;
input [63:0] a;
reg [63:0] c;
reg d;
reg [63:0] e;

always @ (a)
begin
d<= a[63];
e=a<<1;
c[0]= a[63];
c[63:1]=a[62:0];
end
endmodule

// module try (out,c1,b1);

// output out;
// inout c1;
// input b1;
// try1 a1(z,m,c1,z1,x,y,clock,s,enable,reset);
// assign out = c1|b1;
// endmodule
//
//[24] Multiplication
module MUL ( clk, rst, enable, opa, opb, sign, product_7, exponent_5);
input clk;
input rst;
input enable;
input [63:0] opa, opb;
output sign;
output [55:0] product_7;
output [11:0] exponent_5;
reg [5:0] product_shift;
reg [5:0] product_shift_2;

reg sign;
reg [51:0] mantissa_a;
reg [51:0] mantissa_b;
reg [10:0] exponent_a;
reg [10:0] exponent_b;
reg a_is_norm;
reg b_is_norm;
reg a_is_zero;
reg b_is_zero;
reg in_zero;
reg [11:0] exponent_terms;
reg exponent_gt_expoffset;
reg [11:0] exponent_under;
reg [11:0] exponent_1;
wire [11:0] exponent = 0;
reg [11:0] exponent_2;
reg exponent_gt_prodshift;
reg [11:0] exponent_3;
reg [11:0] exponent_4;
reg exponent_et_zero;
reg [52:0] mul_a;
reg [52:0] mul_b;
reg [40:0] product_a;
reg [40:0] product_b;
reg [40:0] product_c;
reg [25:0] product_d;
reg [33:0] product_e;
reg [33:0] product_f;
reg [35:0] product_g;
reg [28:0] product_h;
reg [28:0] product_i;
reg [30:0] product_j;
reg [41:0] sum_0;
reg [35:0] sum_1;
reg [41:0] sum_2;
reg [35:0] sum_3;
reg [36:0] sum_4;
reg [27:0] sum_5;
reg [29:0] sum_6;
reg [36:0] sum_7;
reg [30:0] sum_8;
reg [105:0] product;
reg [105:0] product_1;
reg [105:0] product_2;
reg [105:0] product_3;
reg [105:0] product_4;
reg [105:0] product_5;
reg [105:0] product_6;
reg product_lsb; // if there are any 1's in the remainder
wire [55:0] product_7 = { 1'b0, product_6[105:52], product_lsb };
reg [11:0] exponent_5;
always @(posedge clk)
begin
if (rst) begin
sign <= 0;
mantissa_a <= 0;
mantissa_b <= 0;
exponent_a <= 0;
exponent_b <= 0;
a_is_norm <= 0;
b_is_norm <= 0;
a_is_zero <= 0;
b_is_zero <= 0;
in_zero <= 0;
exponent_terms <= 0;
exponent_gt_expoffset <= 0;
exponent_under <= 0;
exponent_1 <= 0;
exponent_2 <= 0;
exponent_gt_prodshift <= 0;
exponent_3 <= 0;
exponent_4 <= 0;
exponent_et_zero <= 0;
mul_a <= 0;
mul_b <= 0;
product_a <= 0;
product_b <= 0;
product_c <= 0;
product_d <= 0;
product_e <= 0;
product_f <= 0;
product_g <= 0;
product_h <= 0;
product_i <= 0;
product_j <= 0;
sum_0 <= 0;
sum_1 <= 0;
sum_2 <= 0;
sum_3 <= 0;
sum_4 <= 0;
 sum_5 <= 0;
sum_6 <= 0;
sum_7 <= 0;
sum_8 <= 0;
product <= 0;
product_1 <= 0;
product_2 <= 0;
product_3 <= 0;
product_4 <= 0;
product_5 <= 0;
product_6 <= 0;
product_lsb <= 0;
exponent_5 <= 0;
product_shift_2 <= 0;
end
else if (enable) begin
sign <= opa[63] ^ opb[63];
mantissa_a <= opa[51:0];
mantissa_b <= opb[51:0];
exponent_a <= opa[62:52];
exponent_b <= opb[62:52];
a_is_norm <= |exponent_a;
b_is_norm <= |exponent_b;
a_is_zero <= !(|opa[62:0]);
b_is_zero <= !(|opb[62:0]);
in_zero <= a_is_zero | b_is_zero;
exponent_terms <= exponent_a + exponent_b + !a_is_norm + !b_is_norm;
exponent_gt_expoffset <= exponent_terms > 1021;
exponent_under <= 1022 - exponent_terms;
exponent_1 <= exponent_terms - 1022;
exponent_2 <= exponent_gt_expoffset ? exponent_1 : exponent;
exponent_gt_prodshift <= exponent_2 > product_shift_2;
exponent_3 <= exponent_2 - product_shift;
exponent_4 <= exponent_gt_prodshift ? exponent_3 : exponent;
exponent_et_zero <= exponent_4 == 0;
mul_a <= { a_is_norm, mantissa_a };
mul_b <= { b_is_norm, mantissa_b };
product_a <= mul_a[23:0] * mul_b[16:0];
product_b <= mul_a[23:0] * mul_b[33:17];
product_c <= mul_a[23:0] * mul_b[50:34];
product_d <= mul_a[23:0] * mul_b[52:51];
product_e <= mul_a[40:24] * mul_b[16:0];
product_f <= mul_a[40:24] * mul_b[33:17];
product_g <= mul_a[40:24] * mul_b[52:34];
product_h <= mul_a[52:41] * mul_b[16:0];
product_i <= mul_a[52:41] * mul_b[33:17];
product_j <= mul_a[52:41] * mul_b[52:34];
sum_0 <= product_a[40:17] + product_b;
sum_1 <= sum_0[41:7] + product_e;
sum_2 <= sum_1[35:10] + product_c;
sum_3 <= sum_2[41:7] + product_h;
sum_4 <= sum_3 + product_f;
sum_5 <= sum_4[36:10] + product_d;
sum_6 <= sum_5[27:7] + product_i;
sum_7 <= sum_6 + product_g;
sum_8 <= sum_7[36:17] + product_j;
product <= { sum_8, sum_7[16:0], sum_5[6:0], sum_4[9:0], sum_2[6:0],
sum_1[9:0], sum_0[6:0], product_a[16:0] };
product_1 <= product >> exponent_under;
product_2 <= exponent_gt_expoffset ? product : product_1;
 product_3 <= product_2 << product_shift_2;
product_4 <= product_2 << exponent_2;
product_5 <= exponent_gt_prodshift ? product_3 : product_4;
product_6 <= exponent_et_zero ? product_5 >> 1 : product_5;
product_lsb <= |product_6[51:0];
exponent_5 <= in_zero ? 12'b0 : exponent_4;
product_shift_2 <= product_shift; // redundant register
// reduces fanout on product_shift
end
end
always @(product)
casex(product)
106'b1??????????????????????????????????????????????????????????????????????
???????????????????????????????????: product_shift <= 0;
106'b01?????????????????????????????????????????????????????????????????????
???????????????????????????????????: product_shift <= 1;
106'b001????????????????????????????????????????????????????????????????????
???????????????????????????????????: product_shift <= 2;
106'b0001???????????????????????????????????????????????????????????????????
???????????????????????????????????: product_shift <= 3;
106'b00001??????????????????????????????????????????????????????????????????
???????????????????????????????????: product_shift <= 4;
106'b000001?????????????????????????????????????????????????????????????????
???????????????????????????????????: product_shift <= 5;
106'b0000001????????????????????????????????????????????????????????????????
???????????????????????????????????: product_shift <= 6;
106'b00000001???????????????????????????????????????????????????????????????
???????????????????????????????????: product_shift <= 7;
106'b000000001??????????????????????????????????????????????????????????????
???????????????????????????????????: product_shift <= 8;
106'b0000000001?????????????????????????????????????????????????????????????
???????????????????????????????????: product_shift <= 9;
106'b00000000001????????????????????????????????????????????????????????????
???????????????????????????????????: product_shift <= 10;
106'b000000000001???????????????????????????????????????????????????????????
???????????????????????????????????: product_shift <= 11;
106'b0000000000001??????????????????????????????????????????????????????????
???????????????????????????????????: product_shift <= 12;
106'b00000000000001?????????????????????????????????????????????????????????
???????????????????????????????????: product_shift <= 13;
106'b000000000000001????????????????????????????????????????????????????????
???????????????????????????????????: product_shift <= 14;
106'b0000000000000001???????????????????????????????????????????????????????
???????????????????????????????????: product_shift <= 15;
106'b00000000000000001??????????????????????????????????????????????????????
???????????????????????????????????: product_shift <= 16;
106'b000000000000000001?????????????????????????????????????????????????????
???????????????????????????????????: product_shift <= 17;
106'b0000000000000000001????????????????????????????????????????????????????
???????????????????????????????????: product_shift <= 18;
106'b00000000000000000001???????????????????????????????????????????????????
???????????????????????????????????: product_shift <= 19;
106'b000000000000000000001??????????????????????????????????????????????????
???????????????????????????????????: product_shift <= 20;
106'b0000000000000000000001?????????????????????????????????????????????????
???????????????????????????????????: product_shift <= 21;
106'b00000000000000000000001????????????????????????????????????????????????
???????????????????????????????????: product_shift <= 22;
106'b000000000000000000000001???????????????????????????????????????????????
???????????????????????????????????: product_shift <= 23;
106'b0000000000000000000000001??????????????????????????????????????????????
???????????????????????????????????: product_shift <= 24;
106'b00000000000000000000000001?????????????????????????????????????????????
???????????????????????????????????: product_shift <= 25;
106'b000000000000000000000000001????????????????????????????????????????????
???????????????????????????????????: product_shift <= 26;
106'b0000000000000000000000000001???????????????????????????????????????????
???????????????????????????????????: product_shift <= 27;
106'b00000000000000000000000000001??????????????????????????????????????????
???????????????????????????????????: product_shift <= 28;
106'b000000000000000000000000000001?????????????????????????????????????????
???????????????????????????????????: product_shift <= 29;
106'b0000000000000000000000000000001????????????????????????????????????????
???????????????????????????????????: product_shift <= 30;
106'b00000000000000000000000000000001???????????????????????????????????????
???????????????????????????????????: product_shift <= 31;
106'b000000000000000000000000000000001??????????????????????????????????????
???????????????????????????????????: product_shift <= 32;
106'b0000000000000000000000000000000001?????????????????????????????????????
???????????????????????????????????: product_shift <= 33;
106'b00000000000000000000000000000000001????????????????????????????????????
???????????????????????????????????: product_shift <= 34;
106'b000000000000000000000000000000000001???????????????????????????????????
???????????????????????????????????: product_shift <= 35;
106'b0000000000000000000000000000000000001??????????????????????????????????
???????????????????????????????????: product_shift <= 36;
106'b00000000000000000000000000000000000001?????????????????????????????????
???????????????????????????????????: product_shift <= 37;
106'b000000000000000000000000000000000000001????????????????????????????????
???????????????????????????????????: product_shift <= 38;
106'b0000000000000000000000000000000000000001???????????????????????????????
???????????????????????????????????: product_shift <= 39;
106'b00000000000000000000000000000000000000001??????????????????????????????
???????????????????????????????????: product_shift <= 40;
106'b000000000000000000000000000000000000000001?????????????????????????????
???????????????????????????????????: product_shift <= 41;
106'b0000000000000000000000000000000000000000001????????????????????????????
???????????????????????????????????: product_shift <= 42;
106'b00000000000000000000000000000000000000000001???????????????????????????
???????????????????????????????????: product_shift <= 43;
106'b000000000000000000000000000000000000000000001??????????????????????????
???????????????????????????????????: product_shift <= 44;
106'b0000000000000000000000000000000000000000000001?????????????????????????
???????????????????????????????????: product_shift <= 45;
106'b00000000000000000000000000000000000000000000001????????????????????????
???????????????????????????????????: product_shift <= 46;
106'b000000000000000000000000000000000000000000000001???????????????????????
???????????????????????????????????: product_shift <= 47;
106'b0000000000000000000000000000000000000000000000001??????????????????????
???????????????????????????????????: product_shift <= 48;
106'b00000000000000000000000000000000000000000000000001?????????????????????
???????????????????????????????????: product_shift <= 49;
106'b000000000000000000000000000000000000000000000000001????????????????????
???????????????????????????????????: product_shift <= 50;
106'b0000000000000000000000000000000000000000000000000001???????????????????
???????????????????????????????????: product_shift <= 51;
106'b00000000000000000000000000000000000000000000000000001??????????????????
???????????????????????????????????: product_shift <= 52;
106'b000000000000000000000000000000000000000000000000000000?????????????????
???????????????????????????????????: product_shift <= 53;
// It's not necessary to go past 53, because you will only get more than 5
3 zeros
// when multiplying 2 denormalized numbers together, in which case you wil
l underflow
endcase
endmodule

module acc(clock,reset,accdatain,accen,accdataout);
output [63:0] accdataout;
input [63:0] accdatain;
input clock,reset;
input accen;
reg [63:0] dataout;

assign accdataout=dataout;
always @ (posedge reset, negedge clock)
begin
if (reset==1'b1)
dataout<=64'b0;
else if (accen==1'b1)
dataout<=accdatain;
else
dataout<=dataout;
end
endmodule

//module PC(clock,reset,pcdatain,pcinen,pcdataout);
//output [11:0] pcdataout;
//input clock,reset,pcinen;
//input [11:0] pcdatain;
//reg [11:0] pcdataout;
//
//always @ (posedge reset, negedge clock)
//begin
//if(reset==1'b1)
//pcdataout<=12'b0;
//
//else if(pcinen==1'b1)
//pcdataout<=pcdatain;
//
//else
//pcdataout<=pcdataout;
//end
//endmodule
//

module control_unit(clock,
reset,
OpCode,
ACCNeg,
ACCZero,
 Grant,
NextState,
//PCInEn,
IRInEn,
wr,
read1,
read2,
en,
//ACCInEn,
//ACCOutEn,
//MemReq,
//RdWrBar,
//AddressSel,
//ALUSrcBSel
);
parameter OpcodeSize = 40;
parameter StateSize = 2;
parameter Low = 1'b0;
parameter High = 1'b1;
//parameter SelInstrAddr = 1'b0;
//parameter SelOperandAddr = 1'b1;
//parameter SelAddress = 1'b0;
//parameter SelData = 1'b1;
parameter AND = 40'b0000000000_0000000000_0000000000_0000000000;
parameter OR = 40'b0000000000_0000000000_0000000000_0000000001;
parameter XOR = 40'b0000000000_0000000000_0000000000_0000000010;
parameter SL = 40'b0000000000_0000000000_0000000000_0000000011;
parameter SR = 40'b0000000000_0000000000_0000000000_0000000100;
parameter INC = 40'b0000000000_0000000000_0000000000_0000000101;
parameter DEC = 40'b0000000000_0000000000_0000000000_0000000110;
parameter RRC = 40'b0000000000_0000000000_0000000000_0000000111;
parameter RLC = 40'b0000000000_0000000000_0000000000_0000001000;
parameter COMP = 40'b0000000000_0000000000_0000000000_0000001001;
parameter SETC = 40'b0000000000_0000000000_0000000000_0000001010;
parameter COMPC= 40'b0000000000_0000000000_0000000000_0000001011;
parameter RESETC=40'b0000000000_0000000000_0000000000_0000001100;
parameter RESETZ=40'b0000000000_0000000000_0000000000_0000001101;
parameter SETZ = 40'b0000000000_0000000000_0000000000_0000001110;
parameter CAMP = 40'b0000000000_0000000000_0000000000_0000001111;
parameter LXI = 40'b0000000000_0000000000_0000000000_0000010000;
parameter MOV = 40'b0000000000_0000000000_0000000000_0000010001;
parameter MVI = 40'b0000000000_0000000000_0000000000_0000010010;
parameter NOP = 40'b0000000000_0000000000_0000000000_0000010011;
parameter HALT = 40'b0000000000_0000000000_0000000000_0000010100;
parameter ADD = 40'b0000000000_0000000000_0000000000_0000010101;
parameter SUB = 40'b0000000000_0000000000_0000000000_0000010110;
parameter RR = 40'b0000000000_0000000000_0000000000_0000010111;
parameter RL = 40'b0000000000_0000000000_0000000000_0000011000;
parameter MUL = 40'b0000000000_0000000000_0000000000_0000011001;
//parameter MAP = 8'h64;
parameter Init = 2'b00;
parameter InstrFetch = 2'b01;
parameter InstrExec = 2'b10;
parameter InstrStop = 2'b11;
input clock;
input reset;
input [OpcodeSize - 1 : 0] OpCode;
input ACCNeg;
input ACCZero;
input Grant;
output [StateSize - 1 : 0] NextState;
//output PCInEn;
output IRInEn;
output wr;
output read1;
output read2;
output en;
//output ACCInEn;
//output ACCOutEn;
///////output MemReq;
//output RdWrBar;
//output AddressSel;
//output ALUSrcBSel;
//reg PCInEn;
reg IRInEn;
reg wr;
reg read1;
reg read2;
reg en;
//reg ACCInEn;
//reg ACCOutEn;
//reg MemReq;
//reg RdWrBar;
//reg AddressSel;
//reg ALUSrcBSel;
wire [StateSize - 1 : 0] NextState;
reg [1:0]state;
assign NextState = state;
always @(posedge reset or negedge clock)
begin
if(reset == 1'b1)
begin
state <= Init;
end
else
begin
casex ({Grant,OpCode,state})
43'b0_xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx_00: state <= Init;
43'b1_0000000000000000000000000000000000000000_00: state <= InstrFetch;
43'b1_xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx_00: state <= InstrFetch;
43'b1_xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx_01: state <= InstrExec;
//43'b1_1111111111111111111111111111111111111111_10: state <= InstrStop
;
//43'b1_xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx_10: state <= InstrFetc
h;
//43'b1_1111111111111111111111111111111111111111_11: state <= Init;
//default: state <= Init;
endcase
end
end
always @(reset or state or ACCNeg or ACCZero or OpCode)
begin
if (reset == 1'b1) // instruction initialiation
begin
//PCInEn <= Low;
IRInEn <= Low;
wr <= Low;
read1 <= Low;
read2 <= Low;
en <= Low;
//ACCInEn <= Low;
//ACCOutEn <= Low;
//MemReq <= Low;
//RdWrBar <= Low;
//AddressSel <= Low;
//ALUSrcBSel <= Low;
end
 else
if (state == InstrFetch) // instruction fetch
begin
//PCInEn <= High;
IRInEn <= High;
//ACCInEn <= Low;
//ACCOutEn <= Low;
wr <= Low;
read1 <= Low;
read2 <= Low;
en <= Low;
//MemReq <= High;
//RdWrBar <= High;
//AddressSel <= SelInstrAddr;
//ALUSrcBSel <= SelAddress;
end
else
if (state == InstrExec)
begin
case (OpCode)
AND:
begin
// PCInEn <= Low;
IRInEn <= High;
wr <= Low;
read1 <= Low;
read2 <= Low;
en <= High;
// ACCInEn <= High;
// ACCOutEn <= Low;
// MemReq <= High;
// RdWrBar <= High;
// AddressSel <= SelOperandAddr;
// ALUSrcBSel <= SelData;
end
OR:
begin
// PCInEn <= Low;
IRInEn <= High;
wr <= Low;
read1 <= Low;
read2 <= Low;
en <= High;
// ACCInEn <= High;
// ACCOutEn <= Low;
// MemReq <= High;
// RdWrBar <= High;
// AddressSel <= SelOperandAddr;
// ALUSrcBSel <= SelData;
end
XOR:
begin
// PCInEn <= Low;
IRInEn <= High;
wr <= Low;
read1 <= Low;
read2 <= Low;
en <= High;
// ACCInEn <= High;
// ACCOutEn <= Low;
// MemReq <= High;
// RdWrBar <= High;
// AddressSel <= SelOperandAddr;
// ALUSrcBSel <= SelData;
end
SL:
begin
// PCInEn <= Low;
IRInEn <= Low;
wr <= Low;
read1 <= Low;
read2 <= Low;
en <= High;
// ACCInEn <= High;
// ACCOutEn <= Low;
// MemReq <= Low;
// RdWrBar <= Low;
// AddressSel <= SelOperandAddr;
// ALUSrcBSel <= SelAddress;
end
SR:
begin
// PCInEn <= Low;
IRInEn <= Low;
wr <= Low;
read1 <= Low;
read2 <= Low;
en <= High;
// ACCInEn <= High;
// ACCOutEn <= Low;
// MemReq <= Low;
// RdWrBar <= Low;
// AddressSel <= SelOperandAddr;
// ALUSrcBSel <= SelAddress;
end
INC:
begin
// PCInEn <= Low;
IRInEn <= Low;
wr <= Low;
read1 <= Low;
read2 <= Low;
en <= High;
// ACCInEn <= High;
// ACCOutEn <= Low;
// MemReq <= High;
// RdWrBar <= High;
// AddressSel <= SelOperandAddr;
// ALUSrcBSel <= SelData;
end
DEC:
begin
// PCInEn <= Low;
IRInEn <= Low;
wr <= Low;
read1 <= Low;
read2 <= Low;
 en <= High;
// ACCInEn <= High;
// ACCOutEn <= Low;
// MemReq <= High;
// RdWrBar <= High;
// AddressSel <= SelOperandAddr;
// ALUSrcBSel <= SelData;
end
RRC:
begin
// PCInEn <= Low;
IRInEn <= Low;
wr <= Low;
read1 <= Low;
read2 <= Low;
en <= High;
// ACCInEn <= High;
// ACCOutEn <= Low;
// MemReq <= High;
// RdWrBar <= High;
// AddressSel <= SelOperandAddr;
// ALUSrcBSel <= SelAddress;
end
RLC:
begin
// PCInEn <= Low;
IRInEn <= Low;
wr <= Low;
read1 <= Low;
read2 <= Low;
en <= High;
// ACCInEn <= High;
// ACCOutEn <= Low;
// MemReq <= High;
// RdWrBar <= High;
// AddressSel <= SelOperandAddr;
// ALUSrcBSel <= SelAddress;
end
COMP:
begin
// PCInEn <= Low;
IRInEn <= Low;
wr <= Low;
read1 <= Low;
read2 <= Low;
en <= High;
// ACCInEn <= High;
// ACCOutEn <= Low;
// MemReq <= High;
// RdWrBar <= High;
// AddressSel <= SelOperandAddr;
// ALUSrcBSel <= SelData;
end
SETC:
begin
// PCInEn <= Low;
IRInEn <= Low;
wr <= Low;
read1 <= Low;
read2 <= Low;
 en <= High;
// ACCInEn <= High;
// ACCOutEn <= Low;
// MemReq <= High;
// RdWrBar <= High;
// AddressSel <= SelOperandAddr;
// ALUSrcBSel <= SelData;
end
COMPC:
begin
// PCInEn <= Low;
IRInEn <= Low;
wr <= Low;
read1 <= Low;
read2 <= Low;
en <= High;
// ACCInEn <= High;
// ACCOutEn <= Low;
// MemReq <= High;
// RdWrBar <= High;
// AddressSel <= SelOperandAddr;
// ALUSrcBSel <= SelData;
end
RESETC:
begin
// PCInEn <= Low;
IRInEn <= Low;
wr <= Low;
read1 <= Low;
read2 <= Low;
en <= High;
// ACCInEn <= High;
// ACCOutEn <= Low;
// MemReq <= High;
// RdWrBar <= High;
// AddressSel <= SelOperandAddr;
// ALUSrcBSel <= SelData;
end
RESETZ:
begin
// PCInEn <= Low;
IRInEn <= Low;
wr <= Low;
read1 <= Low;
read2 <= Low;
en <= High;
// ACCInEn <= High;
// ACCOutEn <= Low;
// MemReq <= High;
// RdWrBar <= High;
// AddressSel <= SelOperandAddr;
// ALUSrcBSel <= SelData;
end
SETZ:
begin
// PCInEn <= Low;
IRInEn <= Low;
wr <= Low;
read1 <= Low;
read2 <= Low;
 en <= High;
// ACCInEn <= High;
// ACCOutEn <= Low;
// MemReq <= High;
// RdWrBar <= High;
// AddressSel <= SelOperandAddr;
// ALUSrcBSel <= SelData;
end
CAMP:
begin
// PCInEn <= Low;
IRInEn <= Low;
wr <= Low;
read1 <= Low;
read2 <= Low;
en <= High;
// ACCInEn <= High;
// ACCOutEn <= Low;
// MemReq <= High;
// RdWrBar <= High;
// AddressSel <= SelOperandAddr;
// ALUSrcBSel <= SelData;
end
LXI:
begin
// PCInEn <= Low;
IRInEn <= Low;
wr <= Low;
read1 <= Low;
read2 <= Low;
en <= High;
// ACCInEn <= High;
// ACCOutEn <= Low;
// MemReq <= High;
// RdWrBar <= High;
// AddressSel <= SelOperandAddr;
// ALUSrcBSel <= SelData;
end
MOV:
begin
// PCInEn <= Low;
IRInEn <= Low;
wr <= Low;
read1 <= Low;
read2 <= Low;
en <= High;
// ACCInEn <= High;
// ACCOutEn <= Low;
// MemReq <= High;
// RdWrBar <= High;
// AddressSel <= SelOperandAddr;
// ALUSrcBSel <= SelData;
end
MVI:
begin
// PCInEn <= Low;
IRInEn <= Low;
wr <= Low;
read1 <= Low;
read2 <= Low;
 en <= High;
// ACCInEn <= High;
// ACCOutEn <= Low;
// MemReq <= High;
// RdWrBar <= High;
// AddressSel <= SelOperandAddr;
// ALUSrcBSel <= SelData;
end
ADD:
begin
// PCInEn <= Low;
IRInEn <= Low;
wr <= Low;
read1 <= Low;
read2 <= Low;
en <= High;
// ACCInEn <= High;
// ACCOutEn <= Low;
// MemReq <= High;
// RdWrBar <= High;
// AddressSel <= SelOperandAddr;
// ALUSrcBSel <= SelData;
end
SUB:
begin
// PCInEn <= Low;
IRInEn <= Low;
wr <= Low;
read1 <= Low;
read2 <= Low;
en <= High;
// ACCInEn <= High;
// ACCOutEn <= Low;
// MemReq <= High;
// RdWrBar <= High;
// AddressSel <= SelOperandAddr;
// ALUSrcBSel <= SelData;
end
RR:
begin
// PCInEn <= Low;
IRInEn <= Low;
wr <= Low;
read1 <= Low;
read2 <= Low;
en <= High;
// ACCInEn <= High;
// ACCOutEn <= Low;
// MemReq <= Low;
// RdWrBar <= Low;
// AddressSel <= SelOperandAddr;
// ALUSrcBSel <= SelAddress;
end
RL:
begin
// PCInEn <= Low;
IRInEn <= Low;
wr <= Low;
read1 <= Low;
read2 <= Low;
 en <= High;
// ACCInEn <= High;
// ACCOutEn <= Low;
// MemReq <= Low;
// RdWrBar <= Low;
// AddressSel <= SelOperandAddr;
// ALUSrcBSel <= SelAddress;
end
MUL:
begin
// PCInEn <= Low;
IRInEn <= Low;
wr <= Low;
read1 <= Low;
read2 <= Low;
en <= High;
// ACCInEn <= High;
// ACCOutEn <= Low;
// MemReq <= High;
// RdWrBar <= High;
// AddressSel <= SelOperandAddr;
// ALUSrcBSel <= SelData;
end
default:
begin
//PCInEn <= Low;
IRInEn <= Low;
wr <= Low;
read1 <= Low;
read2 <= Low;
en <= Low;
//ACCInEn <= Low;
//ACCOutEn <= Low;
//MemReq <= Low;
//RdWrBar <= High;
//AddressSel <= SelOperandAddr;
//ALUSrcBSel <= SelAddress;
end
endcase
end
else
if (state == InstrStop)
begin
//PCInEn <= Low;
IRInEn <= Low;
wr <= Low;
read1 <= Low;
read2 <= Low;
en <= Low;
//ACCInEn <= Low;
//ACCOutEn <= Low;
//MemReq <= Low;
//RdWrBar <= High;
//AddressSel <= SelAddress;
//ALUSrcBSel <= SelAddress;
end
end
endmodule