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O RGANIC T RANSISTORS

—

M ETHODIK ZUR S CHALTUNGSANALYSE FÜR

ORGANISCHE T RANSISTOREN

Universität Erlangen-Nürnberg

zur Erlangung des Grades

D OKTOR – I NGENIEUR

vorgelegt von

Jürgen Krumm

Erlangen – 2008

Als Dissertation genehmigt von

der Technischen Fakultät der

Universität Erlangen-Nürnberg

Tag der Promotion: 03.03.2008

Dekan: Prof. Dr.-Ing. habil. J. Huber

Berichterstatter: Prof. Dr.-Ing. W. H. Glauert

Prof. Dr.-Ing. habil. R. Weigel

I

Danksagung

Diese Arbeit entstand als Ergebnis meiner wissenschaftlichen Tätigkeit am Lehrstuhl für

Rechnergestützten Schaltungsentwurf der Friedrich-Alexander-Universität Erlangen-Nürnberg.

Ich bedanke mich bei Herrn Prof. Dr.-Ing. Wolfram H. Glauert für die hervorragende Be-

treuung und Begutachtung dieser Arbeit. Für die freundliche Übernahme des Zweitgutachtens

danke ich Herrn Prof. Dr.-Ing. Dr.-Ing. habil. Robert Weigel. Bei den folgenden Personen

bedanke ich mich für die vielen fachlichen Diskussionen bzw. für das Korrekturlesen von

Kapiteln meiner Arbeit: Ahmed Amar, Dr. Robert Blache, Dr.-Ing. Markus Böhm, Dr. Hen-

ning Rost, Katharina Schätzler, Wolfgang Schirmer und Dr. Dietmar Zipperer. Ferner gilt

mein Dank den Lehrstuhlkollegen Elke Eckert, Wolfgang Magerl und Klaus Schneider, mit

denen ich an verschiedenen Projekten aus der Polymerelektronik arbeiten durfte. Besonders

bedanken möchte ich mich auch bei meinen Zimmerkollegen Thomas Bürner, Werner Haas

und Reinhard Hofmann für das nette Arbeitsumfeld. Für die organisatorische Hilfe im Vor-

feld und während der Promotionsprüfung bedanke ich mich bei Frau Roswitha Rauch, der

Sekretärin des Lehrstuhls.

Schließlich danke ich meiner Familie für ihre Unterstützung.

Jürgen Krumm

II

Contents III

Contents

1 Introduction 1

1.1 Circuit Simulation in the Optimization of OFETs . . . . . . . . . . . . . . . 2

1.2 Aim of this Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.3 Scientific Contribution of this Work . . . . . . . . . . . . . . . . . . . . . . 4

1.4 Outline of this Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 State of the Art in Organic Circuits . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Organic Semiconductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2.1 Oligomers and Polymers . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2.2 Unipolar and Ambipolar Semiconductors . . . . . . . . . . . . . . . 9

2.2.3 Charge Transport Models . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3 Organic Field-Effect Transistors . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3.1 Device Characteristics of an OFET . . . . . . . . . . . . . . . . . . 11

2.3.2 Differences between MOSFET and OFET . . . . . . . . . . . . . . . 13

2.4 Printing and Roll-to-Roll Fabrication . . . . . . . . . . . . . . . . . . . . . . 15

2.5 Chapter Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1 Model Requirements for Circuit Simulation . . . . . . . . . . . . . . . . . . 19

3.2 Existing Models for OFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.2.1 Shichman-Hodges Model (Level-1 Model) . . . . . . . . . . . . . . 22

3.2.2 Model for Polycrystalline TFTs . . . . . . . . . . . . . . . . . . . . 27

3.2.3 Model for Amorphous TFTs . . . . . . . . . . . . . . . . . . . . . . 32

3.2.4 Analytic VRH Models . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.2.5 General Table-based Models . . . . . . . . . . . . . . . . . . . . . . 43

3.2.6 Dresden Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.2.7 Modeling of Complementary OFETs . . . . . . . . . . . . . . . . . 46

3.2.8 Modeling of Ambipolar OFETs . . . . . . . . . . . . . . . . . . . . 48

IV Contents

3.3.1 Procedures for the Level-1 Model . . . . . . . . . . . . . . . . . . . 50

3.3.2 Extraction Procedures for TFT Models . . . . . . . . . . . . . . . . 59

3.3.3 Parameter Fitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

3.4 Automation of Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.4.1 Existing Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.4.2 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

3.5 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

4 VSat Method 69

4.1 Extraction based on VSat Method . . . . . . . . . . . . . . . . . . . . . . . . 70

4.2 Modeling based on VSat Method . . . . . . . . . . . . . . . . . . . . . . . . 73

4.2.1 VSat -Type Table-Based Model . . . . . . . . . . . . . . . . . . . . . 73

4.2.2 Linvar Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

4.3 Experimental Results on Transistor Fitting . . . . . . . . . . . . . . . . . . . 76

4.3.1 Analysis of a Level-1 Transistor . . . . . . . . . . . . . . . . . . . . 76

4.3.2 Analysis of Model for Polycrystalline TFTs . . . . . . . . . . . . . . 77

4.3.3 Effect of Contact Resistance on Level-1 Model . . . . . . . . . . . . 81

4.3.4 Compensation of Contact Resistance . . . . . . . . . . . . . . . . . . 82

4.3.5 Analysis of a PDHTT Transistor . . . . . . . . . . . . . . . . . . . . 87

4.3.6 Modeling of a P3HT Transistor . . . . . . . . . . . . . . . . . . . . 87

4.3.7 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

4.4 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

5.1 Logic Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

5.1.1 Basic Circuit Concepts . . . . . . . . . . . . . . . . . . . . . . . . . 93

5.1.2 Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

5.2 Circuit Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

5.3 Characterization of Robustness . . . . . . . . . . . . . . . . . . . . . . . . . 99

5.3.1 Method of Equilibrium Zones . . . . . . . . . . . . . . . . . . . . . 99

5.3.2 Concept of Noise Margin . . . . . . . . . . . . . . . . . . . . . . . . 102

5.3.3 Unity Gain Method . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

5.3.4 Method of Maximum Squares . . . . . . . . . . . . . . . . . . . . . 106

5.3.5 VTC Gain Considerations . . . . . . . . . . . . . . . . . . . . . . . 109

5.3.6 Discussion of Characterization Methods . . . . . . . . . . . . . . . . 110

5.4 Timing Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

5.5 Automation of Circuit Characterization . . . . . . . . . . . . . . . . . . . . 115

Contents V

5.5.2 General Characterization Tools . . . . . . . . . . . . . . . . . . . . . 116

5.5.3 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

5.6 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

6.1 Typical Analysis Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

6.2 Novel Analysis Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

6.2.1 Data Management . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

6.2.2 Modeling System . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

6.2.3 Analysis Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

6.2.4 Simulator Encapsulation . . . . . . . . . . . . . . . . . . . . . . . . 135

6.3 Analysis Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

6.3.1 Analysis of an Inverter in Current-Source Configuration . . . . . . . 136

6.3.2 Analysis of NOR-Gates in Current-Source Configuration . . . . . . . 143

6.3.3 Analysis of Parameter-dependent Gate Behavior . . . . . . . . . . . 146

6.4 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

7.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

7.2 Further Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

C Glossary 163

Bibliography 170

VI

VII

Abstract

In this work, a novel computer-aided methodology for the analysis of the performance of

organic transistors (OFETs) in logic circuits is described. The basic idea of the concept is to

provide an integrated environment which includes data management, modeling of transistors,

and the automatic analysis of organic circuits. Existing OFET models as well as procedures

and software tools for extracting their model parameters are analyzed. A novel formalism

which compares the quality of models is defined using a model quality chart. Furthermore, a

novel method of extracting basic model parameters in dependence on the gate-source voltage

is detailed. It aids in visualizing which type of model best maps a given transistor. Two

transistor models are presented: a table-based model and an analytical model. Procedures for

characterizing static and dynamic behavior of basic logic circuits are discussed as well as tools

for deriving appropriate performance figures. Novel methods of extracting the robustness

of logic gates are presented. Several examples demonstrate the application of the analysis

methodology to organic logic circuits and OFET modeling issues, respectively.

Kurzfassung

In dieser Arbeit wird eine neue, Computer-gestützte Methodik zur Performanceanalyse von

organischen Transistoren (OFETs) in Logikschaltungen beschrieben. Das Konzept basiert

auf der Grundidee, eine integrierte Umgebung für die Datenverwaltung, die Modellierung

von Transistoren und die automatische Analyse organischer Schaltungen bereitzustellen. Ex-

istierende OFET-Modelle sowie Prozeduren und Software-Werkzeuge zur Extraktion der zuge-

hörigen Modellparameter werden untersucht. Ein neuer Formalismus, um die Qualität einzel-

ner Modelle mit Hilfe einer Qualitätscheckliste zu vergleichen, wird definiert. Ein neues Ver-

fahren zur Extraktion grundlegender Modellparameter in Abhängigkeit von der Gate-Source-

Spannung wird beschrieben. Das Verfahren visualisiert, durch welchen Modelltyp ein ge-

gebener Transistor am besten abgebildet werden kann. Zwei Transistormodelle werden vorge-

stellt: ein Tabellenmodell und ein analytisches Modell. Verfahren und Software-Werkzeuge,

um das statische und dynamische Verhalten grundlegender Logikschaltungen zu charakter-

isieren und zugehörige Kennzahlen zu ermitteln, werden diskutiert. Neue Methoden zur Bes-

timmung der Gatterrobustheit werden vorgestellt. Mehrere Beispiele zeigen die Anwendung

der Analysemethodik bei organischen Logikschaltungen bzw. bei Fragestellungen der OFET-

Modellierung.

VIII

1

Chapter 1

Introduction

The field of low-cost organic electronics is a relatively new topic of research in the domain

of semiconductor technology. Activities started in the 1980s by demonstrating organic field-

effect transistors (OFETs) which make use of special organic compounds for the semiconduct-

ing channel instead of crystalline silicon. These OFETs cannot compete with silicon-based

transistors regarding switching speed or packing density but provide prospects of consider-

ably reducing fabrication costs, large-area manufacturing (i.e. direct application of electronic

structures onto large substrates), or implementing mechanically flexible integrated circuits.

These advantages generate applications of OFETs where fabrication costs or flexibility are

more important than e.g. switching speed of the transistors. One example is the implemen-

tation of extremely low-cost radio-frequency identification (RFID) tags. Fabrication costs

below one Cent would e.g. boost application of RFID devices as price tags in supermarkets.

Owing to their complex fabrication, silicon-based RFID tags cannot reach this price target.

Currently, low-cost organic electronics is in the early stages of development and optimiza-

tion of devices and processes. Various materials and fabrication processes are continuously

tested and optimized. Circuit simulation is an important part in this process as it provides

insight into the performance potential of existing or hypothetical OFET generations in OFET-

based circuits. In the course of circuit simulation, devices are modeled and the electrical

performance of typical application circuits is analyzed. Employing circuit simulation in the

process of optimizing devices consists of numerous iterations of modeling devices, simulating

application circuits, and extracting performance figures from simulation results. Therefore,

efficient methods of modeling OFET devices and analyzing OFET-based circuits by use of

circuit simulation are needed in order to automate the analysis process as much as possible.

This thesis describes a methodology for efficient modeling of OFETs and analysis of

OFET-based logic circuits. The basic idea is to provide a uniform analysis environment which

seamlessly integrates transistor modeling, circuit analysis of OFET-based circuits, and neces-

sary data management.

2 Chapter 1. Introduction

Fig. 1.1 shows where circuit simulation can be used in the evaluation of an OFET process.

The flow consists of manufacturing OFETs, characterizing their electrical performance or

long-term stability, and subsequently improving the process, which leads to new iterations of

the procedure.

Device

fabrication

Circuit Simulation

characterization extraction

analysis modeling Models

Testbench Benchmark

generation circuits

Circuit

characterization Testbenches

leads to

Process Reporting

improvements

Fig. 1.1: Generic analysis flow showing the evaluation of the electrical performance of novel

OFET technologies by use of circuit simulation.

In the depicted flow, device characterization and performance analysis include circuit sim-

ulation (shaded box in the figure) where device parameters like threshold voltage or charge-

carrier mobility are extracted. From these parameters, simulation models are generated for

the OFET devices. Depending on the fabrication technology, different transistor models are

needed. Devices fabricated in a certain layer setup (bottom gate / bottom contact structure

[2, 3], see Section 2.3.1) e.g. display substantial contact resistance between the electrodes

and the channel. Models and their parameters are used in the analysis of benchmark circuits.

The term benchmark circuit refers to the fact that these circuits are used for the evaluating

and comparing different device generations. Benchmarking should be carried out with typical

application circuits like OFET-based logic circuits. Analysis of benchmark circuits requires

suitable testbenches. A testbench is a circuit setup containing the benchmark circuits and ad-

1.1. Circuit Simulation in the Optimization of OFETs 3

ditional circuitry used for extracting performance figures. Performance figures related to logic

circuits are e.g. robustness of the desired logic function against interfering noise at the inputs

and outputs of the gates, circuit speed, power consumption, etc. These performance figures

can be established using a technique called circuit characterization or cell characterization.

Circuit characterization provides information on the electrical properties of the circuits un-

der consideration like input capacitances, timing data, or power consumption at reasonable

operating conditions.

The performance figures of the analyzed circuits can be compared with data derived by

analyzing earlier device generations. This approach is helpful when measuring the improve-

ments between different device generations but is also useful in selecting the most efficient

solution from a list of possible circuit concepts for a given process.

Traditional software tools from the domain of electronic design automation (EDA) easily

cover the circuit simulation tasks depicted in Fig. 1.1. Several problems arise when working

with standard software:

2 Existing software for model extraction is currently not well adapted to OFET devices.

OFET-based transistor models are missing and would have to be included into the ex-

tractors.

circuits. They do not include simple analyses like the determination of the maximum-

square noise margin (see Section 5.3.4). Including new analyses into existing tools is

often difficult as the source code of the programs is not disclosed or would have to be

reworked.

2 Collaboration between different tools is necessary. Data from the model extractor would

have to be transferred to the testbenches used by the characterization tool and charac-

terization results would have to be displayed and archived for documentation and later

reuse.

2 Data organization is up to the user. The optimization of OFET devices and organic logic

gates leads to many iterations of measurement, model extraction, and circuit analysis.

The respective data have to be stored in an efficient way. Prior analysis results must

be accessible later on in order to explore the effects of optimization steps in the fab-

rication process. Moreover, analysis procedures might change because new figures of

merit are introduced. In such a case, prior analyses need to be repeated with the new

characterization flow.

2 The characterization flow depends on the different tools used in the analysis process.

These tools are coordinated by control scripts. As soon as vendors change their tools

4 Chapter 1. Introduction

the characterization flow has to be updated, including the control scripts. Moreover,

migration to other tools would also require recoding of scripts. Additionally, the users

need to understand the inner workings of the tools in order to include them in their

analysis flow.

Therefore, it is desirable to integrate the required tools into a coherent, generic, and flex-

ible framework. Coherent means that the framework seamlessly integrates the different tools

and also covers data management. Generic means that the tools are integrated using abstract

interfaces so that they can easily be replaced. Novel tools can then be integrated by including

appropriate interfaces. Flexible means that the users can add novel characterization scripts by

use of easily adaptable interfaces.

In this thesis, a computer-aided methodology for modeling of OFETs and analyzing their

performance in logic circuits is presented. Development of the methodology leads to research

in the following domains:

dures for extracting their parameters.

low-complexity logic circuits are in focus.

2 Analysis concept: Development of an analysis flow for carrying out parameter extrac-

tion for OFET models and logic gate characterization as well as data management.

Progress in the simulation-based modeling and circuit analysis of organic transistors could be

made in this work. First, a checklist to assess the quality of a modeling approach for OFET

devices in logic circuits has been defined in the model quality chart (MQC). The MQC allows

its users to compare different modeling approaches. Formalisms like the MQC did not exist

before in the domain of organic electronics.

Second, a novel methodology for extracting device parameters in a two-step approach has

been developed. In a first step, the transistor characteristics drain-current (ID ) vs. drain-source

voltage (VDS ) are inspected. For each ID curve, the transition point VSat between linear and

saturation region is extracted using a one-dimensional search. VSat and the measurement data

are then used for calculating three basic transistor parameters: threshold voltage VT , process

1.4. Outline of this Work 5

these parameters extracted for a series of ID curves are characteristic for different model types.

Therefore, they can be used for identifying the model which maps best the measured curves.

This approach contrasts with other analysis procedures which concentrate on the problem

which set of parameters maps best the measured curves for a given model. In a second step,

the extracted VGS -dependent parameters can be mapped to simulation models, e.g. the ones

developed in this work: a table-based model and a fitting-based analytic model.

Third, progress has been made in the analysis of OFET-based logic gates. A novel ap-

proach has been introduced to define the robustness of logic gates by inspecting the gain of

the fix point in the voltage-transfer characteristic. An existing method to qualitatively define

the compatibility of valid logic level ranges has been extended to yield noise margins.

A computer-aided methodology has been developed to run data storage, OFET model-

ing, automatic testbench generation, and circuit characterization within a single environment.

The novelty of the concept is the integration of these tasks by use of appropriate data struc-

tures. Moreover, a graphical scripting system has been integrated into the concept so to allow

non-expert users to flexibly compose their own characterization schemes. Existing tools and

analysis methods have been adapted to the analysis of OFET-based logic circuits.

In Chapter 2, the basics of low-cost organic electronics are sketched with focus on OFETs

and OFET-based logic circuits. Chapter 3 deals with the modeling of OFETs. Here, general

requirements on transistor models are described and existing models for organic transistors are

discussed. Moreover, existing procedures and tools for modeling of transistors are reviewed.

A novel methodology for translating measured transistor characteristics into model parameters

and two new transistor models based on this methodology are detailed in Chapter 4. Here,

selected analysis examples are presented where the methodology is applied. Next, OFET-

based logic circuits and the way how to characterize their static and dynamic behavior are

discussed in Chapter 5. Existing tools for circuit characterization are presented. A novel

analysis concept is then detailed in the first part of Chapter 6. This concept implements

a computer-aided methodology for modeling of OFETs and analysis of OFET-based logic

circuits. In the second part of the chapter, sample sessions demonstrate the application of the

analysis concept in a prototype implementation. Chapter 7 concludes the work by presenting

a summary of the work and an outlook to further developments.

6 Chapter 1. Introduction

7

Chapter 2

Electronics

In recent years, electronic devices based on organic materials have appeared in real appli-

cations. Displays composed of organic light emitting diodes (OLEDs) provide images with

increased brilliance when compared to more traditional display technologies. Small OLED-

based displays have already been commercially introduced. In organic photovoltaics, solar

cells are developed where organic semiconductors are used as the active layer. Moreover,

organic materials are considered for use in non-volatile memories. Another important focus

are integrated circuits (ICs) based on OFETs, which are currently in the development stage.

In the following, the concepts of organic electronics will be briefly introduced. More detailed

descriptions can be found in the references provided in the respective paragraphs. The dis-

cussion will focus on items relevant for low-cost organic transistors (OFETs), which are the

basic building blocks of organic integrated circuits.

The major advantage of organic electronics is ease of fabrication instead of improved electrical

performance of a device. A large number of organic materials can be deposited from solution,

enabling e.g. application of high-speed and high-throughput printing methods. With increased

fabrication speed and output, lower fabrication costs are possible.

Organic ICs e.g. target smart price tags (also called RFID tags or transponders) as applica-

tion. These transponders can be electronically interrogated using a reader and radio frequency

communication. The organic RFID transponders draw their energy from the RF field of the

reader and consist of an antenna, organic rectifiers and an OFET-based logic block for trans-

mitting their information to the reader.

8 Chapter 2. Concepts of Low-Cost Organic Electronics

Prototype RFID tags with organic logic chips have lately been presented [4, 5], partially

fabricated using clean-room techniques. Yet, fully-printed circuits currently lag behind these

complexities and performances. In the domain of low-cost mass printed circuits, state-of-

the-art results were obtained with gravure printed polyfluorene (F8T2) as semiconductor and

offset printed PEDOT-PSS as source-drain material [6]. Measurement results of a seven-stage

ring oscillator1 were presented with an oscillation frequency of 1.2 Hz at a supply voltage of

48 V. Details about the early stages of the underlying fabrication process were presented in

[7]. Another group [8] reported results for a printed seven-stage ring oscillator with polytri-

arylamide (PTAA) as semiconductor. The oscillation frequency was 67 Hz at a supply voltage

of 30 V.

In the following, a brief introduction into organic semiconductors and popular models to de-

scribe their charge-transport mechanisms is given.

Organic semiconductors are the most important materials for the functional layer of organic

transistors used in organic electronics. They are molecules consisting of a repetition of carbon-

based compounds with low molecular weight (called repetition units or monomers). Depend-

ing on the number of repetition units n, organic semiconductors belong to one of two cate-

gories: oligomers or polymers. An oligomer is a compound with n usually less than about 10

to 15. Most oligomers cannot be deposited from solution because they are not very soluble in

common solvents [9]. Instead, they are deposited e.g. by vacuum deposition. Semiconduct-

ing oligomers show superior electrical performance (e.g. switching speed) when compared to

semiconducting polymers. Popular oligomers with semiconducting properties are e.g. pen-

tacene or oligothiophenes. A polymer on the other hand is a compound with a higher number

of repetition units. More precisely, a polymer can be defined as a compound where adding a

new repetition unit will not alter its chemical and electrical behavior [10]. In order to make

polymers soluble in a variety of solvents and provide film forming properties, side chains are

chemically attached to the polymer chain so to allow deposition e.g. by printing methods. A

popular organic semiconductor is the p-type semiconducting polymer poly(3-hexylthiophene)

or P3HT in short. The basic building block of P3HT is thiophene, a ring of four carbon atoms

and one sulfur atom. A hexyl (C6 H13 ) side chain is added to the thiophene ring in order to

1

An oscillator circuit where seven inverters are cascaded and the output of the last inverter is fed back to the

input of the first inverter.

2.2. Organic Semiconductors 9

allow P3HT to be soluble in organic solvents. Fig. 2.1 shows the chemical structure of P3HT.

In the figure, n denotes the number of repetition units.

C6 H13

( S

S

)n

C6 H13

quence of single and double carbon-carbon bonds. Conjugation leads to the presence of delo-

calized molecular orbitals in the material where electrons belong to a group of atoms instead

of a single bond or atom [11]. These electrons are important for charge transport.

The majority of organic semiconductors displays unipolar p-type transport, i.e. hole trans-

port. There also exist unipolar n-type transport materials which show electrical performance

and lower stability under normal environmental conditions, however. Recently, ambipolar

semiconductors (e.g. [12, 13]) have been reported where both n-type and p-type charge trans-

port is possible. These materials are nevertheless in the early stages of research. They are

either intrinsically ambipolar or consist of mixtures of p-type and n-type conducting semicon-

ductors.

Numerous models have been developed to deal with the mechanisms of charge transport

within organic semiconductors. The most popular of these are listed in the following.

Band Transport

By combining atoms into molecules, molecular orbitals are created. The highest molecular

orbital filled with electrons is denoted as HOMO (highest occupied molecular orbital) and the

lowest molecular orbital devoid of electrons as LUMO (lowest unoccupied molecular orbital).

HOMO and LUMO in organic semiconductors are used analogous to the opposing edges of

the valence and conduction bands in more traditional semiconductors. They are separated by

an energy gap.

10 Chapter 2. Concepts of Low-Cost Organic Electronics

positions and distances of the opposing edges of the valence and conduction band. Charge

transport of holes in the valence band and of electrons in the conduction band is limited by

scattering of the charge carriers at lattice vibrations or impurities. The mobility of charge

carriers decreases with elevated temperature because lattice vibrations are less pronounced at

lower temperatures.

Hopping Transport

Many organic semiconductors are regarded as disordered systems where band transport does

not seem reasonable between different molecules. Here, hopping transport provides a better

description of charge transport. In this model, free movement of charge carriers is not possible.

Instead, they hop between neighboring hopping sites. When a charge carrier hops to another

site, its presence there leads to a local deformation of the polymer. The pair of charge carrier

and deformation is called polaron and is modeled as a single quasi-particle. In order to move

between sites, the polaron has to overcome an energy barrier. The probability of crossing this

energy barrier and hopping between sites increases with elevated temperatures.

In the model of multiple trapping and release (MTR), charge carriers are assumed to travel by

band transport. This transport is impeded by the presence of traps near the band edges. These

traps are energy levels within the bandgap which are caused by the presence of impurities or

structural defects [14]. When a charge carrier “falls” into such a trap, it is not available for

charge transport until it gets released again after a certain amount of time, e.g. by thermal

activation. The trapping time depends on the temperature and the energetic depth of the trap.

which are separated by amorphous grain boundaries. While the charge carriers are assumed

to move freely in bands in the crystallites, they get trapped and released at traps in the grain

boundaries. These traps are due to the structural disorder at the interfaces of neighboring

grains. The traps in the grain boundaries get charged by capturing charge carriers. This

trapping creates a depletion region which in turn leads to the formation of an energy barrier.

Charge carriers have to overcome this energy barrier in order to travel across the depletion

region. The grain boundary model can be assumed as a special variation of MTR where traps

concentrate at the grain boundaries.

2.3. Organic Field-Effect Transistors 11

Organic semiconductors find application in organic field-effect transistors. OFETs have many

similarities with more traditional MOSFETs but also considerably differ from these. In the

following, the basic properties of OFETs and their differences to MOSFETs are briefly dis-

cussed.

In Fig. 2.2, circuit symbol as well as output characteristics ID vs. VDS and transfer charac-

teristics ID vs. VGS of an OFET are sketched. For the output characteristics, VDS is swept

in the range of interest at constant VGS values. The transfer characteristics are obtained by

applying a fixed VDS and sweeping VGS in the range of interest.

The schematic plots show the behavior of an n-type (electron transport) OFET with pos-

itive voltages. P-type (hole transport) FETs operate similarly with inverted voltages and cur-

rents. The drain current is modulated by the voltage differences between the three device

electrodes drain (D), gate (G), and source (S). In principle, an OFET operates as a voltage-

dependent resistor between drain and source which is controlled by the gate-source and drain-

source voltage. In logic circuits, this resistor can be regarded as a nonlinear switching element

which cannot be completely switched-off as shown by the logarithmic transfer characteristics

in Fig. 2.2c.

a) b) c)

ID VGS4 log ID

D

fixed VDS

ID

VGS3

G VDS

VGS2

VGS

VGS1

0

S 0

VDS VGS

Fig. 2.2: a) FET symbol with terminal voltages and drain current, b) schematic output char-

acteristics ID vs. VDS , and c) logarithmic transfer characteristics ID vs. VGS .

12 Chapter 2. Concepts of Low-Cost Organic Electronics

In OFETs, the drain current ID is usually proportional to certain material and structural

properties. These material properties are charge-carrier mobility µ or the relative permittivity

εr of the insulator capacitance. Structural properties are channel width W , channel length

L, or the thickness of the insulating layer tis . Using these parameters, ID (here again dis-

cussed for an n-type device) can be approximated by the well-known Shichman-Hodges [15]

equations

W

(VGS − VT )VDS − 21 VDS

2

L

µCis : VDS < VGS − VT

ID = (2.1)

1W

2

µCis (VGS − VT ) : VDS > VGS − VT

2 L

The voltages VDS and VGS are defined according to Fig. 2.2. VT is the threshold voltage.

It can roughly be defined as the voltage at which the channel begins to switch on. Cis is the

capacitance per unit area of the insulator and reads Cis = ε0 εr /tis . ID saturates at high VDS

values (|VDS | ≥ |VGS − VT |) because the voltage drop across the channel no longer leads to

accumulation of charge carriers. In a first-order approximation, the channel region there is

regarded as being pinched-off. Consequently, the drain current saturates.

OFETs belong to the class of thin-film transistors where the semiconducting channel is

deposited as a thin film on the substrate. Owing to this fact, OFETs are also referred to as

OTFTs (Organic Thin-Film Transistors, e.g. [9]). Fig. 2.3 shows a graphical representation of

frequently used OFET structures. These structures are distinguished according to the positions

of the electrodes. In top-gate structures, the gate electrode is deposited on top of all other

layers. In bottom-gate structures, conversely, it is deposited first on the substrate. Each device

setup has special requirements on the compatibility between the different materials used in

the fabrication process (layer materials, solvents, resists, developers).

Top-gate devices provide the advantage of encapsulating the semiconducting layer be-

tween the substrate and the insulator. Bottom-gate devices are often fabricated using the

well-established technology of silicon wafers. Silicon is used for the gate electrode while

silicon dioxide grown on top of the silicon acts as the insulating layer [16].

Charge-carrier mobilities of amorphous organic transistors are usually very low, i.e. in

the range µ < 0.1 cm2 /Vs [17] as opposed to crystalline silicon transistors with electron mo-

bilities µ > 500 cm2 /Vs. This restriction leads to OFETs with large channel widths in the

millimeter range so to allow drain currents of 1 µA and above. Therefore, OFETs are often

realized as interdigitated structures. Fig. 2.4 shows an OFET (top-gate structure) with five fin-

gers in top view. The geometrical device parameters (channel length and width) are indicated

in the drawing.

Parameters for fully-printed as well as clean-room fabricated devices are given in Table 2.1.

For the printed devices, the semiconductor was PTAA while the clean-room fabricated devices

2.3. Organic Field-Effect Transistors 13

Drain Source Semiconductor

Insulator

Insulator Insulator

Semicon.

Drain Source Gate Gate

Substrate Substrate Substrate

Fig. 2.3: Schematic view of different OFET classes: a) top-gate structure, b) bottom-gate

bottom-contact structure, and c) bottom-gate top-contact structure.

Channel width W

Gate

Channel length L

Drain

Source

Fig. 2.4: Schematic top view of an OFET with an interdigitated finger structure.

was manufactured using P3HT. As can be seen from the listed data, considerable differences

between the two processes exist.

Table 2.1: Parameters for fully-printed [18] and clean-room fabricated [19] OFETs.

Parameter fully-printed clean-room fabricated

relative insulator permittivity εr 2.2 to 50 3

insulator thickness tis 0.1-10 µm, depends on εr 300 nm

electrode thickness > 300 nm 40 nm

semiconductor thickness > 500 nm 50 nm

In the following, the operation modes of MOSFETs and OFETs will be compared. First, the

well-known MOSFET is shortly presented and is then compared with an OFET in order to

show the differences between the two transistor types. P-type transistors will be used in the

discussion.

14 Chapter 2. Concepts of Low-Cost Organic Electronics

MOSFET Operation

In p-type MOSFET devices, the channel region is a substrate with n-type doping, i.e. with

electrons as majority carriers (see Fig. 2.5). An oxide is grown on top of the channel region

and serves as the insulator. The drain and source region are both p-type doped with holes as

majority carriers. Therefore, there exist pn junctions at the interface between the electrodes

and the channel when zero voltages are applied at drain, gate, and source. By applying a

negative voltage between gate and source, the channel is depleted. When VGS reaches the

threshold voltage VT , the concentration of minority carriers (holes) begins to exceed the con-

centration of majority carriers (electrons) and the device operates in inversion mode where

the channel region is p-type conducting. Under these conditions, the pn junctions between the

source electrode and the channel as well as the drain electrode and the channel no longer exist

and current can flow between drain and source through the channel. By applying a positive

VGS , majority carriers (electrons) are accumulated and the channel is switched off. No mat-

ter which polarity VDS has, always one of the two pn diodes at source and drain is biased in

reverse direction and blocks current flow.

Gate

Gate Oxide

Drain p+ p+ Source

n−Substrate

Fig. 2.5: Schematic cross section of a p-type MOSFET (p+ and n+ denote heavily p-type and

heavily n-type doped regions).

OFET Operation

substrate or the dielectric. The semiconductor is not doped but intrinsically provides hole

transport. Source and drain electrodes are metals or metal-like conductors with (ideally) little

resistance to the channel region for transport of holes. By applying a negative VGS , holes

injected from the source electrode are accumulated in the channel. Conversely, a positive VGS

depletes the channel and leads to higher channel resistance, which leads to low current.

2.4. Printing and Roll-to-Roll Fabrication 15

Comparison

Table 2.2 provides a comparison between silicon-based MOSFET and OFET technologies.

Property MOSFET OFET

Operation mode strong inversion accumulation

Transport mechanism band transport various models, but still

under debate

Source/drain contacts pn junctions for majority low-resistance contacts for

carriers, one of these is re- majority carriers

verse biased

Substrate provides channel region, no electric function, insu-

semiconducting lating

Typical Charge-carrier 400 to 500 cm /Vs for ≤ 0.1 cm2 /Vs in amor-

2

Fabrication method lithographic process, using various, from photolitho-

clean-room facilities graphy to printing

Semiconductor silicon various conjugated poly-

mers/oligomers

Insulator mainly silicon dioxide numerous possibilities

Electrodes / Intercon- various metals, polysilicon various metals and organic

nect (as gate) conductors

Critical dimension < 1 µm > 1 µm

Based on the selection of constituent materials, OFET-based circuits can be fabricated in

a variety of deposition (e.g. vapor deposition, spin-coating) and structuring methods (e.g.

photolithography, shadow masks). The reader is referred to [20, 21] for a review of fabrication

techniques used in organic electronics.

The most advantageous fabrication techniques are printing methods, which are not appli-

cable in conventional silicon-based processes. Printing techniques like flexography, gravure

printing, screen printing, or inkjet printing, etc. can be used. These lead to high fabrication

volume and throughput as well as low-cost fabrication, which are specific features of low-cost

organic electronics.

Use of printing techniques comes at the cost of some restrictions. The feature sizes are

currently limited to the micrometer range instead of a nanometer scale used with conventional

16 Chapter 2. Concepts of Low-Cost Organic Electronics

silicon transistors [18]. Printing materials have to be chosen carefully so to remain compatible

with the respective printing technology regarding e.g. viscosity, drying behavior, etc. [21, 22].

Some printing techniques can be used in roll-to-roll manufacturing, where the printing

substrate is fed through a printing machine from one roller to another. In comparison to batch

processing of IC wafers, roll-to-roll manufacturing can reach higher throughput. In order to

explain roll-to-roll manufacturing, gravure printing will be discussed in the following with the

help of Fig. 2.6. In gravure printing, a flexible foil is continuously unwound from a roll, travels

between a rotating gravure cylinder and an impression cylinder, and is finally rewound into

another roll. In the printing process, the surface of the rotating gravure cylinder is wetted by

an ink or soluble polymer in a tank. The ink (in organic electronics: semiconductor, insulator,

metal-like electrode material, etc.) is scraped by a doctor blade so that only the quantity filling

up the recessed parts of the cylinder remains. This ink is transferred to the desired positions

of the printing substrate while the cylinder rolls across it.

Roll Impression

cylinder

Roll

Printing substrate

Doctor blade

Gravure cylinder

Ink

2.5. Chapter Conclusions 17

As was shown in Section 2.3.1, MOSFETs and OFETs operate similarly. From the modeling

point of view, the two types of transistors differ in operation mode (strong inversion vs. accu-

mulation), transport mechanisms (band transport vs. various possibilities from band transport

to hopping), and technological choices (materials, fabrication methods). Yet, output and trans-

fer characteristics are comparable. Therefore, MOSFET-based models of transistors are used

as first-order approximations of OFETs in circuit simulation. Nevertheless, the OFET tech-

nology features numerous fabrication methods and materials for the various transistor layers.

This situation creates many factors complicating modeling because different transport mech-

anisms (band-like, hopping) and effects at the interfaces between the semiconductor and the

electrodes (presence of contact effects) or between the semiconductor and the insulating layer

(presence of traps, hysteresis) might arise. Hence, a generic simulation environment needs to

adapt to different modeling approaches and procedures for parameter extraction.

18 Chapter 2. Concepts of Low-Cost Organic Electronics

19

Chapter 3

Circuit simulations of low-cost organic circuits are useful in the development and optimization

of devices and processes. Simulations provide relevant performance figures during device

optimization. They can be used without fabricating and measuring real devices. However,

employing circuit simulation in this field requires accurate OFET models.

This chapter discusses models suitable for circuit simulation as well as procedures and

tools for extracting the respective model parameters. First, requirements are defined which

determine the strengths and weaknesses of transistor models. These requirements are useful

when comparing models and identifying their deficiencies. Next, existing OFET models pre-

sented in literature on device modeling are discussed. Finally, frequently used procedures and

tools for the extraction of transistor parameters are reviewed.

Transistor models need some properties in order to be useful in the simulation of OFET-

based logic circuits. Model performance in digital circuits usually depends on a small set

of parameters of the DC characteristics such as threshold voltage and drive current [24]. A

“good” agreement between ID -VDS measurements and simulation is traditionally considered

to be enough [25]. The level of accuracy can be defined by the mean-square error between

measurement and simulation [25, 26, 27]. However, users of transistor models prefer more

sophisticated rating criteria in order to identify the strengths and weaknesses of individual

models. Tsividis and Suyama [25] studied requirements on transistor models useful in the

simulation of circuits. Their research focused on model requirements for analog circuits but

the results can also be adapted to models for OFET-based digital circuits. In this work, the

idea of Tsividis and Suyama is adapted to the assessment of OFET devices. The adaption

consists of grouping the requirements into five sections, dropping criteria more important for

20 Chapter 3. OFET Modeling for Circuit Simulation

analog models, and adding new criteria dealing with the accuracy of predicted voltage levels,

noise margin, or stress effects. Good candidates for modeling OFET devices should comply

with as many requirements as possible of the following model quality chart (MQC):

⊲ I-V characteristics,

⊲ speed predictions for logic circuits,

⊲ propagation delays at the individual nodes within the circuit,

⊲ voltage levels and noise margin determinations,

⊲ a reasonable range of bias voltages and temperatures.

2 Capacitance Modeling — The model should include proper modeling of the transistor

capacitances like gate-source and gate-drain capacitances. The accurate simulation of

time-dependent voltage levels and signal shapes depends on the correct modeling of

these capacitances.

reflecting device structure and fabrication processing (channel thickness, number

of trap states, etc.).

⊲ Such a model would be especially useful in statistical circuit analysis where effects

of variations in fabrication and parameter distribution are accounted for.

⊲ In order to be of service in statistical circuit analysis, empirical parameters without

physical meaning should be avoided.

⊲ The model accuracy should not depend on the geometrical dimensions of each

device, so one set of model parameters should be valid for all devices of the same

type and fabrication process.

2 Parameter Extraction — The process of parameter extraction must be easy and straight-

forward:

⊲ The number of required test devices and measurement procedures for the parame-

ter extraction should be kept as small as possible.

⊲ Ideally, model parameters are directly resolved using analytical reasoning without

much computational effort.

3.2. Existing Models for OFETs 21

fail due to numerical instabilities.

2 Stress Effects — The candidate model should implement hysteresis effects present in

OFET devices like the threshold voltage shift due to bias stress [3, 28, 29, 30].

Although OFET-based modeling does currently not meet all of the above requirements,

the MQC is a useful tool in the discussion of strengths and weaknesses of different model-

ing approaches. Currently, the following issues prevent complete compliance with the MQC

criteria:

2 The physics of OFETs are not fully understood yet. Experiments presented in literature

are often carried out on devices fabricated on silicon wafers and by photolithographic

means. Such devices are not comparable to devices fabricated with low-cost manufac-

turing techniques. For the latter, fabrication speed and cost are more important than

device quality and repeatability.

of crystalline silicon transistors made of uniform and well-characterized materials [31].

Under these circumstances, deriving a small set of physics-related parameters is difficult

and often leads to empirical modeling of the devices.

2 OFETs can be fabricated using a variety of device structures and fabrication processes.

This situation gives rise to many individual effects. One example of such effects is the

series resistance between the electrodes and the transistor channel. Depending on the

device structure, the series resistance influences the transistor current [28, 32]. A large

variety of candidate materials for the semiconductor, the dielectric, and the interconnect

lines also leads to additional variables in the modeling process.

In the following, transistor models are presented which have already been applied to OFETs.

Some of these models were developed for more traditional semiconductor materials while

others are especially designed for specific types of OFETs. The following review makes

use of the model quality chart (MQC) in order to compare weaknesses and strengths of the

individual models. However, the reader should note that the models are difficult to compare

regarding accuracy as they have been developed for different device setups, i.e. different

material combinations, device structures, and fabrication methods.

22 Chapter 3. OFET Modeling for Circuit Simulation

The models reviewed in the following sections can roughly be divided into different cate-

gories. These categories are:

1. Models adapting well-known approaches for silicon transistors based on the shapes

of the output characteristics or structural similarities (Level-1 in Section 3.2.1, TFT

models in Section 3.2.2 and Section 3.2.3).

2. A model specifically developed for OFETs, i.e. the model of variable range hopping

(VRH) in four variants in Section 3.2.4.

3. Models sacrificing any physical background (table-based models in Section 3.2.5, Dres-

den model in Section 3.2.6) but instead focusing on quick and accurate reproduction of

measured output characteristics.

4. Models for ambipolar OFETs in Section 3.2.8, which are combinations of other models.

A special situation arises from Necliudov’s [32] application of the TFT model for amor-

phous silicon to OFETs (Section 3.2.3). Here, the generic adaption of a silicon-based model

is combined with OFET-specific contact effects. Brederlow and colleagues [33] developed a

similar approach but focused on a physics-related description of the contact effect and mod-

eled the intrinsic transistor with standard MOSFET equations. In this work, the model in [33]

has nevertheless been listed in the section dealing with the TFT model for amorphous silicon

as the model description was too short for a thorough analysis within the framework of this

thesis.

A popular and simple transistor model was developed by Shichman & and Hodges in the 1960s

for the general class of IGFETs (insulated gate field-effect transistors) [15]. In the following,

the name “Level-1 model” will also be used for this approach. The name originates from

SPICE, where Shichman-Hodges modeling is selected for MOSFETs by setting the transistor

parameter LEVEL=1 [34].

Some researchers employ the Level-1 equations as a first-order approximation of the out-

put characteristics of OFETs (e.g. [3, 35]). The equations are also used in Section 2.3.1 for a

discussion of the electrical behavior of OFETs.

Although the Level-1 model has been developed with operation in strong inversion mode

in mind, the resulting current-voltage relationship also approximates thin-film transistors op-

erating in accumulation mode as has been shown in [36].

3.2. Existing Models for OFETs 23

Fig. 3.1a shows the output characteristics of an OFET, which can be divided into three regions:

cutoff (not visible in the plot), linear, and saturation. In the following text, equations for the

three regions will be presented by use of an n-type transistor but the resulting equations are

applicable to both n-type and p-type devices.

For an n-type transistor with true Level-1 behavior, no current flows for VGS less than the

threshold voltage VT . The device is then in the cut-off region (see Fig. 3.1b). Above threshold,

the current increases with a square-law dependence on VDS in the linear region until it reaches

the boundary between linear and saturation region (shown by the dotted line in Fig. 3.1a). In

the saturation region, the current is proportional to the drain-source voltage.

ID ID

VDS = VGS − VT

VGS ↑ Region Region Region

VT VDS = const

0 VDS 0 VGS

Fig. 3.1: Schematic output characteristics of a transistor with Level-1 behavior: a) output

characteristics ID vs. VDS with linear and saturation region separated by a dotted curve, and

b) linear transfer characteristic ID vs. VGS with threshold voltage VT .

The equations of Level-1 transistors were already introduced in (2.1) but will be repro-

duced here in order to separate the different operation regions:

1. Cutoff region:

2. Linear region:

W VDS

ID = µ·Cis · VGS − VT − VDS ·(1+λVDS ) with 0 < VDS < VGS −VT (3.2)

L 2

24 Chapter 3. OFET Modeling for Circuit Simulation

3. Saturation region:

1 W

ID = µ · Cis · (VGS − VT )2 · (1 + λVDS ) with 0 < VGS − VT < VDS (3.3)

2 L

The parameters used in (3.1) to (3.3) are µ for the charge-carrier mobility, Cis for the

capacitance per unit area of the gate dielectric, VT for the threshold voltage, λ for the channel-

length modulation parameter, W and L for the width and length of the transistor channel. For

convenience reasons in hand calculations, the process conductance parameter KP [37] was

introduced as

KP = µCis . (3.4)

The device conductance parameter β further extends KP by taking into account the geometry

of the transistor. It is defined as

W W

β = KP = µCis . (3.5)

L L

The process conductance parameter KP reflects the driving capabilities of the transistor

device. The threshold voltage on the other hand defines how much gate-source voltage is

needed to induce charge carriers in the transistor channel. The channel-length modulation

parameter has been introduced in the original IGFET equations to account for a channel-

length reduction in saturation. This reduction is associated with the pinch-off of the transistor

channel at some point near the drain electrode. The pinch-off leads to a reduction of the

effective channel length which in turn increases the slope of ID vs. VDS in the saturation

region. The value of λ defines this slope according to (3.3). λ = 0 corresponds to a slope of

zero in the saturation region.

Reasonable parameter values for Level-1 devices are given in Table 3.1. As there is not just

one mainstream OFET technology but many different processes currently in the development

stage, parameter values for the various fabrication technologies considerably differ. Therefore,

it is not possible to provide typical values, and Table 3.1 can only provide a general idea of

reasonable parameter ranges.

Parameter Value

process conductance KP < 9 pA/V2

threshold voltage VT 0,2 V

channel-length modulation λ 5 · 10−3 1/V

using Fig. 3.2, where output and transfer characteristics of variations of all three Level-1 pa-

3.2. Existing Models for OFETs 25

rameters are shown. The reference device was an n-type FET with the following parameters:

KP = 1 nA/V2 , VT = 2 V, λ = 0, W/L = 2000. The parameters have been chosen for demon-

stration purposes. In Fig. 3.2a-b, the effect of varying the process conductance is depicted.

Increasing KP from 1 pA/V2 to 1.5 pA/V2 will proportionally increase the drain current ID .

In Fig. 3.2c-d, the influence of the threshold voltage is demonstrated. Here, VT is raised

from 2 V to 10 V. The impact of this increase is best seen in the ID vs. VGS plot where

the onset of drain current shifts from VGS = 2 V to 10 V. In Fig. 3.2e-f, the impact of the

channel-length modulation λ is shown.

3.2.1.2 Discussion

In Table 3.2, a rating of Level-1 modeling with respect to the model quality chart (MQC)

from Section 3.1 is shown. Due to the multitude of materials and processing routes, there is

no uniform shape of the current/voltage characteristics of OFET devices [30]. Therefore, the

accuracy of the Level-1 approach has been rated from bad to medium. It can adequately repro-

duce OFET types where the mobility only weakly depends on the gate-source voltage. Other

modeling approaches are better suited for devices with e.g. variable mobility. Modeling of

capacitances is not part of the basic equations. It should be noted, however, that Level-1 imple-

mentations in SPICE simulators include nonlinear modeling of capacitances which is similar

to OFET-related capacitance values expectable from numerical analysis (see Section 3.2.4.2).

As the Level-1 model is based on a physical background (gradual channel approxima-

tion) and only few parameters are necessary in the equations, compactness of the model has

been rated as good. Numerous approaches can be used for deriving these parameters (see

Section 3.3.1). Therefore, parameter extraction has also been rated as good. Stress effects are

not included in the model.

Requirement Rating

Accuracy bad to medium

Capacitance Modeling not included

Compactness good

Parameter Extraction good

Stress Effects not included

In literature on modern MOSFET modeling [38], the Level-1 approach is only considered

as a convenient first-order approximation because the relatively simple equations facilitate

parameter extraction. More advanced models require concurrent fitting of several parameters

to more sophisticated equations, which complicates the extraction process.

26 Chapter 3. OFET Modeling for Circuit Simulation

a) b)

3.5u 3.5u

KP =1.0 pA/V2 KP =1.0 pA/V2

3.0u KP =1.5 pA/V2 3.0u KP =1.5 pA/V2

ID [A]

2.0u 2.0u

ID [A]

40 V

1.5u 1.5u

1.0u 30 V 1.0u

0.5u 20 V 0.5u

VDS = 50 V

0.0u 0.0u

0 10 20 30 40 50 −10 0 10 20 30 40 50

VDS [V] VGS [V]

c) d)

VT = 2 V VT = 2 V

VT = 10 V VT = 10 V

2.0u 2.0u

1.5u 1.5u

ID [A]

ID [A]

1.0u 1.0u

0.5u 0.5u

VDS = 50 V

0.0u 0.0

0 10 20 30 40 50 −10 0 10 20 30 40 50

VDS [V] VGS [V]

e) f)

80n

λ = 0.000 1/V

70n 2.5u λ = 0.005 1V

VGS = 10 V

60n

2.0u

50n

ID [A]

ID [A]

40n 1.5u

30n

1.0u

20n

0.5u

10n λ = 0.000 1/V

λ = 0.005 1/V VDS = 50 V

0n 0.0u

0 10 20 30 40 50 0 10 20 30 40 50

VDS [V] VGS [V]

Fig. 3.2: ID vs. VDS and ID vs. VGS for variations of the Level-1 parameters: a-b) variation

of KP , c-d) variation of VT , and e-f) variation of λ.

3.2. Existing Models for OFETs 27

The Level-1 model presented in Section 3.2.1 was designed for crystalline silicon transistors

and does not account for VGS -dependent mobilities. Therefore, more sophisticated modeling

approaches for organic transistors have been presented in literature such as the grain bound-

ary model for polycrystalline transistors. This model is based on the fact that vapor-deposited

organic semiconductors like pentacene organize themselves into grains of single-crystalline

structure [39]. Charge carriers are impeded by traps when they move across boundaries of

adjacent grains. Those traps can cause carrier scattering and momentum transfer to phonons

in the crystal [39]. The existence of traps leads to trapping of carriers, which in turn is re-

sponsible for a depletion of charge carriers at the grain boundaries [40] and the formation of

a barrier potential.

Polycrystalline silicon thin-film transistors (Psi-TFTs) show comparable behavior. In

these devices, the mobility is described by an empirical equation

1 1 1

= + , (3.6)

µeff µg µgb

with µeff being the effective mobility (i.e. net mobility), µg the mobility inside the single-

crystalline grain, and µgb the mobility obtained at the grain boundaries.

The drain current above threshold can be calculated with

VDS

W

Z

Id = {Cis [VGS − VT − V (x)] · µeff } dV, (3.7)

L

0

where V (x) is the drain-source voltage at position x along the length of the channel. The

other variables have their usual meaning.

Popular simulation models for polycrystalline silicon do not provide an exact solution to

(3.7) but instead express the mobility by an empirical equation, e.g. [41] for the Psi-TFT

model from the Rensselaer Polytechnic Institute (RPI, Troy, NJ, USA). Such an approach

eventually leads to an adaption of the basic model presented in Section 3.2.1 with a VGS -

dependent mobility [42]. The nature of charge transport in organic semiconductors is still a

matter of debate. Nonetheless, some groups (e.g. Horowitz and co-workers [43], Frisbie and

co-workers [44, 45]) established theories for organic crystals and polycrystalline structures

where charge transport within a single grain can be viewed as band-like. Transport across

grain boundaries and the semiconductor interface to the electrodes, however, is impeded by

the presence of traps.

The Psi-TFT model has been used in [46] for modeling of the above-threshold current of

OFETs.

28 Chapter 3. OFET Modeling for Circuit Simulation

In the following, simplified equations for the RPI Psi-TFT model will be presented. A more

detailed description can be found in [47]. The RPI model assumes the effective charge-carrier

mobility µeff to be determined by an empirical law

1 1 1

= ′ + , (3.8)

µeff µ1 µ0

with µ0 being an upper mobility limit for high gate biases similar to µg in (3.6) and µ′1 deter-

mined by an empirical power law for low VGS values as

m

µ

µ′1 ∼ µ1 VGST . (3.9)

Here, µ1 is the low-field mobility and mµ is a mobility parameter. Both quantities can be

extracted from current-voltage measurements. For convenience reasons, VGST = VGS − VT is

used.

The drain current is composed of three contributors:

Fig. 3.3 shows a schematic plot1 of the drain current and its three contributors in logarith-

mic scale vs. the gate-source voltage VGS . The derivation of the equations for Ileak , Isub , and

Ia are detailed by Jacunski and colleagues [47]. In this work, only simplified equations will

be presented in order to show the VGS - and VDS -dependence of the contributing currents.

The subthreshold leakage current Ileak in the RPI model has not been used in the modeling

of OFETs so far. Therefore, the equations will not be reproduced here.

The subthreshold current in the Psi-TFT model reads

W 2 VGST −VDS

Isub = µs · Cis (ηi Vth ) exp 1 − exp . (3.10)

L ηi Vth ηi Vth

Here, µs is the subthreshold mobility and ηi is the subthreshold ideality factor. Both param-

eters are extracted using measurements of the drain current. The other parameters have their

usual meaning.

1

Model data: µeff = 1 · 10−3 cm2 /Vs, Cis = 1 · 10−7 F/cm2 , VT = 1 V, αsat = 1.1, µs = 1 · 10−11 cm2 /Vs,

ηi =3.34, I0 = 1 · 10−13 A, W/L = 1000. A simple fitting equation for the leakage current has been used, which

reads Ileak = I0 exp(−(VGS − VT )/6).

3.2. Existing Models for OFETs 29

10.0u

Isub

1.0u

100.0n

10.0n Ia

ID [A]

1.0n

100.0p

10.0p

1.0p

100.0f

Ileak

10.0f

−4 −2 0 2 4 6 8 10

VGS [V]

The slope of the subthreshold current Isub in (3.10) in decimal logarithmic scale is given by

log e/(ηi Vth ). For OFETs, it is the reciprocal of the subthreshold swing [48] or subthreshold

slope [49] S. [49] defines the subthreshold slope as the necessary variation of the gate-source

voltage for modulating the subthreshold current by one decade. Alternatively, the IEEE stan-

dard on the characterization of OFETs [48] defines the subthreshold swing as the maximum

slope of the logarithmic transfer characteristic in the subthreshold region. The subthreshold

slope is given in V/dec and typically ranges from 1 to 5 V/dec for p-type organic semicon-

ductors [49]. In comparison to crystalline silicon with a typical subthreshold slope of approx-

imately 60 mV/dec at room temperature, a large range of gate-source voltage is required to

achieve low off currents [49].

2

W VDS

µ C VGST VDS − for VDS < αsat (VGST )

eff is L 2αsat

Ia = (3.11)

(VGST )2 αsat

µeff Cis W for VDS ≥ αsat (VGST )

L 2

Here, µeff is the VGS -dependent mobility from (3.8), αsat is an empirical parameter accounting

for a VGS -dependent modulation of the transition point between the linear and the saturation

region.

30 Chapter 3. OFET Modeling for Circuit Simulation

1

ID = Ileak + . (3.12)

1 1

+

Isub Ia

With the reciprocal subterm, a unified equation for the subthreshold region, above-threshold

region and transition region between the two can be used.

The effective control voltage VGST used in the RPI model is defined by

VGS − VT

for VGS − VT > 2ηi Vth

VGST = . (3.13)

2ηi Vth else

Here ηi is the subthreshold ideality factor introduced in (3.10). (3.13) effectively limits

VGST to values above 2ηi Vth . Without limiting VGST , values close to zero could be reached in

(3.11). These values would introduce an incorrect singularity in the transition region.

A reasonable parameter set for a P3HT transistor in top-gate configuration is listed in

Table 3.3 (details on how the values were obtained are given in Section 4.3.6).

Fig. 3.4 provides plots where the parameters mµ and αsat are varied. Reference parameters

for the plots were αsat = 1.0, mµ = 0.0, VT = 2.0 V. These were chosen so that the drain

currents of the Psi-TFT device and the Level-1 device presented in Section 3.2.1 are identical.

By varying αsat and mµ , the changes introduced by the Psi-TFT equations with respect to the

original Level-1 modeling can be studied.

3.2.2.2 Discussion

A rating of the polycrystalline grain boundary model is presented in Table 3.4. The model

takes a VGS -dependent mobility into account. Therefore, accuracy has been rated as good (see

Section 4.3.6 for an example of model accuracy). Modeling of capacitances is not included

in the model. Compactness has been rated as good because only a small number of parame-

ters is needed for modeling the above-threshold behavior. One can argue, however, that the

underlying RPI model uses only an “effective medium approach” [50] where the stochastic ar-

rangement of grains of different sizes is modeled by a single effective medium with equivalent

properties. Hence, the model equations can be considered as statistical descriptions. This fact

complicates finding the relationship between model parameters and those parameters which

reflect device structure and fabrication processes. Nevertheless, compactness has been rated

as good as only a small amount of parameters is necessary. Parameter extraction is difficult

because of the bias-dependent mobility as will be discussed in Section 3.3.2. This property

leads to a rating of medium. Similar to Level-1 modeling, stress effects are not included in

3.2. Existing Models for OFETs 31

Table 3.3: Psi-TFT parameters for top-gate p-type P3HT device (other parameters not used).

Parameter Value

capacitance Cis per unit area 1 · 10−7 F/cm2

low-field mobility µ1 2.5 · 10−5 cm2 /Vs

zero-bias threshold voltage VT 2.9 V

saturation variation parameter αsat 0.8

low-field mobility exponent mµ 0.886

channel-length modulation parameter λ 0.005 V−1

a) b)

αsat = 1.0 αsat = 1.0

αsat = 0.5 αsat = 0.5

2.0u 2.0u

1.5u 1.5u

ID [A]

ID [A]

1.0u 1.0u

0.5u 0.5u

0.0u 0.0u

0 10 20 30 40 50 0 10 20 30 40 50

VDS [V] VGS [V]

c) d)

mµ = 0.0 mµ = 0.0

4.0u 4.0u

mµ = 0.1 mµ = 0.1

3.5u 3.5u

3.0u 3.0u

ID [A]

ID [A]

2.5u 2.5u

2.0u 2.0u

1.5u 1.5u

1.0u 1.0u

0.5u 0.5u

0.0u 0.0u

0 10 20 30 40 50 0 10 20 30 40 50

VDS [V] VGS [V]

Fig. 3.4: ID vs. VDS and ID vs. VGS for variations of the Psi-TFT parameters αsat and mµ :

a-b) variation of αsat , c-d) variation of mµ .

32 Chapter 3. OFET Modeling for Circuit Simulation

the model.

Requirement Rating

Accuracy good

Capacitance Modeling not included

Compactness good

Parameter Extraction medium

Stress Effects not included

The effective medium approach has also been used for studying the grain-size-dependent

mobility for pentacene-based OFETs [51] in order to yield an effective mobility

1

µeff = µg , (3.14)

1 + nβ exp(qVB /kT )

with µg being the grain intrinsic mobility, n the number of grain boundaries along the chan-

nel, β the ratio between an effective grain-boundary size and the channel length, and VB the

potential barrier between grains. For polycrystalline silicon TFT (Psi-TFT) devices, similar

relationships have been exploited to derive closed-form drain-current equations in the form of

[52]

W

ID = µeff Cis (VGS − VT )VD . (3.15)

L

Here, the drain current in the linear region is modeled. Results in [51] suggest that µeff non-

linearly depends on the effective grain size and the gate-source voltage. Studies on the VGS

dependence of Psi-TFT devices in [52] yielded a sixth-order polynomial needed for modeling

of the potential barrier VB (VGS ). To the knowledge of the author of this work, this model

has not been applied to polycrystalline OFETs so far. It is suggested to further explore this

approach.

Necliudov and colleagues [32] describe a model which improves the fitting between the Level-

1 model and experimental data for vapor-deposited pentacene OFETs. The model is based on

the assumption that above threshold, most of the charge carriers induced in the channel are

trapped and only a small fraction contributes to charge transport. A VGS -dependent mobility

reflects this property. The model is derived from the TFT model for amorphous silicon TFTs

(a-Si TFT). In a-Si TFTs, no long-range order of the silicon material exists. Instead, the atoms

are organized in a random network, which leads to many energy states in the forbidden band-

gap. These states are localized and statistically distributed. They arise from unterminated

3.2. Existing Models for OFETs 33

bonds or variations of bond angle and bond length. Fig. 3.5 provides a schematic view of

the energy band diagrams of crystalline and amorphous silicon. In crystalline silicon, there is

a clear band gap without states between the edges of the valence band (EV ) and conduction

band (EC ). In amorphous silicon, no clearly-defined band gap exists.

a) crystalline

density of states

band band gap band

EV EC energy

b) amorphous

density of states

band states band

EV EC energy

Fig. 3.5: Schematic energy band diagram of a) crystalline silicon and b) amorphous silicon

(adaption from [53]).

Charge carriers trapped in band-gap states do not contribute to the drain current of the

FET. Hence, the effective mobility of a-Si TFTs is below the one of single-crystalline silicon

devices. Moreover, it depends on the gate voltage because at higher gate voltages, more trap

states are filled and therefore, more charge carriers of the ones injected at the source electrode

can contribute to the current flow.

γ

VGS − VT

µ = µ0 . (3.16)

VAA

Here, µ0 , VAA , and γ are fitting parameters obtained from experimental data, where γ is a

power parameter and VAA is the characteristic voltage for the charge-carrier mobility [54].

34 Chapter 3. OFET Modeling for Circuit Simulation

[32] reported results for top-contact (TC) and bottom-contact (BC) pentacene devices.

Bottom-contact devices showed nonlinear output characteristics at gate-source voltages around

zero. These devices were modeled with constant source and drain series resistors and pairs of

Schottky diodes. Fig. 3.6 shows the configuration. The approach is an adaption of the RPI

model for amorphous silicon thin-film transistors (RPI a-Si TFT) [55] to organic transistors.

It is a fitting model which neglects the physical background of the equations.

RD

RS

Fig. 3.6: Equivalent circuit of a bottom-contact OFET with diodes and series resistors for

modeling non-linear contact resistance.

The Schottky diodes are modeled with an empirical extension to the basic Shockley equa-

tion. The extension introduces an ideality factor η which accounts for the influence of non-

ideal effects (η > 1) on the diode current [50]. This current I is

V

I = IS exp −1 . (3.17)

ηVth

Here, IS is the saturation current, V the voltage drop across the diode, and Vth is the thermal

voltage. η determines the steepness of the I-V characteristic of (3.17).

3.2. Existing Models for OFETs 35

Necliudov and colleagues obtained contact resistances in the range of 50 kΩ to 100 kΩ for

channel widths of 220 µm and a diode ideality factor η = 10 for a pentacene device with bot-

tom contacts. Detailed information on the parameters necessary for calculating the saturation

current is not given in [32]. Nevertheless, adequate extraction procedures for standard a-Si

TFTs are available e.g. in in [56, 57].

Table 3.5 provides model parameters for pentacene devices fabricated in both bottom-gate

top-contact (TC) and bottom-gate bottom-contact (BC) configuration [32].

Table 3.5: Typical model parameters of top-contact (TC) and bottom-contact (BC) pentacene

OFETs [32].

Type W/L RS,D VT µ0 γ VAA η

2

TC 220 µm /30 µm 100 kΩ 5 V 10 cm /Vs 0.45 300 kV -

BC 220 µm /20 µm 50 kΩ 13 V 10 cm2 /Vs 0.38 19 kV 10

3.2.3.3 Discussion

The calculated mobility of a-Si TFTs in (3.16) effectively resembles the mobility calcula-

tion for polycrystalline silicon (Psi-TFT) in (3.9) so that comparable results can be expected.

However, the Psi-TFT model also includes a variation factor αsat for the onset of saturation

(see (3.11)) in the output characteristics ID vs. VDS . The a-Si RPI model also includes such a

factor, but Necliudov and colleagues did not use it maybe because αsat is difficult to separate

from contact effects.

In Table 3.6, a rating of the model for a-Si TFTs according to the model quality chart

defined in Section 3.1 is provided. The accuracy of the model with respect to pentacene tran-

sistors is good as demonstrated in [32]. Modeling of capacitances and bias-induced stress is

not included in the model. The model needs only six technology parameters (RC = RS = RD ,

η, VT , µ0 , γ, VAA ), which increases its compactness (rating good). Contact effects influence

the shape of current-voltage characteristics in a non-linear way. Therefore, parameter extrac-

tion schemes which rely on curve fitting are difficult to employ. This property complicates

parameter extraction (rating bad). Necliudov et al. point out that they use the contact resistors

and diodes mainly to approximate the shape of the output characteristics in the linear region.

However, a more precise procedure would consist of measuring the contact resistances and

barriers beforehand and compensating their effects in the calculations of the other parameters.

Moreover, it was pointed out elsewhere [58] that although a FET with double, opposite diodes

at the electrodes provides a good I/V description, it lacks a physical basis. Therefore, other

36 Chapter 3. OFET Modeling for Circuit Simulation

research teams use transistor configurations with only two Schottky diodes instead of four in

order to model non-linear contact effects. One diode is placed at the source electrode and the

other at the drain electrode in opposite direction. For example, Brederlow and colleagues [33]

proposed a configuration with a transistor2, two contact resistors and two contact Schottky

diodes, as shown in Fig. 3.7. In normal operation, one diode is forward-biased while the other

operates in reverse breakdown operation. As an additional feature, the barrier height of each

diode is assumed to be gate-voltage-dependent in [33]. Details about the VGS dependence of

the contact diodes can be found in the cited paper. Procedures for dealing with non-linear

contact effects and for extracting diode parameters can be found e.g. in [46, 59].

Gate

Source Drain

Fig. 3.7: Equivalent circuit for contact model with reverse- and forward-biased diodes (adap-

tion from [33]).

Requirement Rating

Accuracy good

Capacitance Modeling not included

Compactness good

Parameter Extraction bad

Stress Effects not included

uration which were fabricated using lithographic processes. In a recent work by Bartzsch

et al. [60], the a-Si TFT model was successfully applied to all-printed p-type F8T2 transis-

tors. The F8T2 devices could be modeled with ohmic contact resistance (RS = RD = 70 kΩ).

Modeling of contact diodes was not needed for reproducing the measured output characteris-

tics. The reported device parameters are somewhat unexpected. As an example, VAA = 1 GV

and γ = 1 · 10−10 of the investigated device suggest that the gate-source voltage does not

noticeably affect the charge-carrier mobility in (3.16).

2

However, the transistor is modeled by a MOSFET model instead of a TFT model. The approach is focused

on the modeling of the contacts.

3.2. Existing Models for OFETs 37

In the following, different interpretations of the variable range hopping (VRH) model are

presented. In the VRH approach, thermally activated tunneling of carriers between localized

states, i.e. hopping, is assumed. The first analytical treatment of VRH-driven charge transport

in organic semiconductors was carried out by Vissenberg and Matters [61]. Meijer and co-

workers [62] provided qualitative equations dealing with the VRH-controlled current in the

linear region of OFETs. Calvetti et al. then provided full treatment of output characteristics

of OFETs based on the VRH approach, including calculations of device capacitances [63].

The model treated linear and saturation region and was later enhanced with equations for

subthreshold current by the same group [64].

In another approach, Fadlallah and colleagues [65] derived similar equations as in [63].

This time, however, the Universal Mobility Law (UML) described by Brown et al. in [3] was

used.

More recent studies by Schliewe and co-workers [66] are also based on the VRH approach,

but with emphasis on modeling the effect of the bulk conductivity on the drain current in the

linear region.

The switch-on model from Meijer and colleagues [62, 67] approaches transistor behavior

by use of a switch-on voltage VSO instead of the threshold voltage VT . VSO represents the

gate voltage at which accumulation of charge carriers begins (see also discussion on p. 59).

In the switch-on model, the conductivity of the transistor channel is determined using an

adaption of the variable-range hopping model [61]. The adaption employs the percolation-

defined conductivity [67]

! TT0

δNt (T0 /T ) 4

sin(π TT0 )

σ(δ, T ) = σ0 (3.18)

(2α)3BC

tion of the temperature-dependent charge carrier occupation, Nt is the density of localized

states, T0 is a parameter representing the width of the exponential distribution, α is an effec-

tive overlap parameter between localized states, and BC is a critical number for the onset of

percolation (2.8 in three-dimensional amorphous systems).

38 Chapter 3. OFET Modeling for Circuit Simulation

Meijer and colleagues calculated the drain current from (3.18) according to:

4 “ ” T0

W VDS εs ε0 σ0

T

q

2kB T0 ( TT0 ) sin π TT T

IDS = L q 2T0 −T εs ε0

× (2α)3 BC

0

(3.19)

hq i 2TT0 −1

εs ε0 Ci (VGS −VSO )

× 2kB T0 εs ε0

.

Here, εs and ε0 are the relative permittivity of the semiconductor and the free permittivity of

vacuum, respectively.

In the switch-on model, the four parameters σ0 , α−1 , T0 , and VSO are used for modeling

of the output characteristics. Meijer’s results [67] show agreement between experimental

data and simulations of poly(2,5-thienylen vinylene) (PTV), solution-processed pentacene,

and poly(3-hexylthiophene) (P3HT). Typical values for samples of these semiconductors are

given in Table 3.7.

Table 3.7: Representative parameters [67] for solution-processed OFETs modeled by the Mei-

jer switch-on model.

Material T0 [K] σ0 [106 S/m] α−1 [Å] VSO [V]

PTV 382 5.6 1.5 1

Pentacene 385 3.5 3.1 1

P3HT 425 1.6 1.6 2.5

While Meijer and co-workers used their VRH equations only as a tool to study the physical

properties of different materials, Calvetti and colleagues [63] from the University of Brescia,

Italy, elaborated an analytical model useful for circuit simulators like SPICE. The drain current

reads

W T

(VGS − VSO )2T0 /T − (VGS − VDS − VSO )2T0 /T

ID = β (3.20)

L 2T0

for an n-type device in the linear region (VGS − VSO > VDS ) and

W T

ID = β (VGS − VSO )2T0 /T (3.21)

L 2T0

in the saturation region for VGS − VSO ≤ VDS . The reader should note that in the original

publication [63], the flat-band voltage VF B is used for denoting the onset of accumulation. For

consistency reasons, however, VSO will be used in the following. The parameter β is defined

3.2. Existing Models for OFETs 39

as T0 /T

2T /T −1

(T0 /T )4 sin(πT /T0 )

σ0 T Cis 0

β= . (3.22)

q 2T0 − T (2kB T0 εs ε0 )T0 /T −1 (2α)3 BC

In this equation, the parameters have their meaning as defined in Section 3.2.4.1. Calvetti et al.

also used the parameters in Table 3.7 and assumed εs = 3.0 as well as Cis = 1.3 × 10−4 F/m2 .

The Brescia model also treats the calculation of dynamic model behavior by specifying

equations for the induced charges QS , QD , and QG at the terminals source, drain, and gate.

The calculations give rise to somewhat lengthy expressions. As an example, QG reads

QGnum

QG = −W LCis , (3.23)

QGden

T 2T0

+1

2T0

+1 kB T 2T0 2T0

QGnum = (VGST

T

− VGDT

T

)+ (VGST

T

− VGST

T

), (3.24)

2T0 + T q

T 2T0 2T0

2T kB T0 2TT0 −1 2T0

−1

QGden = (VGST

T

− VGDT

T

)+ (VGST − VGDT

T

). (3.25)

2T0 2T0 − T q

Here, VGST = VG − VS − VSO , and VGDT = VG − VD − VSO . From QG , the gate-source

and gate-drain capacitances can be derived using

QG QG

CGS = , CGD = . (3.26)

VGS VGD =const VGD VGS =const

Fig. 3.8 shows a comparison of calculated capacitances CGS and CGD in the Brescia VRH

model with capacitances calculated by the Meyer model used in MOSFET models, both nor-

malized to Cg = W LCis . Gate charge in the Meyer MOSFET model was calculated using

2 V 3 − VGDT

3

QG = Cis GST

2 2

. (3.27)

3 VGST − VGDT

The plots were calculated for an OFET with pentacene as active layer. As indicated by the

plots, conventional Meyer model predicts capacitances with slightly different values than com-

puted with the Brescia capacitance model. The reader should note, however, that these calcu-

lations do not include the contribution of the overlap capacitance of the source/drain fingers

(see Fig. 2.4). If e.g. the drain/source fingers are assumed to have the same widths as the

length of the channel, additional overlap capacitances CGSO = CGDO = Cg /2 would have

to be included. Consequently, the curves in Fig. 3.8 would have to be shifted up by 0.5. A

comparison of the curves shows that Meyer-based modeling of capacitances already provides

reasonable first-order approximation. Meyer-modeling of CGS will lead to voltage-dependent

capacitances (without considering overlap capacitances) which are 2% to 12% below the val-

ues predicted by the Brescia model. For CGD , the Brescia-modeled values can lag behind the

40 Chapter 3. OFET Modeling for Circuit Simulation

0.7 Meyer

VRH Meyer

VRH

0.4

0.65

0.3

CGS /Cg

CGD /Cg

0.6

0.2

0.55 0.1

0

−30 −25 −20 −15 −10 −5 −30 −25 −20 −15 −10 −5

VGS [V] VGS [V]

Fig. 3.8: Comparison of capacitance ratios CGS /Cg and CGD /Cg calculated with the Brescia

(solid lines) and Meyer model (stars), respectively. T0 = 385 K (for pentacene) was used in

the VRH calculations.

Calvetti and colleagues also derived equations for the subthreshold region [64]. These

equations were found by numerical simulations of the two-dimensional potential and charge

distribution within the channel in the subthreshold region. The simulations showed that in

the subthreshold region, the conductivity is modulated by the depletion of the carriers in the

semiconductor layer. Moreover, the drain current in subthreshold operation can be determined

using the gradual channel approximation. However, the resulting relations are quite compli-

cated and will not be reproduced here. They can be found in [64].

The model from Fadlallah and co-workers [65] is based on the observation by Brown and

colleagues [3] that the conductivity σ of charge carriers in a semiconductor film is given by

an empirical equation

σ = K ′ NAγ , (3.28)

where NA is the doping-induced charge density in the semiconductor, K ′ and γ are fitting

parameters. The charge-carrier mobility µ is then approximated by the simple power law

µ = KNAγ−1 . (3.29)

3.2. Existing Models for OFETs 41

Here, K is another fitting parameter. Brown et al. showed that this empirical power law can

be applied to a variety of polymer materials. Hence, the law is referred to as the Universal

Mobility Law (UML) in [65]. (3.29) can be employed for the mobility in the gradual channel

approximation in order to get

K W Cis2m+1 h

2(m+1) 2(m+1)

i

ID,lin = V − (V GST − V DS ) (3.30)

(2m + 1)(2m + 2) L (2kB T ε0 εs )m GST

for the linear region (VGS − VT > VDS ) of a p-type OFET. Here, m = γ − 1 and the voltage

VGST = VGS − VT while the other parameters have their usual meaning. The drain current in

the saturation region (VGS − VT < VDS ) is given as

K W Cis2m+1

ID,sat = (VGS − VT )2m+2 [1 + λ(VDS − VGST ]. (3.31)

(2m + 1)(2m + 2) L (2kB T ε0 εs )m

The cut-off current (for VGS > VT ) is assumed to be independent of both the drain-source

voltage and the gate-source voltage and is modeled by

I00 is the current density in the cut-off region and W is the channel width of the device.

Modeling of capacitances on the basis of the UML model is also presented in [65]. The

threshold voltage VT was assumed to be equivalent to the switch-on voltage VSO of the device

so to get the total charge on the gate electrode of

2m+3 2m+3

(2m + 2) VGDT − VGST

QG = Cis W L · 2m+2 2m+2 . (3.33)

(2m + 3) VGDT − VGST

VGST ≥ 0 and VGDT ≥ 0 is necessary in the calculations in order to yield a correct charge in

(3.33). The gate-source capacitance is

∂QG

CGS =

∂VGS VGD =const

2m+1 2m + 2

= −Cis · W · L · VGST ·

2m + 3

2m+3 2m+2 2m+3

(2m + 2)VGDT − (2m + 3)VGDT VGST + VGST

× 2m+2 2m+2 2 . (3.34)

(VGDT − VGST )

42 Chapter 3. OFET Modeling for Circuit Simulation

∂QG

CGD =

∂VGD VGS =const

2m+1 2m + 2

= −Cis · W · L · VGDT ·

2m + 3

2m+3 2m+2 2m+3

(2m + 2)VGST − (2m + 3)VGST VGDT + VGDT

× 2m+2 2m+2 2 . (3.35)

(VGDT − VGST )

Fadlallah and colleagues carried out validations of the Eldo implementation in order to

test the convergence in transient simulations of a ring oscillator. The ring oscillator consisted

of inverters in diode configuration (load transistor with gate and drain at negative supply, both

transistors with PTAA as semiconducting material). A comparison between measured and

simulated oscillation signals was not given in the publication.

The UML model and the Brescia model are almost identical if the following parameter

translation is used:

T0 4

! TT0

sin(π TT0 )

σ0 T T0

K= , m= − 1. (3.36)

q (2α)3BC T

The UML model provides treatment of the channel-length modulation while the Brescia

model contains more sophisticated equations dealing with the subthreshold currents. More-

over, the Brescia model works with the term 2kB T0 εs ε0 while the UML model resorts to

2kB T εs ε0 .

In another approach, Schliewe and colleagues [66] derived VRH equations for the steady-state

drain current:

W aCis b+2

r (VSO − VGS ) − r b+2 (VSO − VGD ) .

ID = − (3.37)

L b+2

Here, a and b are parameters derived from the relationship between the mobility and the gate

voltage

µ(x) = a(VSO − VGx )b . (3.38)

VGx represents the voltage between the gate and the position x along the semiconductor-

insulator interface, VSO is the switch-on voltage. r is a step function which allows using one

3.2. Existing Models for OFETs 43

(

V, V ≥0

r(V ) = (3.39)

0, V < 0.

K Cis2m

a= , b = 2m. (3.40)

2m + 1 (2kB T ε0 εs )m

3.2.4.5 Discussion

The analytical VRH models presented in this section are physics-based models which qualita-

tively predict transistor behavior. In this way, they differ from other models discussed earlier

in this chapter. The other models simply extend existing approaches developed for inorganic

technologies.

Table 3.8 provides a rating of the physical models with respect to the model quality chart

presented in Section 3.1. Accuracy has been rated as good according to the data provided in

[62, 63, 65, 66, 67]. Modeling of capacitances is included. The physical models work with a

limited set of parameters, which improves their compactness and leads to a rating of good in

this category. Parameter extraction has been rated as medium because it is more difficult than

in the case of Level-1 modeling. Stress effects are not included in any of the analytical VRH

models.

Requirement Rating

Accuracy good

Capacitance Modeling good

Compactness good

Parameter Extraction medium

Stress Effects not included

Table-based models avoid the problems of parameter extraction. These models store tables

of output characteristics in a compressed form. The tables are then used in the simulations in

order to derive the behavior of a device. Such approaches completely disregard physics-based

parameters and instead focus on accurate reproduction of measured values.

44 Chapter 3. OFET Modeling for Circuit Simulation

In Table 3.9, table-based models have been rated according to the model quality chart

developed in Section 3.1. Accuracy in reproducing a reference device is excellent because

its characteristics are stored in a table. Modeling of capacitances can also be carried out

accurately by use of tables if the simulation environment supports tables for nodal charges

(e.g. Tanner T-Spice [68]). Parameter extraction is not required.

Compactness has been rated as bad because table-based modeling generally does not pro-

vide parameters which can be accessed by the users. Moreover, these internal parameters

are without physical meaning or relations to device structure. This fact complicates those

statistical modeling approaches where correlations between variations of physical and/or ge-

ometrical device properties and output characteristics are analyzed. Therefore, stress effects

are also difficult to include in the models.

Owing to the missing influence on the output characteristics, table-based modeling is not

suited for the exploratory study of parameter variations. However, it can be a viable tool in

combination with two-dimensional transistor simulators because it provides rapid modeling

without the need to derive model parameters.

Requirement Rating

Accuracy good

Capacitance Modeling good

Compactness bad

Parameter Extraction not needed

Stress Effects not included

Gay and colleagues [69] from the Dresden University of Technology developed a model which

completely disregards the physical background of modeling. Instead, it resorts to powerful

fitting functions and focuses on the simulation of analog circuits which require accurate tran-

sistor models [25].

The Dresden model is based on the observation that the individual curves of the output charac-

teristics ID vs. VDS are similar in shape. A curve for a particular gate voltage VGS,0 is used as

a template and is described by a reference or shape function f and powerful fitting functions

3.2. Existing Models for OFETs 45

that map f to alternate geometries and VGS values. The drain current is described as

VDS

ID = KG · f · h(VGS ). (3.41)

τ (VGS )

Here, KG is a geometry factor which scales arbitrary transistors to the geometry of a reference

transistor for which the function f is derived. KG is calculated according to

W/L

KG = , (3.42)

WR /LR

where W/L and WR /LR are the width-to-length ratios of the actual and the reference de-

vice, respectively. f approximates the current-voltage shape of the reference transistor at a

predefined gate voltage VGS,0 . It is defined as

X

f (VDS ) = −10Xf with Xf = ai exp(−bi VDS ). (3.43)

i

Here, ai and bi are fitting parameters used for approximating the reference curve. The scale

function h scales the drain current with respect to different VGS values where h(VGS,0 ) = 1.

The approximation function is

X

h(VGS ) = 10Xh with Xh = ci · exp(−di · VGS ). (3.44)

i

Here, ci and di are fitting parameters. The delay function τ is used for stretching the reference

function f with respect to different VGS values where τ (VGS,0 ) = 1. τ is defined as

X

τ (VGS ) = 10Xτ with Xτ = pi · exp(−qi · VGS ). (3.45)

i

The parameters ai and bi in the reference function f are fitted to measured drain current

points. ci , di and pi , qi are then concurrently extracted with an optimization scheme.

Device variability is introduced by additional parameters in the drain current equations:

VDS

ID = Ks · KG · f · h(VGS − VON ). (3.46)

τ + τs

Here, KS is a current scale factor, VON is used for shifting the switch-on voltage, and τs is

used for shifting the delay of the transition between the linear and the saturation region. Gay

and colleagues modeled these three parameters with normal distributions, which they obtained

from measurements.

46 Chapter 3. OFET Modeling for Circuit Simulation

Fig. 3.9 shows the output characteristics and the fitting functions for a pentacene device

generated with parameters from Table 3.10.

3.2.6.2 Discussion

In the Dresden model, the function f from (3.43) is used for compressing the measured values

into a more tractable form. Gay et al. use power series in order to approximate the shape of

measured drain current values. They thereby ignore any physical background responsible for

the shape of the curves.

The numerous parameters in the model can be derived easily but are not based on any

physical assumption or meaning. Therefore, there is no direct relationship to material or

process properties.

The Dresden model accounts for dynamic hysteresis effects by adding an RC network

which simulates the delayed transport of mobile charges within the insulator [69]. Moreover,

statistical variation of individual devices is addressed.

Table 3.11 contains ratings for the Dresden models according to the model quality chart

presented in Section 3.1. Accuracy has been rated as good according to the comparisons be-

tween the model and measurement data presented in [69]. The compactness has been rated

as bad because many fitting coefficients (14 in the example from Table 3.10) without physical

meaning are needed. In the parameter extraction, curve fitting is necessary. The fitted param-

eters are not independent of each other because there is no “true” set of parameters describing

the transistor. When different VGS0 values are used (i.e. different shape functions f ), differ-

ent coefficients result. Therefore, the parameter extraction has been rated as medium. Stress

effects are included in the model by simple RC networks. Hence a rating of medium has been

given. Explicit modeling of capacitances is not mentioned in [69]. Judging from results pre-

sented in [69], constant capacitors for CGS and CGD are probably used. The Dresden model

easily copes with contact effects. Nevertheless, there is no link between the fitting coefficients

and physical or structural parameters. As an example, the influence of contact resistances is

hidden in the fitting coefficients from which it cannot readily be extracted. Moreover, phys-

ically meaningful parameters like the threshold voltage are missing. Therefore, the Dresden

model is of limited use for device technologists who want to explore the influence of future

process changes on electrical device parameters.

The modeling of transistors used in complementary organic circuits is no special problem as

dedicated models for the n-type and p-type transistors can be used.

3.2. Existing Models for OFETs 47

Table 3.10: Fitting parameters for typical bottom-gate bottom-contact pentacene transistor

[69] with pronounced contact resistance.

Shape function f Scale function h Delay function τ

a1 -1.2737 b1 0.4115 c1 -3.8416 d1 0.2432 p1 -1.9399 q1 0.1215

a2 -6.7432 b2 1.2e-4 c2 0.8047 d2 -0.0175 p2 1.1035 q2 0.0277

a3 -1.0077 b3 1.9633 – – – – – – – –

x 10−8

0u 0.0

−10u −2.0

−4.0

−20u

−6.0

−30u −8.0

f (VGS )

ID [A]

−40u −10.0

−12.0

−50u

−14.0

−60u −16.0

−70u −18.0

−14 −12 −10 −8 −6 −4 −2 0 −14 −12 −10 −8 −6 −4 −2 0

VDS [V] x

4.0 1.8

3.5 1.6

3.0 1.4

2.5 1.2

τ (VGS )

h(VGS )

2.0 1.0

1.5 0.8

1.0 0.6

0.4

0.5

0.2

0.0

−10 −8 −6 −4 −2 0 −10 −8 −6 −4 −2 0

VGS [V] VGS [V]

Fig. 3.9: Transfer characteristic and Dresden-type fitting functions for a sample pentacene

transistor ([69]).

48 Chapter 3. OFET Modeling for Circuit Simulation

Requirement Rating

Accuracy good

Capacitance Modeling not included

Compactness bad

Parameter Extraction medium

Stress Effects medium

OFETs normally operate as unipolar devices where only one type of carriers (holes in p-type

and electrons in n-type semiconductors) contributes to the current flow. Ambipolar devices

are a special class of OFETs where both holes and electrons can contribute to the current

flow, depending on the bias voltages at drain, gate, and source. The operation of ambipolar

devices will be explained in the following with the aid of [13, 58]. Here, a zero threshold

voltage and positive drain and gate voltages will be assumed. When the gate voltage lies in

the range between the drain and source voltage, the drain side of a standard unipolar transistor

normally gets pinched off. In ambipolar devices instead, charge carriers of opposite polarity

are accumulated in this region. The device is then effectively composed of two regions in

series as shown in Fig. 3.10: a hole-accumulating region of length Lp is series-connected to

an electron-accumulating region of length Ln .

With the assumption of equal currents in both regions, i.e.

1W 1W

Cis µp (VDS − VGS )2 = 2

Cis µn VGS , (3.47)

2 Lp 2 Ln

Ln + Lp = L, (3.48)

1W 2

ID = Cis [µn VGS + µp (VDS − VGS )2 ]. (3.49)

2 L

(3.49) is equivalent to a p-type and an n-type transistor of equal dimensions W and L in

parallel. For the p-type device, however, the position of the drain and source electrodes is

flipped owing to the requirement that VS,p > VD,p , where VS,p and VD,p are the effective

source and drain voltages of the p-type device. During a VDS sweep with a fixed VGS , the

n-type device is operated in normal FET mode while the p-type device has a constant gate-

drain voltage VGD,p . Hence, the latter displays a diode-like drain current, which increases

3.2. Existing Models for OFETs 49

Lp Ln

charge density

holes

electrons

VDS

potential

VGS

0

position along the channel source

drain

Fig. 3.10: Schematic charge and potential distribution in the channel of an ambipolar OFET

with VS < VG < VD (adaption from [58]).

with decreasing gate voltages. Therefore, a diode-like characteristic adds to the normal drain

current, which also increases with reduced gate-source voltage.

For VDS < 0, the situation is reversed and the p-type device acts as the normal transistor

and the n-type device contributes current in diode-like form.

Fig. 3.11 shows the schematic output characteristics of an ambipolar OFET. For the I/V

curves, a p-type transistor and an n-type transistor in parallel with µn = µp = 10−4 cm2 /Vs

have been assumed. In order to show the individual contributions of the two transistors,

VT,n = 10 V and VT,p = -8 V have been chosen.

Models developed in literature on ambipolar OFETs can be reduced to a parallel combina-

tion of a p-type and an n-type transistor. Schmechel et al. [70] used simple Level-1 equations

(see Section 3.2.1) to map drain-current behavior. Meijer and co-workers [13] employed an

analytic VRH model (see Section 3.2.4) in order to explain the increasing influence of the

gate-source voltage. Both models can be implemented using a parallel combination of the re-

spective unipolar devices, i.e. p-type and n-type Level-1-modeled devices for the Schmechel

approach as well as p-type and n-type VRH-modeled devices for the Meijer approach.

50 Chapter 3. OFET Modeling for Circuit Simulation

4.0u

3.0u 0V

2.0u VGS = 20 V 5 V

ID [A] →

1.0u

0.0u

15 V 10 V

−1.0u

-20 V

−2.0u

−3.0u 0V

−4.0u

VDS [V] →

Fig. 3.11: Schematic output characteristic for an ambipolar OFET with gate-source voltage

swept from -20 to 20 V.

Users of transistor models are interested in simple extraction procedures for relevant model

parameters like threshold voltage or mobility. Numerous approaches can be used for extract-

ing important parameters. In the following, frequently used procedures will be presented. A

more thorough analysis of suitable extraction procedures for the threshold voltage and other

important device parameters can be found e.g. in [27, 71, 72, 73, 74, 75].

In this section, popular extraction methods for parameters of the Level-1 model are listed.

These methods are also frequently used in the extraction of OFET parameters.

Threshold Voltage

The threshold voltage VT is one of the three parameters of the Level-1 model. VT can be ex-

tracted in numerous ways. In the following, some frequently cited methods will be presented.

3.3. Popular Procedures for Parameter Extraction 51

∂ID

gd = ≈ β(VGS − VT ) (3.50)

∂VDS

for “small values” of VDS [76]. In literature on parameter extraction, voltages in the order of

10 mV are proposed for VDS [71]. Fig. 3.12 illustrates a simulated sample curve3 for (3.50).

90.0u 6.0u

80.0u

5.0u

70.0u

60.0u 4.0u

gd [A/V]

50.0u

ID [A]

3.0u

40.0u

VT VT

30.0u slope β 2.0u slope β · VDS

20.0u

1.0u

10.0u

0.0 0.0 0

0 10 20 30 40 50 10 20 30 40 50

VGS [V] VGS [V]

Fig. 3.12: Plot of channel conductance gd vs. VGS and drain current ID vs. VGS . Both plots

are for VDS = 10 mV. Data has been taken from a simulated device which operates according

to the Level-1 equations.

Extrapolating the channel conductance curve to zero leads to the threshold voltage as gd =

0 A/V at VGS equal to VT in (3.50).

The drain current ID can also be used for extracting the threshold voltage VT without

the need to derive gd (also shown in Fig. 3.12). Again, VT is obtained by inspecting the

extrapolated intersection of ID with the VGS axis at zero current. The extrapolation is done

at the point of maximum slope, i.e. where the transconductance gm = ∂ID /∂VGS reaches its

maximum [71].

By extrapolating gd or ID in the linear region, series resistance at source and drain of the

device can be neglected as a drain-source voltage VDS ≪ 1V is used. On the other hand, the

transfer characteristic of real OFET devices can considerably deviate from the idealistic Level-

1 model. This generally complicates finding the most useful extrapolation point required in

the intercept calculations.

3

Model data: n-type device, KP = 1 nA/V2 , VT = 8 V, λ = 1 · 10−3 1/V, W/L = 200.

52 Chapter 3. OFET Modeling for Circuit Simulation

transconductance of a transistor denotes the variation of the output current resulting from a

variation of the input voltage and is calculated in the saturation region by

∂ID

gm = = β(VGS − VT ). (3.51)

∂VGS VDS =const

transconductance curve to zero leads to the threshold voltage VT [76].

Alternatively, the square root of the drain current can be used. From (3.3)

r

p β

ID = (VGS − VT ), (3.52)

2

results when again neglecting the channel-length modulation. The threshold voltage VT is

√

extracted by extrapolating ID to zero [77]. Fig. 3.13 depicts the extraction procedure for the

√

gm and ID method.

80.0u 40.0m

70.0u 35.0m

60.0u 30.0m

ID [ A]

gm [A/V]

50.0u 25.0m

√

40.0u 20.0m q

VT

√

2

20.0u 10.0m

10.0u 5.0m

0.0 0.0

0 10 20 30 40 50 0 10 20 30 40 50

VGS [V] VGS [V]

Fig. 3.13: Plot of the transconductance gm vs. VGS and the square root of the transfer charac-

teristic. Data have been taken from a simulated device with Level-1 equations.

Mobility

With the threshold voltage established, other parameters like the charge-carrier mobility µ can

be analyzed. µ is an important parameter in the assessment of device performance and is often

used as a benchmark number (see e.g. [78]) in the comparison of different semiconductors.

In this section, extraction methods for the mobility are presented.

3.3. Popular Procedures for Parameter Extraction 53

From the slope of gd or ID in Fig. 3.12, the device conductance parameter β can be established

[77]. According to (3.5),

β L

µ= . (3.53)

Cis W

It can also be calculated at individual points using the transconductance parameter

gm ≈ βVDS (3.54)

in the linear region. Solving this equation with respect to β and inserting (3.53) [79] leads to

L gm

µ= . (3.55)

W Cis VDS

√

In the saturation region, the slopes of the gm and ID curves as shown in Fig. 3.13 can be

used for deriving the device conductance parameter β. (3.53) can then be employed in the

extraction of the mobility µ.

Alternatively, the mobility can be calculated at individual points. By inspecting the transcon-

ductance gm from (3.51), the mobility can be calculated using (3.53) [80] with

L 1

µ = gm · . (3.56)

W Cis (VGS − VT )

In [78], the mobility is calculated by deriving (3.52) with respect to the gate-source voltage

√ r

∂ ID W

= µCis (3.57)

∂VGS 2L

√ 2

L ∂ ID

µ = 2Cis . (3.58)

W ∂VGS

In order to solve (3.56) VT has to be available while (3.58) and (3.55) are independent of

VT . Nevertheless, calculation of the derivatives is needed.

The channel length modulation parameter λ can be extracted from the saturation region of the

output characteristics when the threshold voltage and the device conductance β are known.

54 Chapter 3. OFET Modeling for Circuit Simulation

This relationship gives rise to two approaches. First, the channel conductance including

the channel length modulation

∂ID

gd = = λβ(VGS − VT )2 (3.60)

∂VDS

can be used for calculating the channel-length modulation. This results in a value of

∂ID

∂VDS

λ= . (3.61)

β(VGS − VT )2

It can also be derived graphically by inspecting the slope of the channel conductance in the

saturation region with respect to the drain-source voltage VDS as shown in Fig. 3.14.

45.0u

40.0u

35.0u

30.0u

gd [A/V]

25.0u

20.0u

15.0u

10.0u ≈ 490 nA/V

5.0u

0.0

0 10 20 30 40 50

VDS [V]

Fig. 3.14: Extrapolation of λ from the channel conductance (gd ) vs. drain-source voltage VDS

plot.

Contact Resistance

The Level-1 model does not include the influence of contact resistances between the transistor

channel and the source and drain electrodes. Nevertheless, the role of contact resistances in

transistor modeling is very important as will be shown in the following. Contact resistances

3.3. Popular Procedures for Parameter Extraction 55

can be modeled by adding series resistors to the transistor as shown in Fig. 3.15.

RD

DP

G

M VDS

SP

VGS

RS

Fig. 3.15: Elementary Level-1 transistor with contact resistors at drain and source.

The schematic in Fig. 3.15 contains a transistor M. The device has two series resistors

RS and RD which account for the contact resistance at the source and drain electrodes to the

channel. Both resistors affect the transistor voltages in a way such that the actual gate-source

voltage VGS

′

between nodes G and SP is

′

VGS = VGS − ID · RS (3.62)

′

between nodes DP and SP is

′

VDS = VDS − ID · (RS + RD ). (3.63)

In the following, the influence of the series resistors will be analyzed. First, RD shall be

neglected (RD = 0 Ω) and for simplified calculations, λ shall be dropped (λ = 0), too. The

drain current in the saturation region can then be expressed by inserting (3.62) and (3.5) into

(3.3):

β ′ β

ID = (VGS − VT )2 = (VGS − ID · RS − VT )2 . (3.64)

2 2

The solution for this equation is given by [81]

√

1 + 2βRS VGST − 1 + 4βRS VGST

ID = , (3.65)

2βRS2

with VGST = VGS − VT . The source resistance RS reduces the effective device conductance

56 Chapter 3. OFET Modeling for Circuit Simulation

2.0m

VGS = 50 V

1.8m

1.6m

1.4m

1.2m

ID [A]

40 V

1.0m

0.8m

0.6m 30 V

0.4m

0.2m 20 V

0.0

0 10 20 30 40 50

VDS [V]

Fig. 3.16: Effect of the source resistance on the drain current: simulated curves for a transistor

with RS (dashed lines) and the same transistor without the contact resistance (solid lines).

If only RD is considered (RS = 0 Ω), the drain current in the saturation region does not

change but the boundary between the linear and saturation region shifts as demonstrated by

the following equation (VSat = effective saturation voltage, VSat

′

= saturation voltage between

DP and SP ):

′ 2

VSat = VSat + β · VGST · RD

′

VGST =VSat 2

= VGST + βVGST · RD . (3.66)

An effective threshold voltage VT∗ can be derived from (3.66) by noting that

2

VT∗ = VT − βRD VGST . (3.67)

(3.67) shows that the effective threshold voltage VT∗ depends on VGST by a square-law

relationship for RS = 0 Ω. Its influence on the drain current is shown in Fig. 3.17.

If both series resistors are active (RS > 0 Ω and RD > 0 Ω) and VGST

′

= VGS′

− VT then

′ ′ ′2

VSat = VSat + IDSat · (RS + RD ) = VGST + β(RS + RD )VGST . (3.68)

The above discussion shows that the contact resistance degrades device performance by

reducing the effective drain-source and gate-source voltages. There exist various methods of

determining the contact resistance. In the following, three frequently used methods will be

3.3. Popular Procedures for Parameter Extraction 57

2.0m

VGS = 50 V

1.8m

1.6m

1.4m

1.2m 40 V

ID [A]

1.0m

0.8m

0.6m 30 V

0.4m

0.2m 20 V

0.0

0 10 20 30 40 50

VDS [V]

Fig. 3.17: Effect of drain resistance on the drain current: simulated curves for a transistor with

RD (dashed lines) and the same transistor without the contact resistance (solid lines).

presented.

Using a systematic variation of the channel length, the resistance between source and drain

can be measured in the linear region as

VDS L 1

RM = = + Rc = G0 · L + Rc . (3.69)

ID W µCis (VGS − VT )

transistor independent of its channel length. The latter is defined as

1

G0 = . (3.70)

W · µCis (VGS − VT )

The contact resistance can then be established by measuring the drain-current characteris-

tics for transistor devices with identical transistor widths but varying lengths and extrapolating

Rc from the RM vs. L plot to L = 0 µm. Fig. 3.18 shows a sample curve for the approach.

where the semiconductor is deposited last and the potential profile along the channel can be

58 Chapter 3. OFET Modeling for Circuit Simulation

2.0M V = 1 V

DS

VGS = 20 V

1.5M

30 V

RM [Ω]

1.0M 40 V

50 V

0.5M

RC

0.0

0.0 50.0u 100.0u 150.0u 200.0u

L [m]

Fig. 3.18: Measured resistance (RM ) vs. channel length (L) of devices with fixed channel

width: squares are the values according to (3.69) and solid lines are obtained from SPICE

simulations at VDS = 1 V.

measured by use of potential probes ([44, 82]). Alternatively, sampling electrodes similar

to four-point probes [83] have to be present in the channel in order to measure the channel

potential at predefined locations. A sample profile for a device operating in the linear region

is depicted in Fig. 3.19. On the y axis, the potential profile is plotted with x being the position

along the channel. At the source contact, x = 0 µm and at the drain contact, x = L. L is the

length of the transistor channel. The value RS for the source contact resistance and the value

RD for the drain contact resistances can be readily extracted from the potential drop at source

and drain.

The idea of the SJ method (named after its inventors Suciu and Johnston [84]) is to assume

that ID can be modeled in the linear region by

′

ID = β(VGS − VT )VDS = β(VGS − VT )(VDS − ID · RC ), (3.71)

with VDS

′

being the actual drain-source voltage at the transistor and RC the sum of source and

drain resistance (RS + RD ). The explicit form of (3.71) is

β(VGS − VT )

ID = VDS . (3.72)

1 + RC β(VGS − VT )

3.3. Popular Procedures for Parameter Extraction 59

y

RS · ID

source drain

electric potential

RD · ID

x

0 L

position

Fig. 3.19: Schematic potential profile along the channel of a bottom-gate bottom-contact tran-

sistor (adaption from [82]).

x 1 + RC β · x

= ≡ E(x) = E0 + ∆Ex, (3.73)

ID /VDS β

where x = VGS −VT and ID /VDS is the reciprocal of the resistance RM which can be measured

by taking ID from a real device. (3.73) is equivalent to

x · RM = E0 + ∆Ex, (3.74)

with E0 = 1/β and ∆E = RC . Fig. 3.20 illustrates the resulting curve E(x).

Suciu and Johnston emphasize that their approach is an analytical extraction procedure

which does not need any optimization procedures. Although the influence of the source re-

sistance RS on the gate-source voltage VGS is neglected in the calculations, the error can be

minimized by taking the measurements at small ID values.

The most important parameter in the model for Psi-TFTs is the threshold voltage from which

the other parameters depend in an extraction procedure. Jacunski et al. [47] give two practical

definitions of the threshold voltage:

1. The voltage above which the drain current no longer exponentially depends on VGS .

2. The voltage above which a MOS-like drain current expression can be used.

60 Chapter 3. OFET Modeling for Circuit Simulation

14.0M VDS = 1 V

12.0M

10.0M

8.0M

E(x)

∆E = RC

6.0M

4.0M

2.0M E0 = 1

β

0.0

0.0 10.0 20.0 30.0 40.0 50.0

VGS [V]

Fig. 3.20: Plot of the extraction function E(x) for the contact resistance.

Threshold voltages obtained by the first definition can considerably differ from voltages de-

rived with the other solution as there is a broad transition range from subthreshold operation in

the first definition to accumulation operation from the second definition. The second method

was also adopted by the IEEE standard on the characterization of OFET devices [48]. This

standard defines the threshold voltage as the minimum gate voltage required to induce the

channel. The value is extracted from IDS vs. VGS measurements.

The definitions in [47] demonstrate the difficulties in exactly describing the threshold volt-

age. In the case of conventional silicon MOSFETs, the threshold voltage is defined as the

gate-source voltage where the strong inversion layer starts to form. For inorganic thin-film

transistors, an additional on-voltage VON was introduced [41]. VON is found by inspecting

the log ID vs. VGS curve at low drain-source voltages. The on voltage is the point where

log ID reaches its minimum and becomes linear. According to [41], the physical meaning of

VON in polycrystalline silicon TFTs is that at VGS = VON the transistor channel starts form-

ing. However, induced carriers are still trapped in band-gap states. At a gate bias equal to

the threshold voltage VT , induced charges begin to appear as mobile carriers in the channel.

Fig. 3.21 illustrates the differences between VON and VT .

[62, 85] simply define VON as the switch-on voltage. This voltage is the value of VGS

where the lowest drain current is measured. A similar definition is used in the RPI model.

In the grain-boundary model, the mobility µ depends on the gate-source voltage (see (3.8)

√

and (3.9)). Therefore, obtaining the threshold voltage VT by plotting ID vs. VGS as usually

applied in literature on parameter extraction leads to incorrect values. Extracted threshold

voltages tend to be more favorable than the true parameter. Fig. 3.22 illustrates this behavior.

3.3. Popular Procedures for Parameter Extraction 61

100.0u 35.0m

10.0u

30.0m

1.0u

25.0m

100.0n

ID [ 3 A]

√

10.0n 20.0m

ID [A]

1.0n 15.0m

√

3

100.0p

VON VT 10.0m

10.0p

5.0m

1.0p

100.0f 0.0

−4 −2 0 2 4 6 8 10

VGS [V]

√

The plot shows log ID and ID of a simulated transistor. In the simulation, ID ∼ (VGS −VT )3

in saturation and VT = 1 V was used. The parameter set of the device is identical to the one

used in Fig. 3.21. An extraction with square-root plotting leads to the incorrect threshold

voltage of VT ≈ 3 V.

100.0u 7.0m

10.0u

6.0m

1.0u

5.0m

100.0n

ID [ A]

√

10.0n 4.0m

ID [A]

1.0n 3.0m

√

100.0p

VT 2.0m

10.0p

1.0m

1.0p

100.0f 0.0

−4 −2 0 2 4 6 8 10

VGS [V]

√

Fig. 3.22: Extraction of the threshold voltage by use of the ID vs. VGS method on a transistor

with ID ∼ (VGS − VT )3 in the saturation region.

62 Chapter 3. OFET Modeling for Circuit Simulation

The preceding discussion shows that knowing the power factor α in the current expression

ID ∼ (VGS − VT )α for the saturation current is necessary in order to correctly extract the

threshold voltage VT .

The power factor α can e.g. be derived by plotting log ID vs. log (VGS − VT ). The slope

of the resulting line yields α. In Psi-TFT modeling, α = mµ + 2 and should not be intermixed

with αsat . Here mµ is the mobility parameter of the device in (3.9). Extraction of α with

log-log plotting requires knowledge about the exact value of VT . It can therefore not be used

for extracting α and then the threshold voltage VT . Variations about the exact VT value lead

to bent curves in the log ID vs. log (VGS − VT ).

Fig. 3.23 shows two log ID vs. log (VGS −VT∗ ) plots for one single device where threshold

voltages of VT∗ = 1 V and of -1 V have been assumed. The actual ID curve has a threshold

voltage of VT = 1 V and a power factor α = 3. The left plot shows a curve with a slope of

three above the x value of approximately 0.3 and a steeper slope below that value. The latter is

due to the interaction between the above-threshold and the subthreshold current. The second

plot has been calculated with an anticipated threshold voltage of -1 V and does not show a

linear shape. This result demonstrates that the anticipated threshold voltage affects extraction

of the power factor α.

−3.5

−4.0

−4.5

−5.0

VT∗ = 1 V

log ID

−5.5

−6.0

−6.5

VT∗ = −1 V

−7.0

−7.5

−8.0

0 0.2 0.4 0.6 0.8 1 1.2 1.4

log(VGS − VT∗ )

Fig. 3.23: Extraction of the power factor α for ID ∼ (VGS − VT )α . The VT∗ values are used in

the x axis calculations.

3.3. Popular Procedures for Parameter Extraction 63

An analytic approach for both polycrystalline and amorphous TFT transistors called Unified

Extraction Method (UEM) has been proposed by Estrada et al. in [56]. The method was

originally developed for a-Si TFTs [57] and defines an extraction function H such that

V

RG

IDSat (VGS )dVGS

0 VG − VT

H(VGS ) = ≈ , (3.75)

IDSat α+1

power factor. An n-type transistor and VG > VT is assumed in the following discussions.

The procedure consists of the following steps:

2. Fit a line to H(VGS ) and extract values for α and VT from the slope and the intercept

point of H with the VGS axis.

The method can also be extended to polycrystalline silicon TFTs (Psi-TFT) by translating

the parameters used in (3.75) to parameters of Psi-TFTs. Details of the process are given in

[56]. The method is also useful in the calculation of the channel-length modulation λ and

series resistance R = RS + RD (RS /RD is the source/drain-side series resistance). In [46],

UEM4 has also been used for extracting parameters for pentacene-based devices in bottom-

gate configuration. The method also accounts for constant and diode-like contact resistances.

Details about the extraction scheme can be found in [46].

An alternate way of correctly deriving the threshold voltage and power factor is demon-

strated in Section 4.3.2.

As an alternative to an analytic extraction, fitting procedures can be used for deriving model

parameters. Such schemes employ an optimization engine to find a feasible set of parameters

to describe given output characteristics. Usually, the least-squares sum of the difference be-

tween model prediction and original data is used for measuring the quality of a fit [25, 86]. In

contrast to the graphics-based and analytic procedures described earlier, parameter fitting can

be applied to any model with a valid analytical description. However, the fitting engine needs

initial values for the parameters to extract. Another drawback of parameter fitting is that the

4

Later in [46], UEM was renamed to Unified Model and parameter Extraction Method (UMEM).

64 Chapter 3. OFET Modeling for Circuit Simulation

solver could find a local minimum or a physically incorrect set of parameters. The interested

reader is referred e.g. to [87] for a discussion of optimization algorithms.

Analytical extraction generally requires special measurement setups and knowledge on feasi-

ble models to use in order to derive model parameters. Parameter fitting does not depend on

such setups and is more general. However, extraction problems often consist of many param-

eters to find. This situation complicates parameter fitting as extraction engines often get stuck

at local minima in multidimensional fitting problems. Moreover, the extraction process needs

a sensible starting point for the extraction. Nevertheless, a numerical solver is far easier to

implement in computer software than an analytical or graphical extraction scheme.

For the users of circuit simulation in the optimization of OFET devices, automatic parameter

extraction is important. Each time a new device generation is introduced, transistor models

have to be generated so that automation of the modeling process is desirable. Automation

takes place in the form of dedicated modeling tools and should include one or more of the

following features:

2 Data Management – Large-scale measurement series need to be managed.

tracted.

⊲ Additional data describing the actual measurements must accompany the measure-

ment data in order to facilitate backtracking of measurement data and extraction

results. This kind of data includes e.g. the name of the sample from which mea-

surements were taken, geometrical dimensions of the devices, date of measure-

ment, operator, etc.

2 Selection tools – The most appropriate modeling approaches for given output character-

istics need to be identified. This requires tools which aid in selecting the most suitable

model for given ID -VGS characteristics. For example, the VSat method (which will be

presented in Chapter 4) can assist in selecting appropriate model types by plotting the

VGS dependence of the principal parameters KP , VT , and λ.

approaches for modeling so to allow users to try out different model types and extrac-

tion schemes. This can be handled by providing generic modeling interfaces where

3.4. Automation of Modeling 65

dedicated model generators can be linked in. These generators can e.g. contain sophis-

ticated graphical user interfaces or capabilities for data analysis.

2 Collaboration with Circuit Characterization Tools – The models are primarily used in

circuit simulation of reasonable circuits like logic gates. Therefore, it is desirable to

embed modeling tools in the circuit characterization environment. In this way, time-

consuming integration of model data into circuit simulations can be avoided.

There are numerous tools for extracting parameters of transistor models. The degree of au-

tomation in these tools ranges from providing an input mask where graphical the extraction of

the parameters can be done by the users to fully automated extraction procedures.

General-purpose extractors like the commercial tool Synopsys Aurora [88] consist of a

configurable solver and provide a script-based computation engine as well as a graphical user

interface. In the case of Aurora, parameters are extracted by curve fitting with a Levenberg-

Marquardt solver using constraints. The tool allows the users to carry out the extraction in

a series of steps. In each step, a set of parameters to optimize and default values for other

parameters can be defined. Setups like the following are possible: A coarse version of the

threshold voltage VT is extracted in the first extraction step using ID − VGS measurements and

a sensible range for VT . In the next step, the device mobility is extracted. Finally, a general

fit uses previously extracted parameter values as starting points and centers the parameters at

the minimum error between model output and measured curves. Tools like Aurora do not pro-

vide data-management capabilities or direct links to circuit characterization tools. Moreover,

appropriate models have to be selected by inspecting the error between modeling results and

original data.

Some SPICE simulators (e.g. Synopsys Star-Hspice [26] or Tanner T-Spice [68]) include

configurable optimizers which can be used for fitting the curves. These optimizers are con-

trolled by use of special statements in the textual netlists. Tools like Cadence/OrCAD PSpice

[89] or Synopsys SaberDeveloper include graphical front-ends which can be used for a graph-

ical fit of the curves. The simulators are directly linked to circuit characterization tools and

carry out the actual simulations needed in the characterization process. However, they do not

provide data management or convenient selection of appropriate models.

More specialized extractor tools like AIM-EXTRACT [90] provide graphical user inter-

faces and external fit programs for dedicated models. These external fit programs are con-

figured with text files containing references to the required measurement data and parameter

setups. In AIM-EXTRACT, the parameters are extracted by an undisclosed multi-step plan.

The drawback of the extraction plan is that the fitting results depend on the input parameters.

66 Chapter 3. OFET Modeling for Circuit Simulation

Experiments done by the author of this work revealed that e.g. the initially given thresh-

old voltage is used in calculations within subsequent parameter extractions inside the model

extractor for Psi-TFT devices. The tool is highly specialized because it can only extract pa-

rameters of certain models. Moreover, it does not provide data management or assistance in

selecting appropriate models.

The commercial package Agilent IC-CAP [91] provides a framework for model extrac-

tion. The tool centers on the management of device and circuit characteristics and provides

modeling, management as well as control of measurement instruments, and simulation facili-

ties. All processes can be automated using a built-in control language. Modeling complexity

ranges from the extraction of parameters of primitive models to models described by SPICE

netlists. IC-CAP collaborates with external simulators in order to test the accuracy of ex-

tracted model parameters or to characterize a circuit using circuit simulations. The simulators

are integrated via an open simulator interface. IC-CAP already includes a large set of models

and specialized extraction procedures for the derivation of their parameters.

3.4.2 Discussion

In summary, tools for circuit-level transistor modeling are either very general or specialize on

certain models. The general tools can be configured very flexibly but specialized modeling

tools provide more convenient extraction schemes. With the exception of IC-CAP, none of the

above-mentioned tools provides the analysis capabilities needed for the extraction schemes

presented in Section 3.3. Conversely, the commercial tool IC-CAP provides both very gen-

eral and highly specialized extraction schemes in one software package. However, all tools

investigated in this section lack the treatment of dedicated OFET models or sophisticated data

management.

The following aspects of OFET modeling were discussed in this chapter:

2 Different charge-transport mechanisms in OFETs are currently under debate. Many

issues need to be resolved in order to fully understand the inner workings of organic

transistors. Modeling is complicated by the fact that different OFET technologies exist,

where the availability of many materials and manufacturing methods leads to various

effects which have to be accounted for.

2 Owing to the early stage in the process of understanding charge transport in organic

semiconductors, many modeling approaches for OFETs are based on well-known mod-

els derived for more traditional semiconductor technologies like crystalline silicon or

3.5. Chapter Summary 67

thin-film transistors. Other models sacrifice a physical basis in favor of accurate mod-

eling, e.g. for simulation of analog circuits. One model with a true OFET-related phys-

ical basis is the model of variable range hopping (VRH). Modeling of capacitances and

stress effects is also still in the beginning. Only one model presented in this chapter

honors stress effects by introducing an RC network in order to introduce hysteresis in

the switching behavior of transistors.

2 The model quality chart (MQC) was defined in this chapter in order to allow ratings and

comparisons of the various models with respect to accuracy, modeling of capacitances,

compactness, parameter extraction and stress effects. OFET models were then analyzed

by use of MQC tables. Table 3.12 lists the results obtained by the discussion of these

models.

Requirement Level-1 Psi-TFT a-Si TFT VRH Table Dresden

& contacts

Accuracy bad to good good good good good

medium

Capacitance – – – good good –

modeling

Compactness good good good good bad bad

extraction needed

Stress Effects – – – – – medium

2 Accuracy in Table 3.12 has been rated according to the data sets used for developing the

respective models. As will be shown in Section 4.3.5 and Section 4.3.6, models have

their peculiar shortcomings when dealing with different device technologies. Therefore,

it is not possible to select one modeling approach equally useful for all types of devices.

Extraction methods are normally centered on finding the best-fitting parameters for a

given set of parameters and a given model. Whether the model matches the data can

only be seen at the end of the extraction procedure. From the user’s point of view, it

would be desirable to have this information before any lengthy extractions are carried

out. In this respect, the traditional question which set of parameters best maps measured

curves for a given model translates into the question which model potentially maps the

given curves.

68 Chapter 3. OFET Modeling for Circuit Simulation

2 There exist many tools and measurement procedures for deriving parameters of popular

models. However, these tools require skilled users and appropriate data sets. In order to

provide maximum use, a generic framework for analyzing the performance of OFETs

in logic circuits should assist users in the derivation of appropriate model sets. Here,

features like data management, selection of best-fitting models, implementation of user-

friendly fitting approaches, and collaboration with the circuit characterization part of the

framework are important. Existing extraction tools do not provide these characteristics.

The issues of extracting reasonable threshold voltages and selecting proper models will

be addressed in the following chapter, where a novel modeling and analysis tool named VSat

method is discussed. Chapter 6 then contains a description of a computerized methodology

for flexible transistor modeling and characterization of OFET-based logic circuits.

69

Chapter 4

VSat Method

In this chapter, a novel approach to extracting model parameters of transistors is detailed. The

method is based on two observations made by the author of this work.

The first observation is that most models presented in Section 3.2 are variations of the

Level-1 model. In these models, constant parameters are replaced by variable parameters,

which e.g. depend on the gate-source voltage. The idea of the novel extraction method is to

decompose a measured set of output characteristics ID vs. VDS into individual output curves,

one for each given VGS value. The basic parameters VT , KP , and λ of the Level-1 model are

then calculated for each of these curves. By plotting the extracted parameters vs. VGS , the

best-fitting model type can be identified because the different models have characteristic VGS

dependences of their parameters.

The second observation is that the three-dimensional problem of extracting the basic pa-

rameters VT , KP , and λ for a single output characteristic can be reduced to a one-dimensional

problem of finding VT and calculating KP and λ from it. VT can be determined by searching

the transition point between the linear and the saturation region, i.e. the saturation voltage

VSat , and calculating VT from the relationship VSat = VGS − VT . Owing to the role of VSat in

the extraction process, the extraction method has been named VSat method.

The extraction procedure and its application in transistor modeling are detailed in the

following sections. First, the extraction scheme is described. Then, two transistor models are

presented which directly integrate the VSat method. Finally, experimental results showing the

application of the extraction procedure and novel modeling techniques are discussed.

70 Chapter 4. VSat Method

Automatic extraction of model parameters with the VSat method is based on the following

assumptions:

2 Individual ID vs. VDS curves with constant VGS can be covered by Level-1 modeling

from (3.1) to (3.3).

2 Appropriate models for given characteristics can be found by plotting the basic Level-1

parameters KP , VT , and λ vs. VGS

The VSat method relies on the determination of the saturation voltage VSat , i.e. the drain-

source voltage of an ID vs. VDS curve where the transition from the linear to the saturation

region takes place. VSat can be determined by varying a guess of it in the available VDS range,

calculating VT , KP , an λ from the guessed VSat , and observing the mean-square error between

the resulting Level-1 model and the measurement data or by employing a one-dimensional

optimization routine.

The values necessary for calculating the model parameters are shown in Fig. 4.1. They

are obtained as follows: From VSat and the respective drain current IDsat , the maximum drain

voltage VDM ax and the respective drain current IDM ax , the parameters KP and λ can be de-

rived using the following equations.

IDM ax − IDSat

f = , (4.2)

VDM ax − VSat

|IDS0| = |IDSat | − f · |VSat |, (4.3)

2

KP = 2|IDS0|/VSat , (4.4)

f

λ= . (4.5)

|IDS0|

Here, f is the slope of ID between VSat and VDM ax , all other parameters have their usual

meaning. Absolute values are used so that positive values are guaranteed for both n-type and

p-type transistors. f can be calculated from the ID values at VDM ax and VSat . Alternatively,

f can also be derived by calculating the linear regression of the ID points between VSat and

VDM ax . The latter procedure is more robust against measurement noise as more points are used

in the calculation of the slope. IDS0 is the drain current in the saturation region with λ = 0.

It can be used to calculate KP by exploiting the relationship IDS0 = 12 W L

2

KP VSat . λ can be

4.1. Extraction based on VSat Method 71

1W 2

derived from IDM ax − IDSat = 2 L

KP VSat · λ · (VDM ax − VSat ) which leads to f = λ · IDS0 .

IDM ax

IDSat slope f

ID

′

IDS0

ID

Fig. 4.1: Important points on the ID vs. VDS curve for calculating model parameters according

to the VSat method. The dashed curve ID ′

denotes the drain current for λ = 0. VGS is constant

for the curve.

Fig. 4.2 shows a plot of the mean-square error vs. the guessed saturation voltage VSat

of two different simulations1. In the underlying experiment, drain currents were simulated

with a VDS increment of 0.1 V and 1.0 V. Then, VSat was guessed by varying the unknown

value between 3 V and 10 V with a step size of 0.1 V. The mean-square error was calculated

according to

n

1X

ε̄ = [ID,m (VDS,i) − ID,s (VDS,i, VSat )]2 . (4.6)

n i

Here, n is the total amount of measured points, ID,m is the measured or interpolated drain

current (index m for “measured”). ID,s is the drain current according to the Level-1 model

and the parameters extracted with the VSat method (index s for “simulated”).

Both curves show minima at VSat ≈ 8.4 V. The curve labeled “original data with VDS

increment of 0.1 V” is smoother. The other curve has local minima which can cause an

optimizer to get stuck at these points (e.g. VSat = 6 V). The plot also shows that the resulting

parameter accuracy depends on the sampling density of the measured ID points. Moreover,

the presence of local minima complicates the application of many numerical optimization

methods. However, the optimal solution can be found by the above-mentioned procedure of

varying VSat in a fixed interval in steps of e.g. 0.1 V and selecting the VSat value for the

minimum mean-square error ε̄.

1

Level-1 model, simulation data: β=10 nA/V2 , VT = −6.4 V, λ = 0.01 1/V, VGS = 2 V.

72 Chapter 4. VSat Method

× 10−15

4.0

3.5

2.5

ε̄ [A2 ]

2.0

original data with VDS increment of 1.0 V

1.5

1.0

0.5

0.0

3 4 5 6 7 8 9 10

guessed Vsat [V]

The reader is referred to Section 4.3 for a demonstration of the VSat method with measured

output characteristics.

Discussion

The VSat method approaches modeling in a mixture of fitting and analytical methods. First,

the threshold voltage VT is derived by a numerical extraction of the saturation point of an ID

vs. VDS plot. Then, the other parameters KP and λ are analytically calculated from VT . This

approach reduces the three-dimensional fitting problem to a one-dimensional search which

can be carried out fully automatically.

Application of the VSat method entails using the whole range of drain-source voltages

VDS . Therefore, effects introduced by series resistances affect the extracted parameters, e.g.

reduce effective voltages due to voltage drops across the series resistors. Existing methods

of extracting VT therefore often resort to ID vs. VGS curves with small drain-source voltages

VDS below 1 V.

The VSat method generates intermediate parameters used to identify appropriate modeling

approaches. For example, the Level-1 model yields parameters which are independent of

VGS while the threshold voltage VT in the Psi-TFT model linearly depends on VGS and on

a conductance factor KP with a power-law dependence (see Section 4.3.2 for more details).

By plotting them against VGS , the parameters aid in the selection of appropriate modeling

approaches because the parameter curves in the individual models have characteristic shapes

4.2. Modeling based on VSat Method 73

The VSat method can be used as the first step of a two-step extraction procedure similar to the

intermediate model approach developed by Kondo and co-workers to extract parameters of

MOSFET transistors [92].

In the intermediate model approach, model parameters are extracted by a two-step con-

cept. In the first step, intermediate parameters are extracted from measured I-V data. In

a second step, these intermediate parameters are transformed into parameters of the target

model. Splitting the extraction process into two steps allows device-independent extraction

routines for the intermediate parameters. Mapping the intermediate parameters to the parame-

ters of the target model is then device-dependent. Kondo and colleagues emphasize that once

an acceptably accurate intermediate model has been established, model designers only need

to derive a mapping procedure for the parameters of the target model.

The original approach by Kondo and colleagues is used to extract one set of parameters

for a complete set of output characteristics. It works with the subthreshold and linear region.

Conversely, the VSat method is used to derive distinct sets of Level-1 parameters for individual

above-threshold curves of ID vs. VDS measured at constant VGS values. The distinct parameter

sets are then related to extract a common parameter set for all measured VDS and VGS values.

In the following, two modeling approaches based on data derived by the VSat method will

be discussed: a table-based model and an analytical model called Linvar model. The latter

model utilizes the concept of intermediate parameters.

The VGS -dependent parameters VT , KP , and λ can be directly recorded in a table generated

by the VSat method. During circuit simulation, the model parameters are then taken from this

table or are interpolated / extrapolated from existing values. A table model has been written

in this work in XSPICE [93]. The reader is referred to Section 6.3 for a demonstration of

its application. This type of model is easy to implement and does not require sophisticated

compression equations like the model in [31]. Moreover, the parameter table does not store

measurement values like other modeling approaches do. Instead, the VGS -dependent param-

eters of the Level-1 model are tabulated vs. the gate-source voltage. With this approach,

parameters of the model can be changed without the need to store a new set of output char-

acteristics for the table model. On the other hand, the table model only works correctly if the

individual I/V curves can be approximated by Level-1 modeling. This is not possible when

74 Chapter 4. VSat Method

Discussion

Table 4.1 provides ratings for the table-based model with respect to the model quality chart

presented in Section 3.1. Accuracy was rated as good because the model can map output

characteristics when the individual curves are Level-1-shaped. Modeling of transistor capac-

itances or stress effects is not included. Compactness has been rated as bad because many

values are needed. In the parameter extraction, only the VSat method is necessary. Therefore,

the parameter extraction has been rated as good.

Requirement Rating

Accuracy good

Capacitance Modeling not included

Compactness bad

Parameter Extraction good

Stress Effects not included

The VGS -dependence of the extracted parameters can be approximated by analytical equa-

tions. The Linvar model has been developed in this work to provide such a relationship. The

model parameters are assumed to be variables linearly depending on VGS . Hence the name

Linvar model is used. Other dependences (polynomial, exponential) were analyzed in [94],

but these functions add more parameters and therefore reduce the compactness of the model.

Experimental studies on OFETs based on poly-(3-hexyl)thiophene (P3HT) (see Section 4.3.2)

showed that a linear dependence represents a good compromise between compactness (num-

ber of parameters) and accuracy (mean-square error with respect to measurements) of the

model.

Model Equations

In the Linvar model, the VGS -dependent parameter sets are mapped to the following functions:

4.2. Modeling based on VSat Method 75

VT (VGS ) = VT 0 + fT · VGS , (4.8)

λ(VGS ) = λ0 + fλ · VGS . (4.9)

Assuming n-type devices for the discussion, the equations of the Linvar model are:

ID = 0. (4.10)

W VDS

ID = KP (VGS ) · VGS − VT (VGS ) − VDS · [1 + λ(VGS )VDS ]. (4.11)

L 2

1 W

ID = KP (VGS ) · [VGS − VT (VGS )]2 · [1 + λ(VGS )VDS ]. (4.12)

2 L

In order to map the existence of a subthreshold or bulk current, a resistor Rpar parallel

to the transistor channel is added between source and drain. The resistance value can be

determined using the difference between a measured ID point for zero VGS and the model

prediction without Rpar . The resistor can be normalized to a width-independent contribution

using

′

Rpar = Rpar · Wref , (4.13)

where Wref is the width of the modeled device. The drain-source current then becomes

′

IDS = ID + VDS · Rpar /W. (4.14)

Discussion

The main advantage of the Linvar model is its simplified parameter extraction scheme. The

procedure is especially suitable for automatic extraction. On the other hand, the Linvar model

simply represents a fitting model. Therefore, the parameters do not directly reflect process or

material properties. The model is restricted to devices where the parameters show linear de-

pendence on VGS . The extraction scheme does not take contact resistances at drain and source

into account. These elements have to be derived beforehand in order to extract meaningful

values for KP , λ and VT .

76 Chapter 4. VSat Method

In Table 4.2, a rating of the Linvar model with respect to the model quality chart pre-

sented in Section 3.1 is shown. Accuracy was rated as medium as the model only matches

a restricted set of device structures. In particular, only devices with linear VGS -dependence

of the parameters are mapped. Capacitance modeling or stress effects are not included in the

modeling. Although the model relies only on a small set of parameters, compactness was

rated as medium because these parameters are only fitting parameters. On the other hand, pa-

rameter extraction is rated as good because easy-to-use fitting parameters are used. Owing to

the application of the VSat method, no starting values are needed for the parameters to extract

and the extraction process is reduced to a one-dimensional search.

Requirement Rating

Accuracy medium

Capacitance Modeling not included

Compactness medium

Parameter Extraction good

Stress Effects not included

In the following, experimental results on the analysis of transistor parameters with the VSat

method are presented. First, the characteristic behavior of commonly used transistor models

will be explored. Then, the effect of constant contact resistance is treated. A method is

demonstrated how these parasitic elements can be compensated for in the analysis. Finally,

the application of the Linvar model on measurement curves is presented.

The VSat method is based on the Level-1 model (see Section 3.2.1) which provides simple

equations to predict the behavior of transistors. In the VSat method, the saturation voltages

of individual ID -VDS curves are extracted. Subsequently, all extracted saturation voltages are

plotted versus their respective VGS values. In the case of a Level-1 transistor, a line with unity

slope can be expected because VSat = VGS − VT . From VSat , the threshold voltage VT can

readily be extracted and the other Level-1 parameters are calculated using (4.2) through (4.5).

Fig. 4.3 shows the output characteristics of a Level-1 transistor2, the extracted saturation

voltage VSat as well as the derived parameters process conductance KP and channel-length

2

Original model data: p-type transistor, VT =3 V, KP =10 pA/V2 , λ= 10 mV−1 .

4.3. Experimental Results on Transistor Fitting 77

modulation λ. The threshold voltage has not explicitly been plotted because it can be derived

from the saturation voltage VSat . As expected, the saturation voltage VSat has a slope of one

and intersects the zero VGS point at −VT . KP and λ are independent of the gate-source bias

and coincide with the given model parameters.

The example shows that the VSat method can well extract a true Level-1 transistor. How-

ever, the extractor needs enough points between the supposed saturation voltage and the maxi-

mum |VDS | in order to safely detect the linear IDS line of the saturation curve. To demonstrate

this requirement, the above transistor is analyzed with the VGS values ranging from 0 to -20 V

in steps of 2 V and VDS also ranging from 0 to -20 V only, but in steps of 1 V. Fig. 4.4 shows

the resulting plot for the VSat curve, the Linvar-model approximation for the parameters KP ,

VT and λ. At |VDS | > 15 V, the curves start to considerably deviate from the expected be-

havior. The data shows that the VSat prediction gets inaccurate for VGS values approaching

-20 V.

The TFT model for polycrystalline silicon (Psi-TFT, see Section 3.2.2) is a semi-empirical

model with a physical background [41]. It effectively extends the Level-1 model by adding

a VGS -dependent mobility and a factor for the variation of the saturation voltage (αsat ). The

output characteristics as well as extracted curves for a simulated polycrystalline thin-film

transistor3 are depicted in Fig. 4.5.

Level-1 parameters derived from the extracted curves do not directly correspond to the

model parameters of the Psi-TFT model. This is due to the modifications of the model with

respect to the original Level-1 model (see Section 3.2.2). In the Psi-TFT model, the satu-

ration voltage is calculated by VSat = αsat (VGS − VT ). Therefore, the slope of the curve in

Fig. 4.5b can be used to derive αsat ≈ 1.7. From this slope, the threshold voltage is derived

by VT = −VSat (VGS = 0 V)/αsat = 1 V.

With VT and αsat established, the power factor mµ for the mobility can be estimated by

plotting log ID vs. log (VGS − VT ) for a fixed VDS in the saturation region. The slope of the

log-log curve corresponds to 2 + mµ owing to ID ∼ (VGS − VT )2+mµ . Fig. 4.5f depicts the

log-log curve. This approach leads to a slope of 3.2, which coincides with 2 + mµ . Finally,

µ0 can be obtained by inserting a measured current value into the model equation and solving

for µ0 . The VGS -dependence of KP in Fig. 4.5c can be used for qualitative examinations. In

the figure, KP displays weakly super-linear behavior which suggests a power factor mµ > 1.

Fig. 4.5d shows λ, the parameter for the channel-length modulation. The deviation from

3

Model data: µ0 = 1·10−3 cm2 /Vs, Cis = 1 · 10−7 F/cm2 , VT = 1 V, αsat = 1.7, mµ = 1.2,

µs = 1 · 10−11 cm2 /Vs, ηi = 3.34, I0 = 1 · 10−13 A, W/L = 1000

78 Chapter 4. VSat Method

a) b)

0.0 VGS = 0 V 0

−0.5u

−5

−1.0u

VSat [V]

−1.5u −10

ID [A]

−2.0u

VGS =-16 V −15

−2.5u

VGS =-18 V

−3.0u −20

VGS =-20 V saturation curve

−3.5u

−25

−30 −25 −20 −15 −10 −5 0 −20 −15 −10 −5 0

VDS [V] VGS [V]

c) d)

15.0m

14.0p 14.0m

13.0m

12.0p 12.0m

KP [A/V2 ]

11.0m

λ [V−1 ]

10.0p 10.0m

9.0m

8.0p 8.0m

7.0m

6.0p 6.0m

5.0m

−20 −15 −10 −5 0 −20 −15 −10 −5 0

VGS [V] VGS [V]

Fig. 4.3: Plot of important parameters of a Level-1 transistor with p-type behavior:

a) output characteristics, b) saturation voltage, c) process conductance, and d) channel-length

modulation.

4.3. Experimental Results on Transistor Fitting 79

a) b)

−2 10.5p

−4 10.4p

−6 10.3p

10.2p

−8

KP [A/V2 ]

VSat [V]

10.1p

−10

10.0p

−12

9.9p

−14

9.8p

−16

9.7p

−18 9.6p

−20 9.5p

−20 −15 −10 −5 0 −20 −15 −10 −5 0

c) VGS [V] d) VGS [V]

4.0 15.0m

14.0m

13.0m

3.5

12.0m

11.0m

VT [V]

λ [V−1 ]

3.0 10.0m

9.0m

8.0m

2.5

7.0m

6.0m

2.0 5.0m

−20 −15 −10 −5 0 −20 −15 −10 −5 0

VGS [V] VGS [V]

Fig. 4.4: VSat -type extraction with an insufficient VDS range: a) extracted saturation volt-

age, b) derived process conductance, c) threshold voltage, and d) channel-length modulation.

Dashed lines show the expected curves.

80 Chapter 4. VSat Method

a) b)

0.0 0.0

−5.0

−0.5m

−10.0

−15.0

VSat [V]

−1.0m

ID [A]

−20.0

−1.5m −25.0

−30.0

−2.0m

−35.0

−2.5m −40.0

−50 −40 −30 −20 −10 0 −20 −15 −10 −5 0

VDS [V] d) VGS [V]

c)

2.5n 20.0

2.0n

15.0

KP [A/V2 ]

1.5n

VT [V]

10.0

1.0n

5.0

0.5n

0.0 0.0

−20 −15 −10 −5 0 −20 −15 −10 −5 0

e) VGS [V] f) VGS [V]

20.0m −6.0

−8.0

15.0m

−10.0

log(ID ) []

λ [V−1 ]

10.0m −12.0

−14.0

5.0m

−16.0

0.0 −18.0

−20 −15 −10 −5 0 0 0.5 1 1.5 2 2.5 3 3.5

VGS [V] log(VGS − VT ) –>

b) saturation voltage, c) process conductance, d) threshold voltage, e) channel-length mod-

ulation, and f) logarithmic drain current.

4.3. Experimental Results on Transistor Fitting 81

constant behavior near zero VGS can be attributed to the influence of the subthreshold current

according to (3.12).

The plots from Fig. 4.5 can be used to check whether the Psi-TFT model matches a mea-

sured device. If the log-log plot of ID vs. VGS − VT does not yield a straight line, the Psi-TFT

model does not correctly map the output characteristics of the respective device.

The ideal behavior of the Level-1 model can be weakened by the presence of contact resis-

tance at the interface between the source/drain electrodes and the channel region. Contact

resistance is often encountered e.g. in bottom-gate bottom-contact transistors where the elec-

trodes disturb the formation of the semiconductor film and trap states occur. These trap states

lead to diode-like contact resistance which can be difficult to model. Diode-like resistances

also occur when the work functions of the electrode material and the semiconductor in the

transistor channel are not aligned.

Constant resistors at the source and drain electrodes are more tractable form of contact

resistance. Their presence in a Level-1-type transistor has already been discussed briefly in

Section 3.3.1. At this point, their influence on extracted parameters will be analyzed. A device

model according to Fig. 4.6 will be assumed. RDC and RSC represent the drain-side and

source-side contact resistances while M maps the ideal Level-1 transistor. The VSat extractor

treats M as a unit with RDC / RSC and derives VGS -dependent Level-1 parameters for the

combined device. The extraction results are effective parameters that can be used to see how

contact resistance affects the output characteristics.

DRAIN

RDC

GATE M

RSC

SOURCE

Fig. 4.6: Schematic of a transistor with contact resistances at drain and source.

In the analysis, RDC and RSC shall be varied independently and the ideal transistor M

shall have the same model parameters as in Section 4.3.1. Fig. 4.7 shows extraction results

82 Chapter 4. VSat Method

for different RDC values. RDC alone (RSC = 0 Ω) strongly influences the saturation voltage

as can be seen from Fig. 4.7a. In the plot, the VGS -dependent saturation voltage is shown. The

data demonstrates that small values of RDC in the range of 100 kΩ do not noticeably affect

transistor behavior for the given device. However, higher RDC values shift the saturation point

to more negative values.

A VSat -type parameter extraction shows that the drain-side resistor strongly influences

(viz. shifts) VT and KP . KP decreases with RDC . Consequently, increasing RDC also de-

creases the attainable current as demonstrated by Fig. 4.7d. The effect of RDC will also be

more pronounced for increasing |VGS | owing to the fact that the drain current also increases

as well as the voltage drop at RDC .

The source-side contact resistance (RSC ) can also be varied with RDC being removed

(RDC = 0 Ω). In this case, the maximum drain current is affected while the saturation points

effectively keep unchanged as long as RSC does not get too large. At some resistance value,

RSC will start to dominate the ID -VDS curve. This can be seen from the graphs in Fig. 4.8.

In conclusion, a noticeable resistance at the drain contact will influence the saturation

voltage VSat , the process conductance KP and on-currents. A noticeable resistance at the

source contact on the other hand will influence the process conductance KP , the channel-

length modulation λ and both the on/off current.

The VSat method only measures effective parameters. It does not separate the contributions of

contact resistors due to the nonlinear interaction between the transistor and RDC /RSC . These

resistances can be determined by a resistance measurement like the potential profiling (see

Section 3.3.1). If the approximate values are known they can be compensated for by placing

additional negative resistors (RCD and RCS ) in series to the transistor during simulation as

shown in Fig. 4.9. At these points in the device setup, they neutralize the effect of the contact

resistances.

The presence of RCD and RCS leads to equal potentials at DRAIN and DP as well as

SOURCE and SP. In a computer simulation, the parameters of transistor M can now be ex-

tracted using the usual methods:

1. Obtain effective parameters or a table-based model of the transistor operating under the

influence of the contact resistances.

3. Neutralize the contact resistance by a setup equivalent to Fig. 4.9. With this setup, the

drain-source voltage and gate-source voltage across transistor M are equivalent to the

4.3. Experimental Results on Transistor Fitting 83

a) b)

0.0 10.0p

−10.0 9.0p

8.0p

−20.0

KP [A/V2 ]

7.0p

VSat [V]

−30.0 6.0p

−40.0 5.0p

RDC = 0.0 MΩ 4.0p

−50.0 0.1 MΩ

1.0 MΩ 3.0p

−60.0 2.0 MΩ

5.0 MΩ 2.0p

10.0 MΩ

−70.0 1.0p

−20.0 −15.0 −10.0 −5.0 0.0 −20.0 −15.0 −10.0 −5.0 0.0

VGS [V] VGS [V]

c) d)

11.0m 10.0u

10.5m

1.0u

ID [A]

λ [V−1 ]

10.0m

0.1u

9.5m

9.0m 10.0n

−20.0 −15.0 −10.0 −5.0 0.0 0.0 2.0M 4.0M 6.0M 8.0M 10.0M

VGS [V] RDC [Ω]

Fig. 4.7: Behavior of important transistor parameters with respect to different values for the

drain-side contact resistance: a) saturation voltage, b) process conductance, c) channel-length

modulation, d) on/off current.

84 Chapter 4. VSat Method

a) b)

0.0 10.0p

9.0p

−5.0

8.0p

−10.0

KP [A/V2 ]

7.0p

VSat [V]

−15.0 6.0p

5.0p

−20.0 RSC = 0.0 MΩ

0.1 MΩ 4.0p

1.0 MΩ

−25.0 2.0 MΩ

5.0 MΩ 3.0p

10.0 MΩ

−30.0 2.0p

−20.0 −15.0 −10.0 −5.0 0.0 −20.0 −15.0 −10.0 −5.0 0.0

c) VGS [V] d) VGS [V]

11.0m 10.0u

10.0m

9.0m

8.0m 1.0u

λ [V−1 ]

ID [A]

7.0m

6.0m

5.0m 0.1u

4.0m

3.0m

2.0m 10.0n

−20.0 −15.0 −10.0 −5.0 0.0 0.0 2.0M 4.0M 6.0M 8.0M 10.0M

VGS [V] RSC [Ω]

Fig. 4.8: Behavior of important transistor parameters with respect to different values of the

source-side contact resistance: a) saturation voltage, b) process conductance, c) channel-

length modulation, and d) on/off current.

4.3. Experimental Results on Transistor Fitting 85

DRAIN

RCD = −RDC

RDC

DP

VDS GATE M

SP

VGS RSC

RCS = −RSC

SOURCE

voltage drop between the terminals DRAIN and SOURCE and GATE and SOURCE,

respectively.

Results of the procedure are demonstrated in Fig. 4.10. The figure depicts extracted curves

vs. VGS for a device simulated with RSC = 2 MΩ, no RDC , and various compensation resistors.

The method of resistance compensation can also be used to determine the contact resis-

tances RSC and RDC . The approach exploits the fact that the channel-length modulation λ

is mainly affected by RSC and the saturation voltage VSat only by RDC . By exploiting these

relationships, RDC can be determined by bringing VSat to a straight line through varying RCD

and RSC by bringing λ to a straight line through varying RCS .

86 Chapter 4. VSat Method

a) b)

0.0 15.0p

RSC = 2 MΩ 14.0p

−5.0 13.0p

12.0p

KP [A/V2 ]

VSat [V]

−10.0

11.0p

10.0p

−15.0

9.0p

RCS = 0.0 MΩ

−20.0

0.1 MΩ 8.0p

1.0 MΩ

2.0 MΩ 7.0p

3.0 MΩ RSC = 2 MΩ

−25.0 6.0p

−20.0 −15.0 −10.0 −5.0 0.0 −20.0 −15.0 −10.0 −5.0 0.0

c) VGS [V] d) VGS [V]

30.0m 10.0u

RSC = 2 MΩ

25.0m

1.0u

λ [V−1 ]

20.0m

ID [A]

15.0m

0.1u

10.0m

RSC = 2 MΩ

5.0m 10.0n

−20.0 −15.0 −10.0 −5.0 0.0 0.0 0.5M 1.0M 1.5M 2.0M 2.5M 3.0M

VGS [V] RSC [Ω]

Fig. 4.10: Behavior of important transistor parameters with respect to different values of

the source-side compensation resistance: a) saturation voltage, b) process conductance,

c) channel-length modulation, and d) on/off current. The contact resistance at the source

electrode is RSC = 2 MΩ.

4.3. Experimental Results on Transistor Fitting 87

Fig. 4.11 shows the ID − VDS curve of a poly(3,3”-dihexyl-2,2’:5’,2”-terthiophene) (PDHTT)

transistor and the parameters extracted by the VSat method. I/V data was taken from [95]. The

device has a channel width of 10,000 µm and a channel length of 10 µm.

The resulting curves show that the saturation voltage decreases linearly between gate volt-

ages of -4 V and -24 V. At gate voltages below -24 V, VSat begins to saturate. This behavior

can be attributed to |VGS | approaching max. |VDS |, a voltage region where the VSat method is

no longer reliable (see Section 4.3.1). The process conductance KP sharply increases between

gate voltages of 0 and -5.0 V and then slowly degenerates. At gate-source voltages below -24

V, it starts to rise again. This latter rise might also be due to the difficulties in extracting

the correct saturation voltages at these VGS ranges. The decline of KP between gate-source

voltages of -6 V and -24 V might be due to the presence of source-side contact resistance.

Moreover, the shape of VSat and KP implies that Psi-TFT or Linvar modeling is not neces-

sary for the transistor. Instead, the VGS -dependent development of the parameters indicates a

Level-1 model including contact resistances. However, for gate-source voltages above -5 V,

the Level-1 model will fail and produce current values far in excess of the measured values

because a Level-1 model would not map the decline of the process conductance parameter

KP between -5 V and 0 V. When using a source-side compensation resistor of RCS = -400

kΩ, KP can be stabilized to 21 pA/V2 for VGS < -10 V with VT = -0.7 V, λ = 0.001 V−1 . The

compensation resistor indicates a source-side contact resistance of RSC = −RCS = 400 kΩ. It

should be noted that such a Level-1 model including a source-side resistor will nonetheless

fail to match device behavior for |VGS | < 5 V.

In this section, the drain current of a P3HT transistor is analyzed using the VSat method and

modeled with the Linvar approach. The device characteristics were obtained from activities

within the research project POLITAG4 . The results of the measurements, extractions, and

approximations with the Linvar model are shown in Fig. 4.12. Solid lines mark measured

I/V curves or parameters extracted with the VSat method. Dashed lines and/or cross markers

indicate approximations with the Linvar model. The plots show that the Linvar model sup-

plies a reasonably good fit. Model parameters in the Linvar model were KP0 = 8 pA/V2 ,

fk = -2 pA/V3 , VT 0 = 2.4 V, fT = 0.2 V, λ0 = 5 mV−1 , fλ = 0 V−2 . In order to better ap-

proximate the drain current at zero gate-source voltage, a normalized parallel resistor with

4

The devices were fabricated in top-gate structure by lithographic structuring of gold electrodes. Spin-coating

was used to deposit the semiconductor. Detailed specifications of the fabrication process were not provided by

the device manufacturer, a commercial source participating in the research project POLITAG. This project was

funded by the German Ministry for Education and Research (BMBF) under the ID 01BI150.

88 Chapter 4. VSat Method

a) b)

1.0u 0.0

VGS = 0.0 V

0.0u

−1.0u -10.0 V −5.0

−2.0u -12.5 V

−10.0

VSat [V]

−3.0u -15.0 V

ID [A]

-17.5 V

−4.0u

-20.0 V −15.0

−5.0u

-22.5 V

−6.0u −20.0

-25.0 V

−7.0u -27.5 V

-30.0 V

−25.0

−30.0 −25.0 −20.0 −15.0 −10.0 −5.0 0.0 −30.0 −25.0 −20.0 −15.0 −10.0 −5.0 0.0

VDS [V] VGS [V]

c) d)

25.0p 0.40

0.35

20.0p

0.30

0.25

KP [A/V2 ]

15.0p

λ [V−1 ]

0.20

10.0p 0.15

0.10

5.0p

0.05

0.0 0.00

−30.0 −25.0 −20.0 −15.0 −10.0 −5.0 0.0 −20.0 −15.0 −10.0 −5.0 0.0

VGS [V] VGS [V]

Fig. 4.11: Extraction of relevant parameters for a PDHTT transistor with channel width

W = 10 mm and channel length L = 10 µm: a) output characteristics (taken from [95]), b)

saturation voltage, c) process conductance, and d) channel-length modulation.

4.4. Chapter Summary 89

Rpar

′

= 10 TΩm was introduced between source and drain of the transistor (effective value

Rpar = 1.67 GΩ). This parallel resistor can be attributed e.g. to bulk conductance of the de-

vice.

Alternatively, the device can be approximated using the Psi-TFT model. When apply-

ing the procedure described in Section 4.3.2, the following model set is obtained by calcu-

lations: Cis = 1 · 10−7 F/cm2 , µ1 = 2.5 · 10−5 cm2 /Vs, VT = 2.9 V, αsat = 0.8, mµ = 0.886,

λ = 0.005 V−1 . Here, Cis and µ0 are arbitrarily interchangeable5 . Apart from subthreshold

behavior, which has been neglected in this example, the parameter set for the Psi-TFT model

shows good agreement with the experimental data (not depicted in Fig. 4.12a). Here, the Psi-

TFT model performs even better than the Linvar model. This better agreement is at the cost

of a more challenging extraction procedure, however.

4.3.7 Conclusions

Section 4.3 deals with the modeling of organic transistors. The analysis is based on the VSat

and Linvar methods of parameter extraction. In principle, the VSat method indicates appro-

priate models for a particular device by showing the linearity and slope of the VGS -dependent

parameters.

The findings in Section 4.3.5 and Section 4.3.6 show that different transistors can consid-

erably differ in behavior. Therefore, it is difficult to find model equations which are suitable

for a wider range of transistors. The dependence of model parameters could be approximated

by fitting polynomials. This technique was analyzed in [94] but polynomials still fail to cor-

rectly map the KP behavior presented in Section 4.3.5. Moreover, mere fitting polynomials

do not comply with the requirement of compact device models derived in Section 3.1 because

numerous and obscure fitting parameters are introduced. The Linvar model is also a fitting

model but uses only as few parameters as possible.

In this chapter, a methodology for extracting parameters of transistor models in a two-step

approach was described. In a first step, the saturation voltage of individual output charac-

teristics ID vs. VDS at fixed VGS values are extracted by a one-dimensional search routine.

The methodology is centered on the derivation of the saturation voltage. Hence, it is called

VSat method. Once VSat has been obtained, Level-1 parameters are calculated analytically for

the individual output characteristics. The advantage of this approach is that no user interac-

5

Due to the fact that information on the relative permittivity and insulator thickness of the device was not

available, the default value has been chosen for Cis .

90 Chapter 4. VSat Method

a) 1.0u b) −2.0

VGS = 0 V −4.0

0.0

VGS = -4 V

−6.0

−1.0u VGS = -8 V

−8.0

VSat [V]

−2.0u VGS = -12 V

ID [A]

−10.0

−3.0u −12.0

VGS = -16 V −14.0

−4.0u

−16.0

−5.0u V = -20 V extraction

GS measurement −18.0 approximation

approximation

−6.0u −20.0

−30.0 −25.0 −20.0 −15.0 −10.0 −5.0 0.0 −20.0 −15.0 −10.0 −5.0 0.0

c) VDS [V] d) VGS [V]

55.0p 40.0m

extraction extraction

50.0p approximation approximation

35.0m

45.0p

40.0p 30.0m

35.0p

KP [A/V2 ]

λ [V−1 ]

25.0m

30.0p

25.0p 20.0m

20.0p

15.0m

15.0p

10.0p 10.0m

5.0p

0.0 5.0m

−20.0 −15.0 −10.0 −5.0 0.0 −20.0 −15.0 −10.0 −5.0 0.0

VGS [V] VGS [V]

Fig. 4.12: Extraction of relevant parameters for a P3HT transistor with channel width

W = 6 mm and channel length L = 10 µm: a) output characteristics, b) saturation voltage,

c) process conductance, and d) channel-length modulation. Measured and extracted data are

shown by solid lines, approximations by the Linvar model are shown by dashed lines and/or

cross markers.

4.4. Chapter Summary 91

tion is necessary regarding initial values or parameter bounds for the parameter extraction.

Therefore, the method can be carried out fully automatically.

By observing the VGS -dependent shapes of the basic Level-1 parameters, viable modeling

approaches (e.g. Psi-TFT, Level-1 modeling, etc.) can be identified and the respective models

can be applied in the second step. Currently, the only models directly using all of the interme-

diate Level-1 parameters are a VSat -type table model and the Linvar model, both presented in

this chapter. VSat -based analysis of more complex models like the Psi-TFT model currently

only uses a small fraction (viz. VT ) of the intermediate parameters in the derivation of their

own parameter values. In future work, mapping of the full range of intermediate parameters

to selected transistor models could be elaborated.

In conclusion, the VSat method can contribute to modeling by providing a fully automated

way of deriving intermediate parameters which can be used a) to select feasible transistor

models for measured output characteristics, and b) to refine these intermediate parameters

into parameters for more complex models.

92 Chapter 4. VSat Method

93

Chapter 5

In this chapter, standard procedures used for characterizing OFET-based logic circuits will

be presented. First, commonly-used circuit concepts realizing OFET-based logic gates will

be discussed. Then, methods of assessing robustness and timing-related performance figures

of logic gates are detailed. Subsequently, existing tools for characterizing logic circuits are

reviewed. The discussion aims at identifying useful performance figures which quantify the

performance of certain OFET generations or circuit technologies as well as requirements of

circuit analysis on an integrated analysis framework.

Logic gates are the principal building blocks of logic circuits. They can be considered as com-

binations of “switching elements” used for computing operations from the Boolean algebra.

The most basic logic gate in a logic family is the inverter. In OFET-based logic circuits,

it is commonly represented in the form of a pull-down and a pull-up element switching the

inverter’s output to ground (GND) or to the supply voltage (VDD ) via a low-resistance path.

Fig. 5.1 shows the schematics of commonly-used configurations of inverters.

In circuits operating with only one type of semiconductor (either n-type or p-type) for

both the pull-up and the pull-down element, the input of the inverter is connected to an input

or driving transistor. This transistor can shortcut the output to GND if the proper voltage

is applied. The pull-up element is then realized by a load transistor where the gate is either

connected to its source or to its drain. If the gate is connected to the source, a fixed gate-source

voltage VGS = 0 V results. This configuration will only work if the transistor is switched

94 Chapter 5. Analysis of OFET-Based Logic Circuits

a) b) c) d) e)

VDD VDD VDD VDD VDD

ML ML MP U MP U RL

Q Q A Q A Q Q

A MD A MD MP D MP D A MD

Fig. 5.1: Basic configurations to implement an inverter: a) Load transistor (ML ) in current-

source load configuration, b) load transistor (ML ) in diode load configuration, c) comple-

mentary pull-up (MP U ) and pull-down transistors (MP D ), d) complementary-like ambipolar

transistors (MP U and MP D ), and e) load resistor (RL ) configuration.

mode in literature (e.g. [96, 97]). A normally-on transistor in this configuration yields an

approximately constant drain current as long as it operates in the saturation region. Hence, the

configuration of a load transistor with the gate connected to its source is referred to as current-

source load (CSL) configuration in this work following the definition of current-sourcing

load used by [98]. Fig. 5.2 shows the relationship between the output characteristics of the

transistors of a CSL-type inverter and its voltage transfer characteristic (VTC), which is the

plot of the output voltage vs. the input voltage. The numbered circles in both plots of the

figure denote corresponding operating points in the output characteristics and the VTC.

a) b) c)

VDD

drain current (driving trans.)

1

load

output voltage

transistor

output drain current

(load trans.)

input

driving 2

transistor 54 2

3 3 4

1 5

0

0 output voltage VDD 0 input voltage VDD

Fig. 5.2: Relationship between output characteristics and VTC of a CSL-type inverter:

a) schematic, b) output characteristics of driving and load transistor, and c) resulting voltage

transfer characteristics. The numbered points in b) and c) correspond.

5.1. Logic Circuits 95

If the gate of the load transistor is connected to the drain, a fixed gate-drain voltage

VGD = 0 V results. This configuration does not rely on a normally-on transistor and yields

an output characteristic similar to a diode for the pull-up transistor. Therefore, this configura-

tion will be referred to as diode load (DL) configuration in the following. OFET-based logic

gates in diode load configuration have been presented e.g. in [3].

Logic circuits in OFET technology usually employ load and input transistors of the same

semiconductor material. There are also reports on circuits using normally-off input and

normally-on load transistors fabricated in laboratory setups. Normally-off or enhancement-

mode means that the transistor is switched off at a gate-source voltage of zero. For example,

Lee and colleagues [99] reported p-type inverters based on pentacene where the input transis-

tor operated with a negative threshold voltage and the load transistor with a positive threshold

voltage. The threshold voltage of the driving transistor had been shifted by a special treatment

of the insulator-semiconductor interface so that the device was switched off at a gate-source

voltage equal to zero. The combination of an enhancement-mode input and a depletion-mode

load transistor is a concept that was commonly used in the early days of MOS integrated

circuits and is referred to as enhancement-depletion (E/D) logic [97, 100].

The pull-up element can also be a transistor of complementary semiconductor type, i.e. n-

type charge carriers if the pull-down transistor is p-type and vice versa. This configuration is

usually employed in state-of-the-art logic circuits and is referred to as CMOS (complementary

metal-oxide semiconductor1) logic [37, 101]. In CMOS-type inverters, both the gate of the

pull-up and the gate of the pull-down transistor are connected to the input. Examples of

organic complementary circuits can be found in [102, 103].

Alternatively, the transfer characteristics of ambipolar OFETs (see Section 3.2.8) can be

exploited to design inverters with CMOS-like voltage-transfer characteristics as shown in

Fig. 5.3. Unlike inverters with true normally-off complementary transistors, ambipolar in-

verters never reach the supply rails. This fact also complicates the implementation of more

complex logic gates like NANDs or NORs, because ambipolar transistors in series connec-

tions do not fully switch off.

Another option is to use a resistor as the pull-up element connecting the output to the

supply rail VDD . Examples of circuits utilizing resistor loads have been presented e.g. in

[104].

1

The expression MOS (metal oxide semiconductor) originates from the early material structure of inversion-

layer CMOS transistors consisting of a silicon dioxide (SiO2 ) dielectric sandwiched between a metal gate and

the semiconductor.

96 Chapter 5. Analysis of OFET-Based Logic Circuits

100

VDD

80

output voltage

60

Input Output

40

20

0

0 20 40 60 80 100

input voltage

5.1.2 Enhancements

The fact that most organic semiconductor materials exhibit weakly normally-on or weakly

normally-off behavior leads to poor performance of the input transistor as it can only be

switched off with difficulties. Unless the complementary-type circuit concept is used, the

logic levels are determined by the ratio between the channel resistance of the input transistor

at a given gate-source voltage and the resistance value of the load element. The switch-off be-

havior of the input transistor can be improved by applying a positive voltage at its gate. This

observation led to the realization of level shifter concepts in OFET-based logic circuits [85].

In principle, the initial logic block is followed by an output stage which shifts the output volt-

age to more favorable voltage levels. For p-type semiconductors, output voltages around zero

are shifted to positive voltages. This technique has already been described in the early 1960s

for transistor-based logic gates [105] and has also frequently been used in logic circuits em-

ploying normally-on gallium-arsenide transistors under the name Buffered FET Logic (BFL)

[106]. With a level-shifter concept, however, an additional supply voltage is required and the

real estate and wiring complexity of circuits increases. Fig. 5.4 shows the schematic of an

inverter in level shifter configuration.

Other researchers switched from static to dynamic logic. Pull-up elements in ratioed logic

are implemented by the same types of transistors as pull-down elements and are statically

driven. If the transistors operate in current-source load configurations the sink current pro-

vided by the pull-up transistor is considerably lower than the drive current provided by the

pull-down transistor. An increased width-to-length ratio of the pull-up device boosts its sink

current but also its gate capacitance. The increased capacitance will limit the attainable circuit

speed. Use of a diode load configuration considerably reduces the parasitic capacitance at the

cost of a reduced noise margin (see Section 5.3.2) of the logic gates. In order to improve the

5.2. Circuit Characterization 97

VDD

M2 M4

A M1 M3

VSS

performance of OFET-based logic circuits, dynamic circuit concepts have been investigated.

Huitema et al. [107] reported on a logic circuit utilizing pentacene transistors and a 120-stage

shift-register with 2,160 transistors in a dynamic circuit concept. The basic idea of a dynamic

circuit concept is to add a clock input to the logic gates. This clock is used for dividing the

operation of the gate into two phases: setup (also called precharge) and evaluation phase. In

the setup phase, the output of the gate is precharged to the logic high voltage regardless of the

input values. In the evaluation phase, the output goes to the low level if the configuration of

the input signals forces it to do so, but will otherwise stay at the high level. Details about the

actual OFET-based implementation were not given in [107] but the concept of dynamic logic

is frequently used for implementing high-speed silicon-based logic circuits. Fig. 5.5 shows

the schematic of a NOR gate in dynamic logic. During the precharge phase, the input PRE is

used for charging the output to the voltage level VDD while the inputs A and B stay at GND.

In the subsequent evaluation phase, the output may go to ground potential, depending on the

states of the inputs.

Circuits are frequently implemented by combining prebuilt cells with different functionality in

order to implement the desired behavior [108]. Normally, chip manufacturers supply libraries

of the cells that can be used for developing the circuit with software for computer-aided circuit

design. These libraries contain specifications of the cells which describe their functional and

electrical behavior.

There exist tools for characterizing the electrical behavior of cells using circuit simulation.

These tools generate testbenches, carry out circuit simulations, and compile characterization

98 Chapter 5. Analysis of OFET-Based Logic Circuits

VDD

PRE

A B

Fig. 5.5: Schematic of a NOR gate in a dynamic logic configuration. The input PRE is used

for precharging the output to VDD via the load transistor.

In the domain of logic circuits, the following properties are characterized [108, 109]:

2 Input capacitance.

These characteristics and especially the first two (logic levels/noise margin and timing) can

also be used for evaluating the performance of an OFET technology. Therefore, it is worth-

while to take a closer look at the mechanisms of the characterization process. The following

two sections will provide a discussion of methods characterization robustness (Section 5.3)

and timing (Section 5.4).

Robustness is discussed because most OFET-based logic circuits suffer from non-ideal

VTCs. The unity-gain method as the standard procedure for analyzing noise margins of logic

circuits (see Section 5.3.3) can only be applied with care. Timing characterization is discussed

because standard methods of deriving delay times and other timing data often assume well-

behaved clocking signals (with sharp slopes) which are not frequently used in low-cost organic

circuits. Therefore, alternate characterization methods have to be investigated.

Other characteristics will not be detailed in the following owing to the fact that standard

methods described in literature [37, 106, 110, 111] can readily be applied to organic logic

5.3. Characterization of Robustness 99

circuits. Moreover, these characteristics are more important for experienced chip designers

than for the analysis of the general performance potential of OFET technologies.

One important characteristic of logic circuits is their robustness. It defines the ability of a logic

circuit to safely detect and issue valid voltage levels for the distinct logic states in the presence

of adverse noise at the input signals. In a general way, noise is defined as any deviation from

nominal voltages [112]. Sources for noise can e.g. be [113]:

point variations.

For OFET-based logic circuits, the contribution of device variations is more important

than spurious signals owing to the low packing density of organic logic circuits [114] and the

early stages in the fabrication technology. Several possibilities exist to derive information on

the robustness of logic circuits. A selection of these will be discussed in the following. First,

the method of equilibrium zones will be discussed as it helps defining valid voltage levels for

logic circuits in the presence of VTC variation. At its core, this method is only a qualitative

approach. Therefore, the concept of noise margin is presented as it introduces figures of merit

which can be measured. Then, the unity-gain method is detailed. It is the standard method for

state-of-the-art integrated circuits using CMOS devices but occasionally fails in assessing the

robustness of organic logic circuits. Therefore, the method of maximum squares is discussed

which is often used in non-CMOS circuits to analyze robustness. Finally, methods inspecting

certain gain values of the VTC are reviewed.

Pierce [115] treated the problem of tolerance and robustness in 1963 by inspecting signal

regeneration in the presence of VTC variations. He introduced “equilibrium zones” in order

to assess the compatibility between different types of logic gates. In the following text, this

method will hence be referred to as method of equilibrium zones in the following. To the

best knowledge of the author of this work, Pierce’s method is not used in other literature on

noise-margin calculations.

The method of equilibrium zones starts by inspecting the VTC of a single-input non-

inverting buffer performing the Boolean identity operation Q=A, where A is the input and Q

the output. The voltage Vout at the output Q of the non-inverting buffer is some function f of

100 Chapter 5. Analysis of OFET-Based Logic Circuits

the input voltage Vin at the input A, i.e. Vout = f (Vin ). A stable VTC has three equilibrium

points where Vin = Vout (see Fig. 5.6):

If identical buffers are arranged in a long chain of gates with the output of each gate

connected to the input of its successor then the following relationship between the input Vin,1

of the first gate and the output Vout,m of the last gate is given by:

Vin,1 = VM ⇒ Vout,m = VM , (5.1)

Vin,1 > VM ⇒ Vout,m = VH .

VM marks the boundary between valid voltage levels for the low and high states with

Vout

VDD

VH

VM

A 1 Q

Vin Vout

VL

Vin

0 VL VM VH VDD

However, one single VTC for all gates is not realistic. Real gates will display slight

differences in their VTC shapes owing to parameter variations or switching noise. In these

cases, upper and lower bound VTCs can be defined and used for the preceding equilibrium

5.3. Characterization of Robustness 101

analyses. In the presence of upper and lower bounds, the analysis will yield equilibrium zones

instead of single equilibrium points (see Fig. 5.7). These equilibrium zones define regions

in which the final equilibrium points will lie. The points cannot be stated exactly owing to

the statistical nature in which the individual VTCs vary. More importantly, it is not known

in the region belonging to the metastable equilibrium points whether the output will increase

or decrease between two or more stages and eventually lead to a stable output high or low

voltage. Hence, the middle region is called indeterminate zone in [115]. Valid logic levels are

required to avoid the indeterminate zone.

low

indeterminate

output voltage

lower bound

upper bound VTC

VTC

high

0 input voltage

Fig. 5.7: Determination of equilibrium zones of non-inverting buffers using upper and lower

bound VTCs. The individual equilibrium points are marked by circles.

The method of equilibrium zones can also be extended to inverters and more complex

gates. In the case of inverters, simply a pair of two gates is combined so to implement the

identity operation and getting plots in the form of Fig. 5.7.

Worst-case combinations of pairs of two inverters have to be considered in order to derive

the equilibrium zones. In spite of that, these zones are readily available when plotting the

upper and lower bound VTCs in a diagram together with their reflections about the x = y line

(see Fig. 5.8). Therefore, it is not necessary to calculate the VTC of the pair of inverters.

By use of the reflection, values on the x axis serve both as input of the first and output of

the second inverter while values on the y axis serve both as output of the first and input of the

second inverter. At each intersection between a true and a reflected VTC, an equilibrium point

of the VTC of the respective pair of inverters is located. This is due to the fact that there, the

second inverter will transform its input voltage to a value equivalent to the input voltage of

the first inverter.

Once the equilibrium zones have been established their positions can be drawn in a dia-

102 Chapter 5. Analysis of OFET-Based Logic Circuits

indeterminate

1 1

output voltage, first inverter

first second

inverter inverter

high

low

output voltage, second inverter

Fig. 5.8: Determination of equilibrium zones for pairs of inverters by plotting true (solid lines)

and reflected curves (broken lines) of the upper and lower bound VTCs. The individual equi-

librium points are marked by circles. The inset shows the constellation of the two inverters.

gram to test the compatibility of gates with different equilibrium zones (see Fig. 5.9). If gates

are to be interconnected their indeterminate zones must not coincide with either the high or

low equilibrium zones of their partners in order to yield regenerating signals.

Driving Gate

0 VDD

Sensing Gate

low ? high Voltage

0 VDD

Fig. 5.9: Compatibility diagram of two gates of different types. The boxes with the question

marks denote the indeterminate zones.

A drawback of the method of equilibrium zones is that, in its original form, it is only a qual-

itative tool. In order to compare the performance potential of different circuit or device tech-

nologies by numbers, the concept of noise margin is helpful.

The noise margin can be calculated by defining four critical voltage levels in a VTC. An

5.3. Characterization of Robustness 103

inverter as the simplest form of logic gate detects and issues logic states according to the

following relationship between input voltage Vin , output voltage Vout , and the four critical

voltage levels VIL,max , VIH,min , VOL,max , and VOH,min [116, 117]:

(5.3)

Vin > VIH,min ⇒ Vout < VOL,max .

Here, VIL,max (VIH,min ) is the maximum (minimum) allowable voltage level for the logic

low (high) level at the input, VOH,min (VOL,max ) is the minimum (maximum) allowable voltage

level for the logic high (low) level at the output. Moreover, positive voltages are assumed. The

relationships in (5.3) give rise to the voltage tolerance between inputs and outputs [116] as

(5.4)

NML = VIL,max − VOL,max .

The tolerance of a gate against variations of the input voltages is defined in terms of the noise

margin NML for the logic low level and NMH for the logic high level. In order to get both

NML > 0 and NMH > 0, the following relationships are required:

0 < VOL,max < VIL,max < VIH,min < VOH,min < VDD . (5.5)

The diagram in Fig. 5.10 can be used for visualizing the definitions in (5.4) and (5.5). In

the lower part of the figure, two gates are connected via a noisy path. It should be stressed that

noise sources can be spurious signals or variations in the transistors of the gates. The upper

part of the figure represents the graphical equivalence of (5.4) and (5.5)

There exists no general rule for the definition of the critical voltages VIL,max , VIH,min ,

VOL,max and VOH,min . Although the method of equilibrium zones can be used for defining

the critical voltages (see Fig. 5.11), this approach is not used in literature on noise margin

calculations. Instead, the unity gain method presented in Section 5.3.3 is often used. For

OFET-based logic circuits, however, it will sometimes predict negative noise margin for fully

functional logic gates.

A simple graphical test to determine whether a particular gate complies with given noise

margins [116] can be carried out. In the test, the VTC f (Vin ) of the gate is drawn in the VTC

box and the shaded areas where Vout < VOH,min for all 0 < Vin < VIL,max and Vout > VOL,max

for all VIH,min < Vin < VDD . A valid VTC does not enter these shaded areas (see Fig. 5.12).

104 Chapter 5. Analysis of OFET-Based Logic Circuits

VOU T VIN

VDD

VOH,min

NMH

VIH,min

VIL,max

NML

VOL,max

1 noise 1

gate M gate M + 1

VIL,max VIH,min

low ? high

Voltage

0 VOL,max VOH,min VDD

Fig. 5.11: Definition of critical voltages using the method of equilibrium zones.

Vout

VDD

VOH,min f (Vin )

VOL,max

0 Vin

0 VIL,max VIH,min VDD

5.3. Characterization of Robustness 105

A popular approach to determine VIL,max , VIH,min , VOL,max and VOH,min is the unity gain ap-

proach (see [116] and the references therein). Currently, it is the method of choice in the deter-

mination of noise margins of CMOS gates. In this approach, VIL,max and VIH,min are given by

the -1 slope points in the VTC. The output voltages can be defined as VOH,min = f (VIL,max )

and VOL,max = f (VIH,min ), see Fig. 5.13. This setup maximizes the sum of the two noise

margins [118]

The maximum value can be derived by finding the zero of the derivative of NML +NMH with

respect to VIL,max and VIH,min . Zero is reached at the unity gain points where the relations are

df (VIL,max )/dVIL,max = −1 and df (VIH,min )/dVIH,min = −1. The reader should note that

negative noise margins can occur for either NML or NMH .

Vout

VDD

VOH,min slope −1

VOL,max

slope −1

0 Vin

0 VIL,max VIH,min VDD

A drawback of the unity gain method is that defining VIL,max and VIH,min by the -1 slope

points is not a necessary condition when checking the validity of a VTC. Therefore, this

approach sometimes leads to negative noise margins for logic circuits because one of the -1

slope points does not exist. A negative value for a VTC would suggest that no regeneration of

input voltages to valid logic levels is possible. However, this is not true as can be seen from

the example in Fig. 5.14. For the VTC depicted in the figure, the unity gain method fails in

106 Chapter 5. Analysis of OFET-Based Logic Circuits

the calculation of the noise margin as only one -1 slope point exists. Yet, the VTC possesses

three equilibrium points and hence, stable voltage levels for logic high and low exist.

Vout

VDD

reflected VTC

inverter VTC

slope −1

VOL,max

Vin

0 VIH,min VDD

Fig. 5.14: Inverter VTC where the unity gain method fails but valid logic levels exist.

Another problem of the unity gain method is that taking the critical values VIL,max , VIH,min ,

VOL,max , and VOH,min from a single VTC is not reasonable as device variations can alter the

VTC shapes. As a solution to this problem, upper and lower bound VTCs can be derived and

worst-case points for the critical values can be selected from these.

The problem of noise margins was treated in [119, 120] by inspecting an infinite chain of

inverters with identical VTCs. Noise can be modeled by voltage sources in series to the inputs

of the inverters in the chain. The worst-case noise condition occurs when noise sources are

present at the inputs of all gates with all low gate and high gate noise sources contributing in

the most deleterious way. This happens when driving the logic low inputs toward logic high

values and the logic high inputs toward logic low values.

In terms of noise analysis, the infinite chain of inverters together with their associated

noise sources can be substituted by a latch consisting of two cross-coupled inverters with

noise voltages in series to the inputs. In this configuration, only two inverters and two noise

sources have to be treated. The noise analysis is used for determining the noise levels which

force the latch to switch from a stored to the other logic state and consequently cause the

memory element to malfunction. The analysis can be carried out by inspecting the VTC of

the first inverter in the latch together with a reflection about the x = y line so that for the

5.3. Characterization of Robustness 107

second inverter in the latch, the y axis serves as the input axis and the x axis as its output

axis. The same graphical representation was also used by Pierce [115] (see Section 5.3.1).

The latch retains the stored logic state as long as the two curves continue to intersect in three

points [121] even in the presence of deleterious noise, which will somehow shift the curves.

Fig. 5.15 shows a graphical representation of the extraction scheme. The latch in the left

part of the figure is used in the analysis and is equipped with noise sources. First/second

VIN /VOU T in the diagram are the input and output voltages of the first and second inverter.

In order to obtain the noise margin for the worst-case series voltage, the maximum possible

square between the normal and reflected VTC is considered. The noise sources with maximum

allowable amplitude Vn,max are represented by the equally-sized sides of the maximum square

within the loop. Upon exerting Vn,max at both noise sources in Fig. 5.15, the points of the

true and reflected VTCs at the corners of the maximum square coincide and there is only

one intersection point for both VTCs. For detrimental noise sources with amplitudes below

Vn,max , there still exist three intersection points between the two.

VDD

noise first

source inverter Vn,max

input voltage, second inverter

output voltage, first inverter

1 Vn,max

1

noise second

source inverter

0

0 input voltage, first inverter VDD

output voltage, second inverter

The approach yields the maximum square noise margin and hence, equal noise margins

for logic low and logic high states. In real gates, attainable noise margins for the logic high

and logic low stare are normally not equal [116]. Therefore, it is sometimes more favorable to

consider the maximum possible product between the noise margin for the logic low and logic

high state. However, the calculation of the maximum square is far more feasible than the

calculation of the maximum product. The maximum square noise margin can be calculated

by rotating the true and reflected VTCs by 45° and then calculating the differences between

the two curves. These differences are equivalent to the diagonals of the squares between

108 Chapter 5. Analysis of OFET-Based Logic Circuits

diagonal points of the two VTCs. The calculation of the differences can even be carried out

in a circuit simulator as demonstrated by Seevinck and colleagues [122]. The procedure in

[122] consists of searching for the longest diagonal between the true and reflected VTC. Upon

rotating both curves by 45°, the original (x, y) coordinate system is translated into a (u, v)

coordinate system. In the latter coordinate system, the v values of the true and mirrored VTCs

can be subtracted in order to yield the diagonal. The magnitudes of the maximum positive

and maximum negative values correspond to the diagonal of the maximum square between

the two curves (see Fig. 5.16). [122] describes the true and reflected VTCs by the functions

y = F1 (x) and y = F2′ (x). F1 represents the true VTC and F2′ the reflected VTC of a second

gate with VTC F2 . Owing to process variations or worst-case considerations, F1 and F2 may

differ. The transformation from (x, y) to (u, v) is

1 1

x = √ u + √ v, (5.7)

2 2

1 1

y = − √ u + √ v, (5.8)

2 2

√

1 1

v = u+ 2F1 √ u+ √ v (5.9)

2 2

√

1 1

v = −u + 2F2 −√ u + √ v . (5.10)

2 2

(5.9) and (5.10) can be used for calculating v as an implicit function of u. The maximum

value of the absolute difference between the two vs is equivalent to the maximum-square noise

√

margin times 2. The solutions for v can be calculated in a circuit simulator using the setup

depicted in Fig. 5.17.

The noise margin as defined by the method of maximum squares is not compatible with

the graphical test from Fig. 5.12. Unlike the unity gain method, it can easily cope with the

problem shown in Fig. 5.14. As long as there exists an opening in the loop between true and

reflected VTCs, a noise margin according to the method of maximum squares can be derived.

Like in the case of the unity gain method, calculating the maximum square from a single

VTC is not reasonable as device variations can alter the VTC shapes. Upper and lower bound

VTCs can be used for calculating worst-case maximum squares.

In work dealing with OFET-based noise margin calculations, the method of maximum

squares is preferably used (see [114, 123, 124]).

5.3. Characterization of Robustness 109

F1

v

F2′

45◦

x

F1 (u) − F 2′ (u)

Fig. 5.16: Extraction of maximum-square noise margin using a coordinate system rotated by

45° (adaption from [122]).

In Section 5.3.1, the robustness of logic gates was treated by introducing the three equilibrium

points VL , VM , and VH for identity gates. VL and VH are stable equilibrium points while VM

between them is metastable. Metastability is reached by a gain or slope of the VTC curve

at VM in excess of unity. For inverters, the VTC of a pair of inverters is inspected in order

to yield a logic identity function. If both inverters have identical VTCs, VM corresponds to

the intersection between the inverter VTC and the curve Vout = Vin . The inverter gain GI

at Vin = VM is critical to the robustness of the gates. Hence, the expression critical gain is

used in this work for gcrit = GI (VM ). In the case of inverters, the gain of the inverter pair

G(VM ) = G2I (VM ) so that |GI (VM )| > 1 is required. Conventionally, GI (Vin ) ≤ 0 for all

sensible input voltages of an inverter so that a critical gain

is required for robust operation. Therefore, the critical gain can be used as a qualitative figure

which represents the robustness of an inverter. To the knowledge of the author of this work,

the concept of critical gain is not used elsewhere in literature on noise-margin calculations.

Instead, the maximum negative gain gmax = max |GI | is sometimes used in other publications

110 Chapter 5. Analysis of OFET-Based Logic Circuits

F1

1

+

+ √1 v1

2 +√

−

u +

vout 2vout + u v1

− √1 u

−

− 2

F2

1

+

+ √1 v2

2 +√

−

u +

vout 2vout − u v2

− −

− √12 u

−

The difference between the critical gain and the maximum negative gain can be explained

by using the inverter gain and VTC plot in Fig. 5.18. The plots show typical simulation results

for an inverter in current-source configuration. Channel length and width of the driving tran-

sistor were L = 5 µm, WD = 1500 µm, and for the load transistor L = 5 µm, WL = 12 mm. In

the simulation, the driving transistor was mapped by a Linvar model while the load transistor

was mapped by a Level-1 model specifically tailored toward reproducing the zero VGS curve.

More details about the simulations can be found in Section 6.3.1. The following values can

be extracted from the plot: VM ≈ -5.15 V, critical gain gcrit ≈ -2.1, gmax ≈ -8.3.

In the VTC, gcrit lies close to the negative unity gain while gmax is located farther away.

This behavior is typical of OFET-based logic circuits without complementary devices for

the pull-up and pull-down path. As will be shown on p. 142, the critical gain has a closer

relationship to the noise margin than the maximum negative gain.

The method of equilibrium zones relies on knowledge about upper and lower bounds for the

VTC. This complicates application of the method because these bounds have to be found by

worst-case analysis, e.g. by time-consuming stochastic simulations or by knowledge about the

influences of the device parameters. This knowledge has to be established beforehand for the

logic family in use. On the other hand, the method of equilibrium zones yields a tangible way

of determining the compatibility of logic gates. This behavior is very important in the case of

ratioed logic which suffers e.g. from bias-induced parameter shifts. As another advantage, a

5.3. Characterization of Robustness 111

0 0

ratio = 8 −1

VTC

−2

output voltage [V] −−> −5

−3

ut

−4

tp

ou

−10

t=

−5

pu

in

−6

−15 −7

gain −8

−20 −9

−20 −15 −10 −5 0

input voltage [V] −−>

Fig. 5.18: Plot of inverter VTC and inverter gain for a gate in current-source configuration:

VM ≈ -5.15 V, critical gain gcrit ≈ -2.1, gmax ≈ -8.3.

sort of worst-case analysis is implemented by this method as the lower and upper bounds mark

the expectable VTC conditions. Noise introduced by parameter variation and subsequent VTC

shift is explicitly treated and therefore, a precise analysis of static noise margins is possible.

The unity gain method is mainly used in the analysis of modern CMOS circuits. Noise

margins can easily be extracted from a measured or simulated VTC by considering the points

where the derivative of dVout /dVin = −1. However, there exist conclusions ([116]) that only

techniques based on embedding some area within the true and reflected VTCs give reliable

noise margin values for a broad range of possible VTCs. These results are consistent with

findings in this work (cf. p. 142). For non-CMOS circuits, noise-margin considerations based

on the unity gain method easily yield negative noise margins although the maximum-square

method predicts the existence of positive noise margins.

With the method of maximum squares, the maximum square noise margin can easily be

obtained by simulation (see Section 5.3.1). A drawback of the method is that variations in

fabrication and environmental conditions are modeled with constant noise sources in the form

of series voltages. These variations lead nevertheless to nonlinear VTC changes. For example,

the noise margins for logic high and logic low states are affected differently as has been shown

in [126]. This problem could be solved by inspecting lower-bound and upper-bound VTCs in

a similar way as in the method of equilibrium zones.

Evaluation of the critical gain of an inverter VTC is a quick method of checking the ro-

bustness of the gate. The calculation of the maximum negative gain on the other hand is

more frequently used in literature on noise-margin calculations. It is more useful in the as-

112 Chapter 5. Analysis of OFET-Based Logic Circuits

sessment of CMOS-type gates with well-behaved VTCs. Both methods (critical gain and

maximum negative gain) suffer from calculation inaccuracies in the derivation of the gain

from the VTCs.

Generally, it is questionable whether voltage sources are sufficient to map the noise con-

tributions of parameter variations on VTC shapes in the derivation of noise margins. Further

investigation seems to be in order. For example, VT or λ shifts are more critical for the low

levels of CSL-type inverters (see Fig. 5.2). The resulting behavior will not be correctly repro-

duced by shifting the VTC with voltage sources. Instead, worst-case considerations of VTCs

need to be used for defining valid noise margins.

Timing characterization shows the attainable speed of a logic cell. Numerous timing figures

have been defined as meaningful performance figures: rise, fall, and delay times. They mea-

sure the response of a gate to a voltage pulse (e.g. [113]). The rise (fall) time is typically

measured from 10% to 90% (90% to 10%) of the difference between the logic low (high) and

logic high (low) state [101]. There also exist definitions using 20% and 80% thresholds [106].

The delay time tD represents the time interval between input and output levels being half way

between logic low and logic high states.

The delay time is an important timing figure in systems with a large number of logic gates

in series where the net delay between the input and the output of the system is large.

A step pulse is typically used for calculating the timing behavior of logic circuits. Analyti-

cal expressions have been derived to predict these times. Popular methods rely on simplifying

assumptions like constant capacitances or negligible influence of feedback effects in the cir-

cuits [127]. Moreover, the response time of a gate is normally longer than the transition time of

a step pulse at its input [128]. Hence, using step pulses overestimates the gate delay [129] and

more sophisticated analysis techniques have been developed to deal with the non-idealities of

logic gates (see e.g. [113, 128, 129, 130, 131, 132]).

Alternate definitions of relevant transition times can be found e.g. in [133], where the

input signal transitions are not restricted to unrealistically ideal steps but instead resort to

ramp signals with finite slopes. Fig. 5.19 details the definitions of the transition times, which

are derived as follows:

2 tf is the fall time indicating the time interval to decrease Vout from its 90% to its 10%

point. This time is also referred to as slew [134].

2 tr is the rise time indicating the time interval to increase Vout from its 10% to its 90%

point.

5.4. Timing Characterization 113

2 tdf is the high–to–low delay time indicating the difference between the 50% point of the

input rising transition and the 50% point of the output transition from high to low.

2 tdr is the low–to-high delay time indicating the difference between the 50% point of the

input falling transition and the 50% point of the output transition from low to high.

Vin (t)

VOH

50%

VOL

t

Vout (t)

tdf tdr

VOH 90%

50%

10%

VOL

t

tf tr

Fig. 5.19: Definition of switching times based on an input signal with ramp-like high and low

transition slopes.

In the case of unbalanced rise and fall times, an average propagation delay in the form of

tP = 21 (tP HL + tP LH ) can be defined. Alternatively, the pair delay tP D represents the delay

of a pair of identical gates. The pair delay is equivalent to the time delay between the time

points where the input of the first gate and the output of the second gate reach 50% of their

voltage swing [135].

The various response times presented in the preceding paragraphs always have to be re-

lated to the capacitive load of the gate under characterization, i.e. the fan-out. The fan-out

(FO) is a value counting the number of identical gates driven by a specified output [101].

An increase in fan-out leads to additional capacitance at the output of a gate. So, reports on

response times always need to specify the output capacitance for which the times have been

obtained. Similarly, a fan-in (FI) can be defined as the number of inputs a gate possesses

114 Chapter 5. Analysis of OFET-Based Logic Circuits

[101]. For example, a 4-input NOR gate has a fan-in of four. The fan-in can also be important

for the response times. This is due to the fact that input transistors influence the charging and

discharging of the output node by providing additional capacitance and/or leakage currents.

Schrom [125] points out that the relation between the response times and the average fan-

in/fan-out is difficult to derive. Numerous models have therefore been developed to predict

this relationship [125, 134].

For numerical analyses in simulations, valid voltage levels for high and low voltages are

needed in order to calculate the measurement points. In CMOS concepts, there is no need to

derive logic levels as usually VDD /10, VDD /2, and VDD can be assumed. Conversely, the real

values of both logic levels in ratioed logic depend on device geometries and parameter varia-

tions. Therefore, the voltage levels for these logic levels need to be established beforehand. A

practical approach in analysis, simulation, and measurement is to use ring oscillator circuits to

produce reasonable waveforms (e.g. [98, 125, 136]). A ring oscillator is a chain of inverting

gates with an odd number of stages. The simplest form of inverting gates can be inverters (see

Fig. 5.20) but other gates like NAND or NOR are also suitable. The output of each gate is

connected to the input of its successor. The output of the last gate is fed back to the input of

the first gate. This configuration leads to an oscillation with a frequency of f ≈ 1/(2ntD )

where n is the number of stages and tD is the delay per stage. The advantage of this approach

is that it yields the attainable voltage levels and transition times under realistic conditions. On

the other hand, n has to be chosen to be sufficiently large in order to allow the output voltages

of the gates to settle in response to rising and falling edges. But a large value for n also leads

to a long period time 1/f which has to be simulated.

1 1 1

Generally, the definitions of the transit times need to be used carefully because the results

depend on the input waveform and output load [125]. Due to different rise and fall times, even

negative delay times may occur [108]. In order to model the influence of input waveform and

output loading, logic cells are usually characterized by tables or equations that relate delay

time and output slew as a function of load capacitance and input slew. By using tables or

equations, timing models for logic simulation and circuit synthesis are possible. In this work,

performance figures are only used for comparing different device generations or logic families.

Consequently, these advanced techniques are considered to be beyond the scope of this work.

The interested reader is referred e.g. to [137] and the references therein for a more detailed

discussion of the topic.

5.5. Automation of Circuit Characterization 115

To carry out circuit characterization in an efficient way, a high degree of automation is re-

quired. Therefore, numerous software packages exist to aid the users in the process of circuit

analysis. In the field of OFET-based semiconductor technologies, the analysis results assist

in the optimization of devices. Design automation tools can be used for determining various

electrical characteristics of circuits. These tools are referred to as circuit characterization

tools and can be broadly separated into characterization tools for logic circuits and general

characterization tools.

Circuit characterization is frequently used for deriving various electrical characteristics of

logic circuits like timing, power consumption, or input capacitances in a form usable by digital

simulation and cell-based circuit synthesis. The latter transforms an abstract description of a

system into a real implementation by generating an integrated circuit. Logic cells like logic

gates or flip-flops are used as the building blocks of the system. The synthesis algorithms need

descriptions of these cells in order to take performance limits into account when numerous

inputs are connected to one single output, etc. Hence, issues like the determination of input

capacitance or timing behavior are emphasized in the characterization of logic circuits. The

focus in this domain is to provide simple models that can be used in calculations during the

synthesis or simulation process.

Characterization tools automatically characterize cells, i.e. provide model parameters use-

ful for logic synthesis, logic simulation, timing and power optimization, or create data books

for designers. SPICE simulations are typically used for measuring and extracting the electri-

cal parameters of logic cells. These parameters are calculated at individual process, voltage,

and temperature corners. A cell under characterization is embedded into a test circuit, where

it is evaluated with reasonable conditions.

A non-exhaustive list of commercial tools includes Z circuit ZChar [138], LibTech LibChar

[139], Synopsys NanoChar [140], Simucad AccuCell [141], or Magma SiliconSmart [142].

During the activities in this work, the author could only experimentally evaluate the open-

source characterization tool Autochar [111]. The other packages were evaluated using the

respective operation manuals, user reports, or conference presentations. Autochar is written

in the popular scripting language Perl and is used for circuit characterization with Synopsys

Star-Hspice or Silvaco SmartSPICE. The tool automates the generation of test circuits useful

in the extraction of load delay, input capacitance, setup and hold times for D-type flip-flops

(DFFs) as well as clock enable and clock-to-Q time for clocked DFFs (Q=output of the flip-

flop). Autochar is specifically tailored toward the characterization of CMOS-type circuits.

116 Chapter 5. Analysis of OFET-Based Logic Circuits

This property is reflected by the fact that e.g. delay times are measured between the fixed

thresholds of 10 and 90% of the supply voltage VDD . In order to be useful in timing analysis

for OFET-based circuits, Autochar would have to adapt to varying voltage ranges for logic

levels. Moreover, the package does not provide the determination of static noise margins.

The analysis flow is managed by a control file in Perl notation. References to netlists

and model sets are stored within this file as well as a specification of the desired analyses

and characterization conditions. The tool reads the control file and generates the relevant test

circuit according to the specifications of the input vectors, waveform slopes, and gate loads.

Then, the tool calls the simulator and retrieves all required information from the simulation

results. The data are interpreted and a characterization report is generated.

In contrast to commercial tools, Autochar does not provide sophisticated automation of

cell characterization. The package does not automatically analyze the structure of cells un-

der characterization in order to derive their logic functionality and required testbenches. It

is the responsibility of the user to define functionality and mode of input excitement. More-

over, there exists no graphical user interface. Instead, Perl-style configuration files have to be

written. On the other hand, Autochar is open source software. Users can readily extend the

functionality of the package. However, the last official release of the software dates back to

the year 2000. Other tools like AccuCell are more flexible when dealing with timing thresh-

olds but do neither include analyses for static noise margins (see Section 5.3.2) nor graphical

user interfaces.

In general, characterization software for logic circuits already implements standard analy-

ses necessary in the treatment of logic circuits (power consumption, circuit speed, etc.). Some

tools require only little work for the configuration of the analyses. These tools try to derive the

logic functionality by inspecting the structure of the cells under consideration. Yet, commer-

cial cell characterization packages are expensive tools where pricing starts at $55,000 [143].

Moreover, the tools mostly implement features not needed in the analysis of OFET-based

circuits with considerably lower structural complexity than the usual logic cells in CMOS li-

braries. On the other hand, simple analyses like the automatic determination of frequencies of

ring oscillators or static noise margins are missing.

The tools mentioned in the previous section focus on the treatment of logic circuits. In this

section, tools are discussed which characterize circuits in a general way. Normally, these

tools can also be used for automatically sizing the devices within a circuit, i.e. the lengths and

widths of the transistors or the resistance values of the resistors, etc., by use of optimization

strategies. There exist different tools with distinct applications, which also employ specific

5.5. Automation of Circuit Characterization 117

optimization schemes. Automatic sizing is less important for low-complexity circuits like

simple logic gates. These circuits can also be sized manually. Tools for circuit sizing get

important when circuits of higher complexities need to be implemented or optimized. In spite

of that, they provide interesting features for the analysis of OFET-based circuits like automatic

testbench generation or generic simulator interfaces. Hence, their evaluation is worthwhile.

In the following, a selection of tools with specific features is presented.

The schematic editor STAR [144] focuses on reusing designs in analog circuit design. The

idea is to add comments to circuit schematics in order to carry out predefined functions from

a library. An execution engine then processes these comments in order to generate necessary

computation routines. The goal of STAR is to create a flexible library which can be extended

with user-specified functions. The prototype tool is composed of four layers: a schematic

capture, a comment parser, an analysis layer, and a data processing layer at the bottom. The

system is implemented by a mixture of code in Tcl/Tk, Perl, and C. The central component

in STAR is the circuit schematic from which all further action is derived by inspecting the

comments embedded in it.

ASF (Analog Synthesis Framework) [145] employs simulation methods used by designers

to validate manual circuit designs during a circuit generation process. ASF incorporates mod-

ular, reusable, and user-configurable testbenches, which are called evaluators by the authors

of the package. The focus of ASF is to provide an easy-to-use and general tool where the

user can create any topology for any desired manufacturing process. The concept implements

an open framework for measuring arbitrary circuit characteristics with minimal effort. A ma-

jor goal of ASF is to feature a robust optimization and search heuristic that operates within

reasonable run-time. In order to achieve this goal, a stochastic search engine is employed for

solution finding. A special feature of ASF is to encapsulate simulators within an abstract layer

so that any simulator with an appropriate interface can be used with the package. This concept

is called simulator encapsulation.

A commercial sizing tool is NeoCircuit from Cadence [146]. It automates circuit sizing

and uses the designer’s simulator, testbenches, and transistor models to automatically evaluate

circuit solutions generated by its solver. All explored sizing candidates are preserved in a

database for further analysis. A user report on NeoCircuit is given in [147]. The tool features

a text console used for controlling the flow of the program as well as a graphical user interface

with almost the same functionality. For post-processing purposes, data can be exchanged with

the engineering software Matlab and its open-source clone Octave.

Conn and colleagues [148] report a sizing system called JiffyTune. It utilizes a circuit

simulator called SPECS and an optimization engine called LANCELOT. JiffyTune requires

the specification of a circuit schematic, input signals, a list of “tunable” transistors, with initial

widths, and a set of circuit performance requirements. The package determines the optimal

118 Chapter 5. Analysis of OFET-Based Logic Circuits

which uses simplified device models and event-driven simulation to decrease simulation time.

LANCELOT, the optimization engine, repeatedly calls the simulator with different settings

for the transistor sizes in order to model the performance of the circuit. The authors in [148]

note that JiffyTune is driven by a textual control file and requires knowledgeable users. Nev-

ertheless, it provides an interface to the Cadence design system.

The above-mentioned packages focus on sizing transistors for a particular design, i.e. de-

termining their optimal width and length. A more general characterization tool is the analysis

environment Decida, which was released as open-source in 2002 by Agere [149]. The envi-

ronment allows a circuit designer to customize the set of analyses, to control and integrate

design tools, and to provide analysis and plotting capabilities [150]. Decida is implemented

using the scripting language Tcl/Tk and can be extended very flexibly. Like JiffyTune, it

resorts to the optimization engine LANCELOT in order to optimize circuits.

The characterization tools discussed in this section focus on the characterization and/or

optimization of individual circuits. Therefore, their view and user concept centers on a par-

ticular design (e.g. operational amplifier, etc.) in the form of a netlist or schematic. Some

tools do not automatically generate testbenches. Instead, the users compose their own test-

benches and define which parameters to optimize. Other tools already provide pre-generated

testbenches or allow the users to compile reusable libraries of testbenches.

The OFET-based approach discussed in this work focuses on bringing together models

and circuits and carrying out analyses on the combination of both. The circuit is not central

to the analysis but the results obtained from combining it with the transistor models. This

approach is more similar to batch-mode circuit characterization of logic circuits. To carry out

this kind of analysis with the above-mentioned general analysis tools, an additional step of

compiling a tractable schematic description would be necessary. Moreover, the existing tools

do not provide special means to generate and manage device models or heterogeneous sets of

data (schematics, models, data vectors, etc.).

5.5.3 Discussion

Characterization tools come in two flavors: specialized characterization tools for logic circuits

and general circuit analyzers. The former focus on creating parameter sets useful in digital

simulation and synthesis. They work on libraries of gates with given models. Variations of cir-

cuit or device parameters are not considered by these tools but have to be provided by the users

in the form of special models. General analysis tools on the other hand focus on the flexible

manipulation of circuit parameters. Their primary building blocks are netlists or schemat-

ics. These tools do not carry out batches of different analyses with different testbenches to

5.6. Chapter Summary 119

generate.

Individual tools manage design databases into which all generated data can be included.

Yet, since the tools do not completely cover the analysis of OFET-based circuits and transis-

tors, e.g. modeling data are not included in the database.

From the user’s point of view, a combination of the cell characterization scheme (auto-

matic testbench generation for different combinations of models and circuits) with the flex-

ibility of general circuit analyzers (parameter variation or performance optimization) would

considerably improve efficiency of the tools. This would also reduce the work in planning and

maintaining the computer experiments because the testbenches are automatically generated by

the computer.

For the human analysts who employ circuit characterization, implementation of the fol-

lowing features by characterization tools is desirable:

terization tool. This allows the users to select benchmark circuits from different circuit

technologies (e.g. logic gates with load transistors in current-source configuration, etc.)

without the need to compile these libraries themselves. The libraries should also be

reusable in later analyses.

2 Reusable Analysis Procedures – The procedures for deriving the electrical performance

of circuits need to be reusable with different sets of models, model parameters, and cir-

cuits to use. Even the operating conditions like supply voltage or ambient temperature

need to be adjustable.

tracking of unexpected analysis results, the analysis procedures need to be documented.

easy to compile. In the analysis of OFET-based logic circuits, standard procedures for

deriving meaningful performance figures still need to be established. Therefore, the

analysis tools must be flexible enough to allow the users to reconfigure the analysis

procedures.

In this chapter, procedures for characterizing OFET-based logic circuits were discussed. The

following items summarize the discussion results:

2 Circuit analysis with emphasis on organic electronics is still in the early stages. Only

few publications analyze the impact of OFET parameters on circuit performance.

120 Chapter 5. Analysis of OFET-Based Logic Circuits

also be used for analyzing the performance of OFET-based logic circuits. These proce-

dures include e.g. static noise margin determination, delay measurement, etc. However,

the methods have to be applied with care because they often predict false results when

dealing with OFET-based circuits. For example, the unity gain method of deriving noise

margins occasionally predicts negative noise margins for functional circuits. Besides,

deriving delay times using step pulses does not reflect the clock generation schemes in

organic logic circuits (where ring oscillators provide clock signals).

2 Existing tools for circuit characterization are not adapted to the special needs of OFET

technologies. Integration of transistor modeling is missing, or basic analyses like the

calculation of maximum-square noise margin are not included. Moreover, the tools are

specifically designed for skilled users of simulators like SPICE and difficult to work

with for the occasional and non-expert user. Often, flexible combinations of different

analysis steps into more complex analyses is not possible or requires special program-

ming knowledge.

Chapter 6 will detail an analysis concept in which OFET-based logic circuits can be an-

alyzed. The concept provides a flexible interface which allows non-expert users to compile

powerful analysis scripts in a graphical way. OFET modeling and data management are also

included.

121

Chapter 6

Analysis Concept

This chapter presents an analysis concept that automates modeling of organic transistors and

characterization of OFET-based logic circuits. The basic idea is to integrate the various soft-

ware tools needed during the analysis into one single platform. The collaboration between

these tools is automated and the required data are managed in a coherent fashion. This ap-

proach allows the device analyst to concentrate on improving the devices and circuits rather

than transferring data between different tools and manipulating result vectors in order to ex-

tract meaningful performance figures. The novelty of the concept is the combination of all

of these tasks in a single environment. Automation of the analysis is reached by a graphical

scripting concept, which allows non-expert users to compose new or alter existing analysis

procedures. With this framework, routine work is delegated to the computer.

The chapter is organized in the following way. First, the typical analysis flow is exam-

ined in order to identify drawbacks of existing solutions. Subsequently, the novel concept

is detailed. Finally, circuit analyses using an experimental implementation of the analysis

framework are demonstrated.

The optimization of OFET devices and circuits based on circuit simulation is an iterative

process. In practical research work, the process typically consists of the following steps (cf.

Fig. 1.1):

2. Netlists are generated. These contain test circuit, devices under test, and the necessary

models. The user has to compile the respective circuits into a netlist and to include the

model descriptions.

122 Chapter 6. Analysis Concept

3. The circuit simulator is executed, which interprets the netlists, simulates the circuits,

and reports calculated results.

4. The analysts (researchers or computer programs) interpret the results and generate data

sheets from the information. They ask questions like the following:

2 Which device and circuit parameters define performance (e.g. robustness against

interfering noise, circuit speed, power consumption, etc.)?

2 Where have the parameters to be pushed to in order to increase the circuit perfor-

mance?

Answering these questions involves variation of the circuit and model parameters so

that different device generations and parameter sets can be taken into account.

Existing software tools can cover the individual aspects of the process. The analysis cycle

is complicated by manually coordinating the steps due to the following reasons:

2 Data have to be transferred between the tools called in the individual operations. Model

sets need to be included into the netlists used in the simulations or circuits have to be

inserted into the testbenches, etc. These processes are time-consuming and error prone.

2 Input data and analysis results have to be preserved in a database in order to document

the analysis process, to record the improvements of a fabrication process, or to support

replay of the analyses. Possibly, many iterations of the analysis are needed so that

preservation of data can quickly get out of hand.

2 The users need to understand numerous tools and data formats. After longer periods of

not working with the analysis tools, this knowledge often has to be reactivated.

The author of this thesis concludes from practical experience that existing tools will fail

to be used in the analysis of OFET-based devices and circuits as long as the following issues

are not resolved:

1. A single software environment is needed. It must be easy to use. The users, who

normally do not work in the domain of circuit simulation, are not interested in learning

to use the individual tools. Instead, they want to focus on getting their results quickly

and in a highly automated way. Therefore, they prefer graphical user interfaces and easy

access to all relevant data and functions.

6.1. Typical Analysis Flow 123

fashion. Contrary to more traditional semiconductor technologies, vendor-supplied

transistor models do currently not exist in organic electronics. For the user of OFETs,

modeling is therefore most often the starting point of the analysis cycle.

3. The environment must provide automatic generation of test circuits. These test circuits

include e.g. setups for measuring performance figures like noise margin or circuit speed.

4. The environment must provide preconfigured analysis procedures and libraries of pop-

ular logic gates. For the users, it is important to have template setups and gates which

they can reuse and adapt to their special requirements. Otherwise, the users would have

to create the necessary circuits and analysis procedures manually.

5. In the generation of test circuits, transistor models must be easy to replace. There exist

many variations of OFETs (alternate semiconductor / dielectric / electrode materials,

top-gate or bottom-gate topology, etc.) and hence many model types. A generic analysis

tool must therefore manage different model types in all of its analyses. Here, model

management is understood to include the ability to conveniently replace models in test

circuits and analysis setups.

6. The analysis procedures must be easy to adapt to new requirements or to include novel

extraction schemes. Users prefer generic analysis procedures which they can manipu-

late and flexibly extend.

varied. A framework must therefore provide mechanisms to dynamically vary model

and device parameters.

i.e. create simulation-ready netlists for the test circuit, execute the target simulators, or

extract the simulation results. This property is highly desirable because many different

simulation tools are available.

Existing tools easily cover individual aspects of the above list. But missing is an inte-

gration framework in which all of these tasks are handled in a coherent fashion. This work

provides the concept for such a framework, which automates the analysis of novel OFET

devices by use of a generic, coherent, and flexible analysis system.

124 Chapter 6. Analysis Concept

The discussion in the previous section showed that an analysis flow constructed from tradi-

tional EDA tools suffers from numerous drawbacks. Therefore, a novel analysis concept has

been developed in this work. The concept describes how OFET-related data are stored and

analyses of device performance are carried out. The novelty lies in the unified and object-

oriented organization of data, analysis scripts, and analysis reports.

The concept consists of an interactive modeling and simulation environment, and defines

a set of central ideas:

2 Data Management: All relevant data items used in the analyses are stored in a hier-

archical data tree similar to a directory structure on a computer disk. Data items can

be measurement data, model sets, circuit descriptions, or analysis scripts. Each data

item in the tree can also have a documentation text and user-defined properties. The

hierarchical data tree serves as the analysis database and stores analysis procedures and

libraries of popular logic gates as well as user-supplied measurement data.

2 Modeling System: The modeling of devices is integrated into the framework. Model

sets can be created and altered within the software environment. A standardized mod-

eling interface allows the users to add novel model extractors. This modeling interface

defines how the modeling tools are configured and used.

2 Analysis Control: Users employ analysis scripts to automate the analysis flow. Each

script consists of a sequence of individual analysis steps which can be defined and edited

using a graphical user interface. Parameters of circuits and models can be altered within

the scripting system. Batch-mode analyses with automatic generation and simulation of

different testbenches are possible. A standardized execution interface allows the users

to include novel analysis steps. The execution interface defines the way how an analysis

step is graphically configured and executed.

2 Simulator encapsulation: Circuit simulators are integrated into the analysis concept by

use of standardized simulator interfaces. The interfaces cover netlist generation, sim-

ulator control, and result propagation. This technique is known as simulator encapsu-

lation [145] and has successfully been used in the optimization of circuits. Simulator

encapsulation is highly desirable as only the simulator interface has to be adapted in

order to link a novel circuit simulator to the analysis framework.

6.2. Novel Analysis Concept 125

Efficient data management provides a sensible and easy-to-use way of managing heteroge-

neous sets of data. Efficiency can be reached by using a unified data-management scheme,

i.e. all relevant data objects are stored within a coherent data repository. The analysis cycle

for OFET-based circuits typically includes objects of different types:

1. measurement data,

4. analysis scripts.

In the concept presented here, data are organized by storing all objects in a single hierar-

chical structure. This structure can be accessed by the user in the form of a hierarchical data

tree. Hierarchical in this context means that objects can contain other objects. Drawbacks of a

hierarchical data tree are that more efficient data management schemes which are utilized by

database management systems (DBMS) are not available, memory consumption is increased,

and searching the whole tree can take a long time. On the other hand, the advantage of the

hierarchical tree is that data can easily be structured, i.e. grouped, according to the desires of

the users. This increases flexibility and ease of use because the users can organize and handle

the data according to their needs.

In order to facilitate use of the hierarchical data tree, it can e.g. be represented in a graph-

ical way similar to the files of a computer disk by the file browsers of popular operating

systems. With a graphical user interface, non-expert users do not need to learn the commands

of a system which works with batch-mode command scripts or an interactive command line.

Moreover, most computer users are accustomed to the concept of a graphical file browser. The

principal idea of the concept is to organize data in a hierarchical tree of different items so to

cover all important data-management aspects of the analysis cycle.

Fig. 6.1 shows an example of a hierarchical data tree. Data types defined by the concept

are:

2 analysis (icon )

An object of this type represents an analysis procedure, which defines the individual

steps in the characterization of circuits and models. In the analysis concept, analysis

procedures are represented by tree-form scripts implementing execution trees. Details

about tree-form scripts and execution trees are provided in Section 6.2.3.

126 Chapter 6. Analysis Concept

2 circuit (icon )

An object of this type represents a circuit useful for testbench generation. The object

holds information on the structure and connectivity of the circuit. The structure defines

which devices are present in the circuit and how they are connected with each other.

Netlists or schematics are possible. The connectivity defines which terminals of a circuit

to the outer world are present in the circuit, their types (input, output, bidirectional, or

supply node), which parameters exist for the circuit (e.g. the dimensions of the critical

devices), and their default values.

6.2. Novel Analysis Concept 127

2 container (icon )

This object type enables the introduction of data hierarchy by acting as a folder into

which other objects can be grouped. It is comparable to a directory in a file system of a

computer.

2 model (icon )

An object of the type “model” is used for representing a transistor model in the analysis

system. The simplest form of a model is a property list in which the individual entries

denote the parameters of the model. The model can be bound to a model extractor,

which is used for deriving the model parameters.

2 wavevar (icon )

“wavevar” objects contain waveform data like measured current curves, x-axis values

in simulations or measurements, etc. This kind of object is generated when a data file is

imported or simulation results are stored in the data tree.

2 wavefile (icon )

A wavefile object is created when a data file containing measurement or simulation

results is imported into the data tree. The wavefile object represents the imported data

file and contains either wavevars or again wavefiles.

objects. Meta data are a form of additional data describing the object [151] they belong to.

In the concept detailed in this chapter, meta data are used for providing classification and

documentation of objects. The following forms of meta data are used:

of creation in a form easily readable by humans.

2 Property lists provide tables with pairs of names and values where additional object-

related data can be stored in a more formal manner than in a documentation text. This

allows computer routines to directly access these tables. Therefore, search queries like

“list all objects with the property level > 1” get possible. The property list can e.g.

contain the creation date of the object, the file from which the object was created, or in

the case of transistors, the width and length of the device, etc.

Using a combination of documentation text and property lists allows a thorough descrip-

tion in a form easily readable by humans and machines. Fig. 6.2 sketches the relationship

between objects and associated data.

128 Chapter 6. Analysis Concept

documentation

object properties

type−specific data

e.g. waveform,

netlist, etc.

Fig. 6.2: Data association for objects: documentation, properties, type-specific data (wave-

forms, netlists, etc.).

In the analysis framework, models are represented by objects of type “model”. These objects

use model extractors for extracting model parameters from measured curves. In this work, a

model extractor is regarded as a software module used for configuring a model object. The

model extractor can be a piece of software entirely contained within the framework core or

an interface to an external program which carries out the actual parameter extraction. The

generator provides a dialog in which the extraction process is set up, carried out, and possibly

repeated later on with different settings.

Model extractors are used for transforming measured device characteristics into parameter

sets for a special model. They are realized in the analysis framework by use of dynamically

loadable modules. Each module provides a standardized function to create a graphical dialog

used for creating or modifying a model set. The details of the mechanisms are specific to the

actual implementation of the analysis framework and will not be discussed here.

Automatic device and circuit analysis is an important aspect of the analysis cycle. The task

is handled by analysis control. In this work, the term analysis control refers to the definition

6.2. Novel Analysis Concept 129

Analysis Steps

The idea in this work is to decompose analysis procedures into smaller steps so to increase the

ability to modify them as opposed to monolithic analyses used e.g. in the cell characterization

tool Autochar (see Section 5.5.1). The individual analysis steps can be as simple as the def-

inition of variables or as complex as the determination of the static noise margin. During its

execution in the course of the analysis, each step takes input parameters and generates output

parameters (see runtime data under the heading Analysis Sequencing on p. 130). The output

parameters can be propagated to successive steps so to create dependent steps. By doing so,

constructs like the determination of rise and fall times get possible where the attainable volt-

age levels for the logic states are derived in one simulation step and propagated to the actual

timing simulation.

Each step is configured using a graphical dialog. An example of such a dialog in an

implementation of the concept is shown in Fig. 6.3, where a step to derive high/low voltage

and other important parameters from a gate’s voltage transfer characteristic is configured.

By subdividing analysis procedures into smaller steps, questions like “How does the

threshold voltage influence the static noise margin and the rise time?” can be answered. This

is carried out by composing an analysis procedure that consists of a sweep of the threshold

voltage. The sweep carries out the extraction of static noise margin and the rise time (two sub-

ordinate steps of the sweep). In this way, circuit characterization can be used as an exploration

tool.

It can be argued that circuit simulators already provide features for this kind of analysis.

Sophisticated SPICE simulators already contain powerful sweep directives and batch-mode

130 Chapter 6. Analysis Concept

simulations. However, users of these tools have to manually write the testbenches and post-

process the results.

By subdividing analysis procedures into smaller steps, more time is needed to configure

the numerous steps. Consequently, providing specialized analysis programs for each kind of

analysis scenario seems to be more convenient. These programs can contain all necessary

configuration items in one dialog and carry out the simulations as predefined by the program

developer. Moreover, utilization of an external simulator can be optimized for maximum

simulation speed because the analysis programs already know in which way the simulator is

used. While this approach is comfortable if only one analysis has to be carried out all the

time, it is not very flexible. If a user wants to change the analysis flow then reprogramming

might be necessary or the original program design has to foresee all sensible modifications to

the standard flow.

Therefore, subdivision of the analysis procedure into smaller steps has been selected in this

work to implement the analysis flow. Existing analyses can be reused as templates for other

analyses. Moreover, no reprogramming of the underlying computer program is necessary if

smaller modifications are introduced to the flow. Analyses can also be cascaded into more

powerful extraction schemes.

Analysis Sequencing

Control of the analysis flow takes place by defining a sequence of analysis steps to be executed.

The sequence is comparable to a computer script carrying out the individual steps and is stored

in the data tree in the form of an object called “analysis”. In this way, analyses can be treated

like normal data, i.e. can get documentation text or property lists and are stored together with

the data they are used for.

Individual steps of an analysis sequence can propagate results to successive steps by use

of runtime data. Runtime data is a form of dynamic data which only exists during execution

of the analysis procedure. The individual types of runtime data are:

2 Dynamic variables are used for propagating results between analysis steps or for varying

parameters.

2 Dynamic models are dynamic copies of models defined in the data tree. Their purpose

is to allow temporary variations of model parameters in analyses. If e.g. the threshold

voltage of a model shall be varied in an analysis, a dynamic copy of the model in the

data tree is generated and the parameter “threshold voltage” of this dynamic model is

changed in the variation.

2 Dynamic circuits operate similarly to dynamic models. They are temporary copies of

6.2. Novel Analysis Concept 131

circuits defined in the data tree. Their introduction allows varying parameters of a circuit

without affecting the original circuit definition.

2 Analysis results are the data vectors displayed at the end of the analysis. They are

generated and populated during runtime of the analysis.

The analysis sequences are formulated by tree-form scripts which define the actual flow. “tree-

form” means that the steps in the sequence are organized as hierarchical trees where the in-

dividual items are described in textual form. Tree-form analysis scripts will also be denoted

as execution trees in the following. The term “script” refers to the fact that the sequences are

interpreted step by step each time the analysis process is started. The user creates the flow by

instantiating steps in the execution tree. Fig. 6.4 shows a schematic example of an execution

tree.

The individual steps are executed in the order they appear in the execution tree. Subtrees

are executed before the step following their parent is processed. In Fig. 6.4, steps 3.1 and 3.2

are executed before step 4 is done. Step 3 could be a variable sweep from one value to another

or an optimization loop, etc.

analysis

step 1

step 2

step 3

step 3.1

step 3.2

step 4

Fig. 6.4: Schematic example of a simple execution tree for an analysis procedure.

Owing to its graphical user interface, tree-form scripting enables non-expert users to compose

their own procedures without the need to get acquainted with a new scripting language. The

tree-like form is an intermediate form between a true programming language using text scripts

and a graphical programming language oriented toward data-flow modeling.

A programming language using only textual scripts provides the most powerful description

as the procedures and functions can flexibly be combined. Nevertheless, maintenance and

further development of text scripts requires programming skill and adherence to certain coding

132 Chapter 6. Analysis Concept

styles, i.e. consistent use of names for functions and variables, intense use of comments, etc.

Textual scripting languages include Perl, Tcl, Python, etc.

Data-flow languages describe programs by a graphical flow chart. The chart consists of

functional elements in the form of icons or labeled blocks and connections between them.

The program developer defines the required function by drawing the elements and connections

between them. The connections determine the data flow. Examples of data-flow languages are

LabVIEW from National Instruments [152], Simulink from The Mathworks [153], or Caslon

Flow from Gradual Software [154]. With data-flow languages, non-expert users can develop

programs by drawing flow charts. Moreover, the program already documents the flow in an

intuitive way and visualizes the propagation of data. On the other hand, composing constructs

like switch operations between different options can be difficult to draw. In addition to that,

reading complex flow charts can also be troublesome.

Consideration of both styles (text-based coding and drawing of flow charts) led to the ap-

plication of an intermediate style, viz. tree-form scripting. The flow elements are described

in textual form but are configured using graphical dialogs. The operation sequence is de-

scribed by an execution tree. With this scripting style, the scripting environment is easier to

implement and to use than a text-based scripting system as non-expert users can configure

and alter programs. For small modifications or rearrangements of steps, tree-form scripting is

the most compact description scheme. Moreover, the analysis concept already uses tree-form

descriptions to hierarchically structure analysis data in the data tree. On the other hand, the

propagation of results from step to step is less intuitive as in data-flow programming. Results

are propagated between steps by use of variables. A step “determine high voltage” would

write its results to the variable “vhigh”. A step “determine delay time” could then refer to this

variable in order to configure the input waveform needed to extract reasonable delay times.

The mechanisms of using variables are hidden in the configuration dialogs of the individual

steps. The variables are more difficult to track when compared to textual programs or data-

flow drawings. For small programs, tracking the propagation of results is not difficult, but for

larger projects, this might confuse users.

The behavior of the individual analysis steps is programmed in the underlying analysis

framework. Basic analysis steps are:

exists as runtime data until the analysis is finished.

model exists only during runtime of the analysis. It can be used for changing parameters

of existing models in the data tree without affecting the original model.

2 Definition of a circuit – defines a dynamic circuit for use in subsequent steps. The circuit

6.2. Novel Analysis Concept 133

exists only during runtime of the analysis. It can be used for temporarily changing

parameters of existing circuits in the data tree.

of the testbench-generating steps. This directive tells the testbench generator which

values to assign to supply-voltage terminals or to unused input pins of the circuit under

characterization.

2 Sweep a variable – creates a variable, assigns the starting value to it and executes all

steps subordinate to the sweep. After all subordinate steps have been carried out, the

next sweep value is assigned to the variable, the subordinate steps are again carried out,

etc.

2 Accumulate a vector – creates a data vector for reporting at the end of the analysis.

More sophisticated analysis steps which also involve execution of external simulators include

for example:

for logic high/low state and critical gain of a logic gate. At runtime, this step constructs

a testbench which contains the gate under characterization as a series of two instances

in a chain. During execution of the step, a simulator is called to analyze the testbench.

The nominal voltage levels and the critical gain are extracted and reported in runtime

variables. Fig. 6.5 sketches the testbench and the expected simulation results for the

VTC determination.

Vout2

output voltage

+ Vin

Vin Vout1 Vout2

−

0 input voltage

Fig. 6.5: Schematic of a testbench and expected simulation results for VTC determination.

The circles in the voltage plot denote the voltages for the logic states low, unstable, and high.

DUT is the device under test, i.e. the gate to be analyzed.

134 Chapter 6. Analysis Concept

2 Analyze ring oscillator – determine the oscillation frequency of a ring oscillator as well

as rise and fall times. A testbench is generated in which the individual gate is mounted

multiple times so to form the ring oscillator. This testbench is used for simulating

the oscillation frequency and extracting timing information of the ring oscillator (see

Fig. 6.6 for a sketch of testbench and expected simulation results).

VRO

VHigh

oscillation voltage

DUT DUT DUT

VRO

VLow

0 time

Fig. 6.6: Testbench and expected simulation results for analysis of ring oscillators. DUT is

the device under test, i.e. the gate to be analyzed.

and analyzed in order to get on and off currents. The off current is regarded as the

current at maximum magnitude of drain-source voltage and minimum magnitude of

gate-source voltage. The on current is regarded as the current at maximum magnitude

of drain-source voltage and maximum magnitude of gate-source voltage.

the noise margin of a gate. Details about the determination of the maximum-square

noise margin are presented in Section 5.3.4.

Analysis steps are realized in the analysis framework by use of dynamically loadable software

modules. Each module provides a standardized function to create an object-oriented repre-

sentation of the analysis step. The representation contains interface functions to load/setup,

graphically edit, execute, and save the analysis step. The details of the mechanism are specific

to the actual implementation of the analysis framework and will not be detailed here.

6.2. Novel Analysis Concept 135

The analysis framework links to circuit simulators by use of simulator encapsulation [145].

This technique refers to the integration of simulators into a design framework in a generic way.

The simulation tool collaborates with the framework through an abstraction layer. This layer

defines a generic interface between the framework and target simulators. When a simulator

shall be integrated, no changes to either the framework core or the simulator are necessary.

Instead, only the interface between them is adapted. The interface provides the following

features:

2 Netlist generation – A generic description of the circuit structure is passed to the in-

terface. The underlying interface code then constructs the appropriate netlist for the

simulator.

2 Result propagation – The relevant information in the output files of the simulation pro-

cess is transferred to the framework core.

Reasons for introducing simulator encapsulation are:

2 Different research teams utilize different simulator tools. The implementation of the

UML-VRH model disclosed in [65] (see Section 3.2.4.3) employs the circuit simulator

Eldo and models devices with Verilog-A, the analog subset of Verilog-AMS. Model-

ing in this work was done with the open-source circuit simulator tclspice [155]. This

simulator resorts to the SPICE extension XSPICE [93] and model descriptions com-

piled from C code. In order to be a generic tool, the framework has to disregard the

peculiarities of the individual simulators and has to use a generic interface.

2 Different simulators use different directives to include models. Mentor Graphics’ Eldo

uses the y directive to include external models, tclspice and all other XSPICE deriva-

tives use the a directive, while e.g. Tanner T-Spice resorts to the x (or subcircuit)

directive. These differences have to be dealt with in the generation of netlists.

2 Some simulators like the original Berkeley SPICE / XSPICE suite do not support param-

eterizable subcircuits. These are nonetheless needed to provide variation of logic gates

in the course of analyses. The netlist generators of the encapsulation interface have

to translate these parameterized subcircuits into representations suitable for Berkeley

Spice / XSPICE.

are composed in a way different from SPICE. The netlist generator must also deal with

these modeling languages.

136 Chapter 6. Analysis Concept

2 Each simulator has its proprietary format for simulation files. The respective interface

must translate the data into a format readable by the framework core.

tion with simulators takes place by use of this interface. A dedicated implementation of the

interface is provided for each simulator. Netlists are expressed in an intermediate form by

routines of the framework core and transferred to the simulator interface, which in turn gener-

ates the real netlist fed into the simulator. With this two-step approach, simulators can easily

be replaced by other tools. On the other hand, the process of netlist generation is prolonged

because the description has to be translated into the target format.

Experimental tests with a prototype implementation of the framework showed that this

translation can affect the time needed to carry out the analysis. This behavior can prolong the

analysis if small circuits are simulated numerous times with tiny variations. A scenario of this

kind is the numerical optimization of circuits. However, the translation process can be sped

up by appropriate programming techniques. Therefore, performance issues are not a major

concern. Moreover, users will not accept the framework if it works with only one particular

simulation tool. Therefore, the advantages of direct netlist generation were sacrificed to a

more flexible simulator interface.

The purpose of the following sections is to demonstrate the application of the analysis frame-

work in the exploration of OFET-based logic circuits. Basic logic gates will be evaluated

in the examples using an experimental implementation of the methodology named DCI (De-

sign and Circuit Investigator). The simulations are based on the model parameters derived

in Section 4.3.6. The extraction of performance figures (operational speed, attainable volt-

age values for logic levels, and noise margin) of inverters, NOR gates, and ring oscillators

in current-source configuration is demonstrated. The following definitions for voltage levels

representing logic states will be used:

2 high – The stable voltage level closer to the supply voltage (VDD ).

A popular circuit technology implementing logic gates is the current-source configuration

(cf. Fig. 5.1). Currently, it is the method of choice in order to implement OFET-based logic

circuits. The load element of logic gates in current-source configuration is a transistor with

6.3. Analysis Examples 137

both gate and source connected to the output. The ratio between the load transistor ML and

the driving transistor MD as well as the supply voltage can be varied in order to get optimal

gate performance in terms of circuit speed and robustness.

Analysis Objective

The influence of the geometry ratio between load and driving transistor on the robustness (i.e.

noise margin) and speed of logic gates in current-source configuration shall be investigated.

Circuit speed will be measured by the oscillation frequency of a ring oscillator and the rise and

fall times of the output of one of its inverters. This approach requires more computation than

traditional timing extraction schemes like simulating the response to a step pulse but results

in more realistic waveform shapes.

The following settings shall be used in the analyses:

2 both load and driving transistor are p-type conducting and work with the same parameter

set,

2 channel width of load transistor WL = r × WD , where r is the ratio between the width

of the load transistor and the driving transistor,

Analysis Scripting

The session to analyze inverters in DCI is depicted in Fig. 6.7. The left-hand side of the image

shows the session database. The right-hand side depicts an analysis script for the determina-

tion of robustness and circuit speed for inverters with different width ratios. The database

contains measured devices (in the folder Devices, not expanded in the screenshot), logic gates

in current-source and other configurations (folder Circuits, sub-folder for gates in current-

source configuration expanded), and numerous DCI analysis scripts in the folder Analyses.

The analysis scripts in the example all have names starting with “Analyze VTC for CS-Load

with ...” and are all variations of the same analysis with different models to use in the sim-

ulations. The model configurations used in the analyses will be explained under the heading

“Impact of Modeling” in the following. The depicted analysis consists of sweeping the ratio

between the load and driving transistor and calculating the following performance figures:

138 Chapter 6. Analysis Concept

2 Nominal voltage levels for logic high and logic low using a pair of identical inverters.

High and low correspond to the stable intersections between the output of the second

inverter and the input voltage.

2 Maximum negative and critical gain of the voltage-transfer curve. The critical gain is

measured at the intersection between the input voltage and output voltage of an inverter.

2 20% / 80% rise and fall times of an individual stage within the ring oscillator. For

calculation of the 20% / 80% thresholds, the voltage swing between the nominal high

and low voltages is used. These voltages were derived above.

Fig. 6.7: DCI session to analyze the performance of inverters in current-source configuration.

6.3. Analysis Examples 139

Impact of Modeling

In order to test the influence of inaccuracies of modeling, four combinations of models are

investigated in the analysis:

1. one single table model for driving and load transistor (called combination with table

model, table-based model, or simply otab in the following),

2. one single Linvar model for driving and load transistor (called all-Linvar combination

in the following),

3. the Linvar model for the driving transistor and a Level-1 model exactly mapping the

drain-current curve for zero gate-source voltage (called Linvar/Level-1 combination in

the following),

4. the Level-1 model for the drain-current curve at zero bias and a Level-1 model approx-

imating the output characteristics in the range of zero to -20 V of gate voltage (called

Level-1/Level-1 combination in the following).

The table model was derived by tabulating the original extraction values for KP , VT , and λ

in the Linvar extraction in Section 4.3.6 and using a linear interpolation for the VGS -dependent

values. Model data are listed in Table 6.1.

VGS [V ] KP [A/V2 ] VT [V] λ [V−1 ]

0 9.9393e-13 8.0 0.0341730670859

-4 1.3613e-11 1.8 0.0125761040059

-8 2.5627e-11 0.5 0.00735829204921

-12 3.4968e-11 -0.2 0.00542531729999

-16 4.4147e-11 -1.0 0.00484211159415

-20 5.0833e-11 -1.6 0.00453755973153

The parameter set for the Linvar model is KP0 = 8 pA/V2 , fk = -2 pA/V3 , VT 0 = 2.4 V,

fv = 0.2, λ0 = 50 · 10−3 V−1 , fl = 0 V−2 , Rpar ′

= 10 TΩm. The Level-1 parameters for

the load transistor are KP = 0.994 pA/V2 , VT = 8 V, λ = 34.2 · 10−3 V−1 . These values

correspond to the line for zero VGS in Table 6.1. Level-1 parameters for the driving transistor

are KP = 51.6 pA/V2 , VT = -2.4 V, and λ = 8.3 · 10−3 V−1 . They were derived using least-

squares-fitting. All models used constant gate-drain and gate-source capacitors equivalent to

1

2

· Cspec · W · L with Cspec = 0.1 µF/cm2 . It is acknowledged that this kind of capacitance

modeling only coarsely describes the capacitive behavior of real devices. More thorough

modeling will also take into account the non-linear nature of device capacitances and the

contribution of layout-related parasitic capacitances.

140 Chapter 6. Analysis Concept

Analysis Results

The set of curves resulting from the analysis is depicted in Fig. 6.8, which also shows the VTC

plot for a width ratio of 8. With the exception of the Level-1/Level-1 combination, the logic

levels for the different model combinations roughly correspond. Owing to the fact that the

least-squares fit for the Level-1 parameters of the driving transistor led to a negative threshold

voltage VT = -2.4 V, the Level-1/Level-1 setup realizes an enhancement/depletion gate leading

to high levels in the range of the supply voltage (≈ −20 V). The critical gains derived by the

all-Linvar combination and Linvar/Level-1 combination also show agreement. The circuit

combination using the table-based model deviates from the other two combinations for ratios

below 6. For the Level-1/Level-1 combination, there is a surge in critical gain due to the

steeper transition between high and low (see Fig. 6.8f). Moreover, the critical-gain point is

situated within the region of steep transition so that the gain is considerably increased.

For the maximum-square noise margin (Fig. 6.8e), the Level-1/Level-1 combination leads

to a considerably larger noise margin than the other combinations. Here, the VTC curve

is shifted to more negative values. The table-based simulation also deviates from the other

two combinations by predicting zero noise margin for ratios of 4 and below. This can be

understood by inspecting the VTC curves in Fig. 6.8f, where the table-model VTC deviates

from the other VTCs in the range close to zero input voltage. There, the high level of the table-

model VTC does not start to saturate and shows some irregularities at its fix-point (intersection

with the dotted line where the critical gain is measured, see Section 5.3.5).

Fig. 6.8a+b show the resulting oscillation frequencies and rise/fall times for the transient

simulations of the ring oscillators. Rise and fall times were measured between the 20% and

80% points of the voltage swing from low to high voltage.

where n is the number of inverters in the ring oscillator and fRO is the oscillation frequency.

Considerable deviations between the different modeling combinations can be seen. More-

over, the table-based simulation only yields oscillation at width ratios of 6 and higher. This

corresponds with the observation that there is no noise margin available for the table-based

combination for ratios below 6. The differences in oscillation frequency might exist because

the Linvar model predicts currents which are up to 20% below the measured values for small

|VGS | values. Therefore, this combination yields lowest speed because the load transistor sinks

less current. For the Level-1/Level-1 combination on the other hand, drain currents of the load

transistor are higher so that higher oscillation frequencies can be expected.

6.3. Analysis Examples 141

a) b)

16.0 30.0m

14.0

25.0m

12.0

frequency [Hz] −−>

20.0m

10.0

8.0 15.0m rise

6.0

10.0m

4.0 otab

all linvar

linvar+lev1 5.0m fall

2.0 lev1+lev1

0.0 0.0m

2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10

c) ratio of width load/driving trans. −−> d) ratio of width load/driving trans. −−>

0.0 0.0

−2.0 −2.0

high/low voltage [V] −−>

−4.0

critical gain [V/V] −−>

−4.0

−6.0

−6.0

−8.0

−8.0

−10.0

−10.0

−12.0

−12.0

−14.0

−16.0 −14.0

−18.0 −16.0

−20.0 −18.0

2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10

e) ratio of width load/driving trans. −−> f) ratio of width load/driving trans. −−>

4.5 0.0

max.−square noise margin [V] −−>

4.0 −2.0

−4.0

output voltage [V] −−>

3.5

3.0 −6.0

2.5 −8.0

−10.0

2.0

−12.0

1.5

−14.0

1.0

−16.0

0.5 −18.0 ratio width load/drive = 4

0.0 −20.0

2 3 4 5 6 7 8 9 10 −20 −15 −10 −5 0

ratio of width load/driving trans. −−> input voltage [V] −−>

Fig. 6.8: Simulated data for an inverter in current-source configuration: a) ring oscillator

frequency, b) rise/fall times at a particular stage in the ring oscillator, c) nominal high and low

voltages, d) critical gain gcrit , e) maximum-square noise margins, and f) VTC plot for width

ratio of 4. Each plot contains curves for different combinations of simulation models.

142 Chapter 6. Analysis Concept

Analysis Conclusions

By observing the plots in Fig. 6.8, a width ratio of 6 can be identified as an acceptable com-

promise between circuit speed and robustness on one hand and area usage of the logic gates

on the other hand. A further increase in ratio beyond 6 will also increase the oscillation fre-

quency. However, frequency and nominal voltage levels only moderately improve.

A comparison of Fig. 6.8a and Fig. 6.8d shows that the presence of an oscillation (i.e. a robust

or regenerating operation of inverters in a chain) correlates with |gcrit | > 1. Therefore, it is

interesting to inspect gcrit in order to derive the robustness of a logic gate. In literature on

noise margin calculations, a high |gmax | is also used as a criterion which reflects robustness

of a circuit (e.g. [125]). The relationship between critical gain, maximum negative gain, and

noise margin can be compared using the plots in Fig. 6.9.

a) b)

12.0 15.0

|gmax |

gain [] & noise margin [V]

10.0 10.0

noise margin [V] −−>

8.0 5.0

6.0 0.0

max−square noise margin max−square

0.0 −15.0

2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10

WL /WD WL /WD

Fig. 6.9: Simulation data for noise margin analysis: a) magnitude of critical and most-negative

gain together with maximum-square noise margin, b) unity-gain and maximum-square noise

margin. Simulations were done with Linvar/Level-1 combination for driving and load transis-

tor.

The magnitude of the critical gain displays a behavior similar to the maximum-square

noise margin while the magnitude of the maximum negative gain vs. the ratio develops differ-

ently. Hence, designs optimizing gcrit lead to different results than designs optimizing gmax .

The unity-gain noise margin also considerably differs from the maximum-square data and

even yields negative values (for the low level). Again, designs optimizing the unity-gain noise

margin and the maximum-square noise margin will yield different results. The unity-gain

6.3. Analysis Examples 143

method easily leads to large noise margins for the logic high level while negative (i.e. nonex-

istent) noise margins for the logic low level might occur, even for circuits with a critical gain

|gcrit | > 1 and existing maximum-square noise margin. The surge in unity-gain noise margin

for a ratio of four is due to the fact that for smaller ratios, only one unity-gain point exists.

Therefore, the noise margins get very small.

When inspecting gcrit and gmax , these two values strongly depend on the granularity of the

VTC curves from which they are calculated. The two gain values are numerically calculated,

i.e. by finite differences, and therefore strongly depend on the step size between neighboring

values of the VTC. This leads to the requirement that step sizes should be as small as possible,

e.g. 0.1 V.

Impact of DCI

The analyses presented so far can also be carried out using existing circuit simulators alone.

However, without an integration environment like DCI, the users are required to create and

update the testbenches by hand and to configure batch scripts controlling the simulation pro-

cess. Some simulation environments feature the use of scripting systems, e.g. the original

SPICE3 distribution from the University of Berkeley, the simulation environment Synopsys

SaberDesigner, or the simulation tool SimPilot from Mentor Graphics. However, these tools

do generally not provide full transparency between different simulation engines. Moreover,

these systems do not automatically generate the required models or testbenches. On the other

hand, cell characterization packages generate testbenches and process simulation results, but

they generally do not explore more basic performance figures like static noise margin or the

critical gain, or provide heterogeneous analysis plans.

DCI interacts with different simulators, creates analysis testbenches as needed and com-

bines transistor modeling, model and circuit management, analysis configuration, and extrac-

tion of performance figures within a single and interactive user interface. Device and circuit

information, analysis instructions, and analysis results are treated as a unit. Moreover, the

users can easily manipulate the complete set of data and scripts.

Inverters alone will not make up useful circuits. More complex gates like NORs are required.

The schematic of a NOR gate with the load transistor in current-source configuration is de-

picted in Fig. 6.10. The gate consists of two driving transistors MD1 and MD2 in parallel and

a load transistor ML in current-source configuration. The driving transistors are controlled by

the two inputs Vin1 and Vin2 , respectively. For NOR3 gates in current-source configuration, a

third driving transistor MD3 would be added in parallel to MD1 and MD2 .

144 Chapter 6. Analysis Concept

VDD

ML

Vin1 Vin2

Fig. 6.10: Schematic of a two-input NOR with load transistor in current-source configuration.

Analysis Objective

configuration shall be carried out. The driving transistors shall have identical widths as defined

by WD1 = WD2 = WD . The width of the load transistor ML shall be varied with respect to

WD so that WL = r · WD . In the course of the analysis, the VTC and transient behavior is

inspected by the methods already presented in Section 6.3.1. One input shall be used for the

characterization while the nominal low voltage Vlow shall excite the remaining input(s). Vlow

shall also be varied.

Analysis Scripting

The analysis session to analyze NORs in DCI is similar to the inverter-related session depicted

in Fig. 6.7. Differences are the use of NOR2 or NOR3 gates as circuits under test and terminal

“in1” as characterization input. The other inputs “in2” and “in3” (if available) are set to a value

Vlow using the “define connectivity” instruction. Vlow is added as a second parameter to sweep,

i.e. in an outer loop.

Analysis Results

The results of the analysis are presented in Fig. 6.11. For the calculations, the transistor model

from Section 4.3.6 was used. The data demonstrates that the anticipated low levels strongly

influence the choice of WL . The analysis can be used for finding the maximum tolerable low

level |VLow | for a particular design. This voltage depends on device parameters but also on

the fan-in, i.e. the number of inputs of a gate. This is demonstrated in Fig. 6.12, where a two-

input NOR gate and a three-input NOR gate with identical transistor dimensions are compared

6.3. Analysis Examples 145

a) b)

16.0 18.0m

−4 V

14.0 16.0m

Vlow = -2 V −3 V

12.0 14.0m

frequency [Hz] −−>

12.0m

10.0 Vlow = -2 V −3 V −4 V 10.0m rise

8.0

8.0m

6.0

6.0m

−3 V −4 V

4.0 4.0m −2 V

INV

NOR2

2.0 2.0m

fall

0.0 0.0m

2 3 4 5 6 7 8 9 10 2 4 6 8 10 12 14

c) ratio of width load/driving trans. −−> d) ratio of width load/driving trans. −−>

0.0 0.0

−2.0

−0.5

high/low voltage [V] −−>

−4.0

critical gain [V/V] −−>

−6.0 −1.0

−4 V

−8.0 −1.5 −3 V

Vlow = -2 V

−10.0

−12.0 −2.0

−4 V

−14.0 Vlow = -2 V −3 V

−2.5

−16.0

−3.0

−18.0

−20.0 −3.5

2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10

ratio of width load/driving trans. −−> ratio of width load/driving trans. −−>

Fig. 6.11: Simulated data for inverters and NOR2 gates with load transistor in current-source

configuration: a) ring oscillator frequency, b) rise/fall times, c) nominal high and low voltages,

d) critical gain. The second input of the NOR gate was biased with Vlow = -2/-3/-4 V.

Analysis Conclusions

The simulation results in Fig. 6.11 and Fig. 6.12 show that the fan-in (FI) strongly influences

the attainable circuit speed and high levels. Increasing the width ratio of NOR gates does

not compensate for the detrimental effect of FI in comparison to the simple inverter. For the

transistor type used in this section, NOR2 gates should have a ratio of at least 8 and NOR3

gates of at least 10.

146 Chapter 6. Analysis Concept

a) b)

16.0 20.0m

14.0 18.0m

16.0m

12.0

frequency [Hz] −−>

rise

14.0m

10.0 12.0m

8.0 10.0m

6.0 8.0m

6.0m

4.0

INV 4.0m

2.0 NOR2 2.0m

NOR3 fall

0.0 0.0m

2 4 6 8 10 12 14 2 4 6 8 10 12 14

ratio of width load/driving trans. −−> ratio of width load/driving trans. −−>

c) d)

0.0 0.0

−2.0 −0.5

high/low voltage [V] −−>

−4.0

−1.0

−6.0

−8.0 −1.5

−10.0 −2.0

−12.0 −2.5

−14.0

−3.0

−16.0

−18.0 −3.5

−20.0 −4.0

2 4 6 8 10 12 14 2 4 6 8 10 12 14

ratio of width load/driving trans. −−> ratio of width load/driving trans. −−>

Fig. 6.12: Comparison of simulation results for inverters and NOR2/NOR3 gates with

VDD = -20 V: a) ring oscillator frequency, b) rise/fall times, c) nominal high and low volt-

ages, d) critical gain. Unused inputs were biased with Vlow = -2 V.

In the examples presented so far in Section 6.3, the analysis does not depend on the model

type. The analysis framework can also be used for predicting directions for material opti-

mization. This is carried out by deliberately varying critical model parameters and inspect-

ing resulting circuit performance. In this section, variation results obtained from DCI sim-

ulations are presented. The analysis is carried out using the simplified Linvar model from

Section 4.3.6.

6.3. Analysis Examples 147

Analysis Objective

The proper function of a NOR gate at a given supply voltage VDD in the presence of off-current

variations shall be verified. This is done using ring oscillator frequencies and the critical gain.

The same ring oscillator configuration as in Section 6.3.1 is used. For demonstration purposes,

the analysis is restricted to the treatment of off-current variations. In principle, analysis of the

impact of on-current variation, threshold-voltage variation, etc. can be done with similar

approaches.

Analysis Scripting

The analysis consists of varying the “off current” Iof f , i.e. the drain current at maximum

magnitude of drain-source voltage and zero gate-source voltage, while keeping constant the

“on current” Ion , i.e. the drain current at maximum magnitude of drain-source and gate-source

voltage. In the Linvar model, this can be accomplished by varying KP 0 and calculating fK in

such a way that KP max remains unchanged. The corresponding formula for fk is

KP max − KP 0

fk = , (6.1)

VGS,max

where KP max is the conductance parameter at the maximum |VGS,max |, i.e. the gate-source

voltage for the “on current”.

Fig. 6.13 shows the DCI script for the analysis. The calculations corresponding to (6.1)

are outlined by boxes. The runtime variables kp0 and fk are used as mapping parameters for

the models describing the load and driving transistors, respectively.

Analysis Results

Fig. 6.14 shows the simulation results. The data suggests that Iof f strongly influences critical

gain, circuit speed, and attainable voltage level for logic high. A weaker influence on the low

level is observed because the VTC range for the logic low voltage is relatively large (see e.g.

Fig. 6.8f) so that a degenerate high level is not so crucial for the low level. For a ratio of 6, the

ring oscillator ceases to function with a zero-based process conductance of 12 pA/V2 , where

the on/ratio dropped to a value below 200.

148 Chapter 6. Analysis Concept

Fig. 6.13: DCI script to analyze the influence of off-current variation on circuit performance.

6.4. Chapter Summary 149

a) b)

−0.5 14.0

−1.0 12.0

ratio = 8

critical gain [V/V] −−>

ratio = 6

10.0

−1.5 ratio = 6

8.0

−2.0

ratio = 8 6.0

−2.5

4.0

−3.0 2.0

−3.5 0.0

0p 2p 4p 6p 8p 10p 12p 14p 16p 0p 2p 4p 6p 8p 10p 12p 14p 16p

zero−based process conductance [A/V²] −−> zero−based process conductance [A/V²] −−>

c) d)

600.0 0

nominal high/low voltage [V] −−>

550.0 −2

500.0 −4

on/off ratio −−>

450.0 −6

400.0 −8

350.0 −10

ratio = 6

300.0 −12

250.0 −14

200.0 −16 ratio = 8

150.0 −18

0p 2p 4p 6p 8p 10p 12p 14p 16p 0p 2p 4p 6p 8p 10p 12p 14p 16p

zero−based process conductance [A/V²] −−> zero−based process conductance [A/V²] −−>

Fig. 6.14: Simulations of two-input NORs with varying zero-based process conductance KP 0

for two ratios (6 and 8): a) critical gain, b) oscillation frequency, c) on/off ratio of the driving

transistor, and d) nominal high and low voltages.

In this chapter, a novel analysis concept was discussed. The basic idea of the concept is to

combine data management, modeling, and circuit investigation in a single analysis framework.

Data is organized in a hierarchical data tree where all items relevant in the analysis (model

data, model sets, circuits, analysis scripts, results) can be stored. Analysis procedures are

described by use of tree-form scripting in which the flow of commands is expressed using

execution trees. Individual actions, i.e. analysis steps, are configured using graphical dialogs.

150 Chapter 6. Analysis Concept

Simulation tools are integrated into the framework via an abstraction layer which provides a

standardized interface.

The analysis framework resolves the following issues with existing tools (cf. p. 122):

1. A single software environment is provided. It is easy to use and allows the users to focus

on carrying out their analysis in a highly automated way. The environment features a

graphical user interface and easy access to all relevant data of the analysis.

which are fully integrated into the framework.

3. The environment provides automatic netlist generation for various performance analy-

ses (noise margin detection, circuit speed, etc.).

4. Preconfigured analysis procedures and libraries of logic gates can be stored in the

database of the analysis environment and reused in later analyses.

5. The environment tracks all model references in the circuits used by the netlist generator.

Arbitrary models can be mapped to the references used in these circuits.

6. Analysis procedures are expressed as execution trees where all individual steps can be

configured using graphical dialogs. Different analysis steps exist to define variables,

perform sweeps, map models and circuits, or to carry out sophisticated simulations.

This setup allows flexible manipulation and extension of existing analysis schemes.

7. During the analyses, model and circuit parameters can be flexibly varied so to provide

means of exploring the parameter-dependent behavior of devices and circuits. New

schemes can be defined by composing the respective execution trees.

tools via an abstraction interface. If the simulation tool is replaced, only an implemen-

tation of the interface to the replacing simulator is required.

151

Chapter 7

This chapter summarizes the work presented in this thesis and discusses possible extensions

to the provided methods, analyses, and tools.

7.1 Summary

Organic field-effect transistors (OFETs) are currently in the early stages of process develop-

ment and device optimization. In the course of optimization, circuit simulation of reasonable

application circuits is a key point in fine-tuning the device parameters of OFET technologies

as it provides insight into the performance potential of given or hypothetical OFET genera-

tions. However, many issues have to be overcome before circuit analysis by circuit simulation

can unfold its full potential in the field of OFET-based circuits. Owing to the early stages in

the field, adequate transistor models, modeling software, and analysis tools (proper perfor-

mance figures, simulation software) dedicated to organic electronics are missing. Therefore, a

computer-aided methodology to analyze the performance of OFETs in logic circuits has been

developed in this work. The basic idea of the concept is to provide an integrated environment

for data management, transistor modeling, and the automatic analysis of benchmark circuits.

In order to implement the methodology, issues in OFET modeling and circuit characterization

were analyzed in this work.

In the part dealing with OFET modeling, a model quality chart was defined so to allow

formal comparison of individual modeling approaches. By using the model quality chart,

model accuracy, proper capacitance modeling, compactness of a model, parameter extraction,

and modeling of stress effects are rated. Existing modeling approaches for OFET devices,

extraction procedures for the respective parameters, and extraction tools were discussed. A

review of the tools showed that they are either very general or specialize on certain models.

The tools cannot visualize which model type can best fit a given transistor. Therefore, users

152 Chapter 7. Summary and Further Work

have to carry out parameter extractions for different model types and have to compare the

resulting model accuracies in order to find the most-appropriate model. In order to facilitate

modeling, a novel extraction scheme called VSat method was therefore developed in this work.

The approach is used for extracting the basic parameters threshold voltage (VT ), process con-

ductance (KP ), and channel length modulation (λ) for individual ID vs. VDS curves. The

VGS -dependence of these parameters is used for identifying appropriate model types because

each type has characteristic VGS dependences for the basic model parameters. Two models

were presented which directly use the basic parameters extracted with the VSat method: a

table model and an analytic model called Linvar model.

In the part dealing with the circuit characterization, a novel approach was introduced

which defines the robustness of logic gates by inspecting the gain of the fix point in the

voltage-transfer characteristic. An existing method of qualitatively defining the compatibility

of valid logic level ranges was extended to yield noise margins.

Traditional methods of defining static and dynamic performance figures of basic logic

circuits were analyzed. Existing tools for circuit characterization were reviewed. Like in

the case of modeling, these tools are either very general or specialize on a limited set of

applications. Many tools lack automatic testbench generation, inclusion of documentation, or

flexible manipulation of the analysis flow and data. Seamless integration of device modeling

is generally not provided.

In view of the drawbacks of existing modeling and characterization tools, a novel analysis

methodology was developed in this work. The concepts of the methodology are:

2 Transistor modeling and circuit characterization are integrated into a single environ-

ment.

2 The users have direct access to all items needed in the modeling and characterization

steps (models, circuits, waveforms, analysis procedures).

2 The items are organized in a data tree and can be arranged hierarchically according to

the needs of the users.

2 Documentation and a property set can be assigned to each item in the data tree. This

facilitates reuse of existing analyses and backtracking of unexpected results as every

item can be thoroughly described.

2 Automation of the analysis is reached using a graphical scripting concept that allows

non-expert users to compose new or reuse existing analysis procedures.

2 Testbenches to analyze typically used performance figures like circuit speed or robust-

ness, i.e. noise margin, are generated fully automatically. The generation process and

result extraction seamlessly integrate into the graphical scripting concept.

7.2. Further Work 153

Scientific progress could be made in this work in the formal comparison of models and

in the extraction of model parameters by use of the novel VSat method. Novel model types

for OFET devices and a computer-aided methodology for OFET-based modeling and circuit

characterization have been developed.

This section summarizes methodological and practical issues which have not been resolved in

the design of the analysis concept presented in Chapter 6 or its experimental implementation,

DCI.

Modeling

The VSat method could be used for generating a modeling wizard. Such a wizard is a program

which analyzes available transistor data and provides different action routes on the basis of

the analysis results. The wizard will run through a number of steps until a proper model has

been selected and the accompanying parameter sets have been derived. In future work, proper

models could be chosen according to the VGS -dependent shapes of the extracted parameters.

The process could be automated by use of shape-detection algorithms. Alternatively, the basic

parameters could be used as initial values for curve fitting.

Another issue is the separation of contact effects during parameter extraction. There have

been reports on the treatment of contact effects in transistor modeling but the extraction pro-

cedures often require interference by the user. Methods like the Unified Extraction Method

(UEM) [56] could help in the extraction of contact effects. Additionally, UEM is also very

interesting for model extraction in general because it is specifically designed for thin-film

transistors. However, UEM requires a sophisticated user interface and a high degree of user

interaction. Here, efficient implementations and automation schemes for selecting appropriate

current-voltage curves could be explored in further work.

Statistical modeling of OFET-based measurement series is currently not included in the

data organization scheme of the analysis concept. However, statistical analyses are important

for more realistic simulations of device performance in integrated circuits.

Capacitance modeling is currently approximated by constant capacitors in the analyses

presented in this work. The influence of nonlinear capacitances on simulation results for ring

oscillators needs to be investigated. Such nonlinear capacitances are included e.g. in models

for variable range hopping [63, 65].

There have been efforts to analytically explain the subthreshold behavior of OFETs [64] in

the framework of variable range hopping. A proper description of this operation region could

154 Chapter 7. Summary and Further Work

improve the accuracy of simulating NAND gates or transmission gates. However, research on

this topic is still in the early stages.

Circuit Characterization

Automatic circuit sizing is currently not addressed by DCI, the experimental implementation

of the methodology. Therefore, it is up to the user to provide sensible transistor configurations

for their circuits under analysis. Generic circuit sizers could be included in the implementation

of the analysis concept by providing appropriate commands to the graphical scripting system.

The special needs and techniques of statistical circuit analysis have currently been disre-

garded in the design of the analysis concept. In spite of that, statistical variation is important

in order to provide realistic data on the performance potentials of OFET-based circuits. Yet,

there is currently only small activity in the research community regarding statistical methods

in the characterization of OFET-based logic circuits. Approaches like the method of equi-

librium zones (MEQ) could be used in conjunction with statistical methods. The statistical

analyses would establish upper and lower bounds for the VTC curves.

155

Appendix A

List of Symbols

α effective overlap parameter between localized states in Å−1

VRH modeling

α power factor for VGS -dependence of ID in TFT modeling –

and UEM

αsat saturation variation parameter in Psi-TFT modeling –

β device conductance parameter of a transistor A/V2

β ratio between effective grain-boundary size and channel –

length in Psi-TFT modeling

∆E voltage-dependent contribution to extraction function E in V/A

SJ method

ε0 free-space permittivity constant (8.854187818 · 10−12 ) AsV−1 m−1

εr relative permittivity of the insulator –

εs relative permittivity of the semiconductor –

η diode ideality factor –

ηi subthreshold ideality factor in Psi-TFT modeling –

γ power parameter for a-Si TFT mobility –

γ fitting parameter for conductivity in UML modeling –

λ transistor channel-length modulation V−1

λ0 constant channel-length modulation in Linvar modeling V−1

µ carrier mobility cm2 /V·s

µ0 upper mobility limit in Psi-TFT modeling cm2 /V·s

µ1 low-field mobility in Psi-TFT modeling cm2 /V·s

µeff effective mobility cm2 /V·s

156 Appendix A. List of Symbols

µg grain intrinsic mobility in Psi-TFT modeling cm2 /V·s

µgb mobility at grain boundary in Psi-TFT modeling cm2 /V·s

µn mobility of electrons cm2 /V·s

µp mobility of holes cm2 /V·s

µs subthreshold mobility in Psi-TFT modeling cm2 /V·s

σ conductivity S/cm

σ0 prefactor for conductivity in VRH modeling S/cm

τ (VGS ) delay function in Dresden modeling –

τs statistical shift parameter for delay function in Dresden –

modeling

a mobility factor in Hamburg VRH modeling cm2 /V·s

ai fitting parameter for shape function f in Dresden modeling –

b power factor for mobility in Hamburg VRH modeling –

bi fitting parameter for shape function f in Dresden modeling –

Bc critical number of bonds per site in largest cluster of a per- –

colation system

CGD gate-drain capacitance F

CGS gate-source capacitance F

ci fitting parameter for scale function h in Dresden modeling –

Cis insulator capacitance per unit area F/cm2

di fitting parameter for scale function h in Dresden modeling –

E(VGS − VT ) extraction function for contact resistance in SJ method V2 /A

E0 constant contribution to extraction function E in SJ method V2 /A

Eb barrier height at grain boundary in TFT modeling eV

EC energy of lower edge of conduction band eV

EF Fermi energy eV

EV energy of upper edge of valence band eV

f (V ) VTC of gate under consideration in unity gain method V

f (VDS ) shape function in Dresden Modeling –

F1 (x) VTC curve of gate under consideration in method of maxi- V

mum squares

F2 (y) inverse VTC curve of gate under consideration in method V

of maximum squares

fλ factor for VGS -dependent channel-length modulation in Lin- V−2

var modeling

157

fk factor for VGS -dependent process conductance in Linvar modeling A/V3

fT factor for VGS -dependent threshold voltage in Linvar modeling –

G0 length-independent channel resistance of transistor Ω/m

gcrit critical gain at fix point of VTC curve of a logic gate –

gd drain conductance S

gm transconductance S

gmax maximum negative gain of VTC curve of a logic gate –

H(VGS ) extraction function in UEM for TFTs V

h(VGS ) scale function in Dresden modeling –

I current A

I00 current density in cut-off region of UML modeling A/m

Ia above-threshold current in Psi-TFT modeling A

ID drain current A

IDM ax maximum current in VSat extraction A

IDS0 saturation current clear of channel-length modulation in VSat ex- A

traction

IDSat current at transition between linear and saturation region A

Ileak subthreshold leakage current A

IS saturation current of Schottky diode A

Isub sub-threshold current in Psi-TFT modeling A

K conductance parameter in UEM extraction for TFTs S

K fitting parameter for mobility in UML modeling S

K′ fitting parameter for conductivity in UML modeling S

kB Boltzmann constant (1.380662 · 10−23 ) VAs/K

KG geometry factor in Dresden modeling A

KP process conductance parameter of a transistor A/V2

KP0 constant process conductance factor in Linvar modeling A/V2

KS statistical current scale factor in Dresden modeling –

L length of the transistor channel m

Ln length of electron-accumulating region in ambipolar transistors m

Lp length of hole-accumulating region in ambipolar transistors m

m power factor for mobility in UML modeling –

mµ mobility parameter in Psi-TFT modeling –

158 Appendix A. List of Symbols

n number of grain boundaries along channel in Psi-TFT modeling –

NA doping-induced charge density in UML modeling –

NMH noise margin for high level of a logic gate V

NML noise margin for low level of a logic gate V

Nt density of localized states in VRH modeling cm−3

pi fitting parameter for delay function τ in Dresden modeling –

q elementary charge (1.6021892 · 10−19 ) As

QD drain charge of transistor C

QG gate charge of transistor C

qi fitting parameter for delay function τ in Dresden modeling –

QS source charge of transistor C

r step function –

RC contact resistance Ω

RCD compensation resistance for drain-side contact resistance Ω

RCS compensation resistance for source-side contact resistance Ω

RD drain-side contact resistance (synonymous to RDC ) Ω

RDC drain-side contact resistance (synonymous to RD Ω

RM effective channel resistance including contact effects Ω

Rpar bulk resistor in Linvar-type OFETs Ω

Rpar

′

width-independent bulk resistor in Linvar-type OFETs Ω·m

RS source-side contact resistance (synonymous to RSC ) Ω

RSC source-side contact resistance (synonymous to RS ) Ω

S subthreshold slope V/dec

T temperature K

T0 width of exponential distribution in VRH modeling K

tdf high-to-low delay of logic gate s

tdr low-to-high delay of logic gate s

tf fall time of of logic gate s

tis insulator thickness m

159

tP D pair delay of two identical gates s

tr rise time of logic gate s

u, v coordinates of rotated coordinate system in method of maximum V

squares

V voltage V

VAA characteristic voltage for mobility in a-Si TFT modeling V

VB potential barrier between grains in Psi-TFT modeling V

VD drain voltage V

VDD supply voltage V

VDM ax maximum (in magnitude) drain current in VSat method V

VDS drain-source voltage (VD − VS ) V

VDS

′

drain-source voltage clear of contact effects V

VDSat saturation voltage (synonymous to VSat ) V

VG gate voltage V

VGDT VG − VD − VT V

VGS gate-source voltage (VG − VS ) V

VGS

′

gate-source voltage clear of contact effects V

VGST effective gate-source voltage (VG − VS − VT ) V

VGST effective VGST clear of contact effects V

VH stable voltage level for logic high in VTC curve of a logic gate V

160 Appendix A. List of Symbols

VIH,min minimum allowable voltage level for logic high at the input of a V

logic gate

VIL,max maximum allowable voltage level for logic low at the input of a V

logic gate

Vin input voltage of a logic gate V

VL stable voltage level for logic low in VTC curve of a logic gate V

VM metastable voltage level in VTC curve of a logic gate V

VOH,min minimum allowable voltage level for logic high at the output of a V

logic gate

VOL,max maximum allowable voltage level for logic low at the output of a V

logic gate

VON on voltage V

VON statistical quantity to shift switch-on voltage in Dresden modeling V

Vout output voltage of a logic gate V

VS source voltage V

VSat saturation voltage (synonymous to VDSat ) V

VSat

′

saturation voltage clear of contact effects V

VSO switch-on voltage V

VT threshold voltage V

VT∗ effective threshold voltage including contact effects V

VT 0 constant threshold voltage parameter in Linvar modeling V

VT,n threshold voltage of electron-accumulating region of ambipolar V

transistor

VT,p threshold voltage of hole-accumulating region of ambipolar tran- V

sistor

Vth thermal voltage V

Xτ power factor for delay function τ in Dresden modeling –

Xf power factor for shape function f in Dresden modeling –

Xh power factor for scale function h in Dresden modeling –

W width of the transistor channel m

161

Appendix B

List of Acronyms

BC bottom contact

BFL Buffered FET Logic

CMOS complementary metal oxide semiconductor

CSL current-source load

DCI Device and Circuit Investigator

DL diode-load

DUT device under test

E/D logic enhancement-depletion logic

EDA electronic design automation

F8T2 poly(9,9-dioctylfluorene-co-bithiophene); short: polyfluorene

FET field-effect transistor

FI fan-in

FO fan-out

GND ground

IC integrated circuit

IGFET insulated-gate field-effect transistor

KCL Kirchhoff Current Law

MOSFET metal oxide semiconductor field-effect transistor

MQC Model Quality Chart

MTR multiple trapping and release

OFET organic field-effect transistor

OLED organic light-emitting diode

OTFT organic thin-film transistor

P3HT poly(3-hexylthiophene)

PDHTT poly(3,3”-dihexyl-2,2’:5’,2”-terthiophene)

162 Appendix B. List of Acronyms

PPV poly(phenylenevinylene)

Psi TFT polycrystalline silicon TFT

PTAA polytriarylamide

PTV poly(2,5-thienylen vinylene)

RFID radio-frequency identification

RO ring oscillator

RPI Rensselaer Polytechnic Institute

SPICE simulation program with integrated circuit emphasis

TC top contact

TFT thin-film transistor

UEM Unified Extraction Method (→ UMEM)

UMEM Unified Model and parameter Extraction Method (→ UEM)

UML universal mobility law

VRH variable range hopping

VTC voltage transfer characteristic

163

Appendix C

Glossary

quence of operations carried out to study the characteristic behavior of a circuit or de-

vice.

benchmark circuit A circuit useful in the extraction of typical performance figures of de-

vices. In the domain of logic circuits, inverters, ring oscillators, flip-flops, counters, etc.

might be used.

tion) or model parameters of a device (device characterization).

circuit This term refers to a combination of two or more devices which carries out a useful

function, i.e. acts as a logic gate, amplifier, etc.

nation of single and multiple bonds [9].

device One of the basic electrical elements supported by a semiconductor technology (tran-

sistor, resistor, capacitor, etc.). In this work, the term mainly refers to transistors.

flexography printing A printing process where ink is transferred from a raised area. The

printing plate is made of a flexible material.

flip-flop A memory element where the level changes of the inputs define the stored state, i.e.

a edge-triggered memory element [134] as opposed to level-sensitive latches. See also

latch.

164 Appendix C. Glossary

framework A software tool in which analysis projects can be developed and organized. The

framework integrates the various tools needed in the analysis process. The terms anal-

ysis environment, analysis framework, and analysis concept are used synonymously.

gravure printing A printing process where ink is transferred from a recessed surface.

latch A memory element where the levels of the inputs define the stored state, i.e. a level

sensitive memory element [134] as opposed to edge-triggered flip-flops. The simplest

form of a latch is the so-called RS latch which consists of two cross-coupled two-input

NAND or NOR gates, respectively (see Fig. D.2). See also flip-flop.

mobility This quantity (unit cm2 /Vs) describes the mobility of charge carriers. Several types

of mobilities can be defined (see [83]). In this work, the gate-voltage-dependent effec-

tive mobility, derived from experimental current-voltage characteristics of a FET [52],

is used.

model The representation of the electrical behavior of a device useful in circuit simulation.

A model consists of a description of the electrical behavior in the form of equations

(analytical model or compact model) or a combination of devices (macro model) as

well as a set of model parameters.

noise Any deviation from nominal voltages [112]. Sources for noise can e.g. be [113] spu-

rious signals/crosstalk which interfere with information-carrying circuit nodes, or in-

herent fluctuations of device parameters owing to fabrication process or operating point

variations.

off current Current at maximum magnitude of drain-source voltage and minimum magnitude

of gate-source voltage. See also on current.

of gate-source voltage. See also off current.

output characteristics Plot of the drain current vs. drain-source voltage of a transistor.

percolation theory This field studies properties of disordered systems like conductivity by

means of statistical methods [156]. In organic electronics, percolation theory is used to

analyze transport in inhomogeneous organic semiconductors.

application. Performance figures can be switching speed, power consumption, robust-

ness against parameter variation, etc.

165

polymer A compound consisting of organic chains. The length of the chains is not clearly

defined [9].

ring oscillator A chain of inverting gates forming a loop with an odd number of stages. The

output of each gate is connected to the input of its successor. The output of the last gate

is fed back to the input of the first gate. This configuration leads to an oscillation with a

frequency of f ≈ 2ntD where n is the number of stages and tD is the delay per stage.

screen printing A printing process where ink is applied to a surface through a fine mesh

screen. The image is defined by blocking parts of the mesh screen [23].

testbench/test circuit A combination of one or more benchmark circuits together with the

required input signals and output loads. The testbench is used to derive performance

figures of devices or circuits during circuit characterization.

thin film.

transfer characteristic Plot of the drain current vs. gate-source voltage of a transistor.

trap An energy level within the bandgap of a semiconductor due to the presence of impurities

or structural defects [14].

voltage transfer characteristic (VTC) Plot of the output voltage vs. input voltage of a logic

gate.

166 Appendix C. Glossary

167

Appendix D

Circuits

Logic Gates

European North−American

Gate Type Truth Table

(EAN) Symbol (ANSI) Symbol

A Q

Inverter A Q A Q L H

H L

A B Q

A A L L H

NAND B & Q B Q L H H

H L H

H H L

A B Q

A A L L H

NOR B Q B Q L H L

H L L

H H L

A B Q

A A L L H

XNOR B Q B Q L H L

H L L

H H H

Fig. D.1: European/american symbols and truth tables for selected logic gates.

168 Appendix D. Symbols and Truth Tables for Logic Circuits

Latches

a)

R Q R S Qn+1

L L Qn

L H H

H L L

Q̄ H H X

S

b)

R̄ & Q R̄ S̄ Qn+1

L L X

L H L

H L Hn

& Q̄ H H Q

S̄

Fig. D.2: Schematics and truth tables for latches: a) NOR-based, and b) NAND-based.

169

Appendix E

Simulation Software

The following software tools have been used during the experimental analyses and for the

implementation of the analysis framework:

logic gates and circuits,

the postprocessing in modeling issues,

DCI, the experimental implementation of the analysis concept,

2 the C++ class library wxWidgets (available at www.wxwidgets.org) for the implemen-

tation of the graphical user interface

for the implementation of a Levenberg-Marquardt optimizer

170 Appendix E. Simulation Software

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