The output of the modulator is the PHASE node. The gain of V 1 + s ⋅ ESR ⋅ C
IN OUT
GAINOPENLOOP =  ⋅ 
∆V 2
the modulator is simply the input voltage to the regulator, OSC 1 + s ⋅ ( ESR + DCR ) ⋅ C
OUT
+s ⋅L
OUT
⋅C
OUT
VIN, divided by the peaktopeak voltage of the oscillator,
∆VOSC, or: FIGURE 4. THE OPEN LOOP SYSTEM
V IN
GAIN MODULATOR = 
∆V OSC
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1888INTERSIL or 3217247143  Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Technical Brief 417
Figure 5 shows the asymptotic Bode plot of the open loop Figure 7 shows the closed loop system with a Type II
system gain. compensation network and presents the closed loop transfer
function.
V
IN
20 ⋅ log  The following guidelines will help calculate the poles and
∆V FESR
pp
0 zeroes, and from those the component values, for a Type II
FLC
GAIN (dB)
network.
2
Technical Brief 417
.
C1
R2 C2
s + 
1

R ⋅C
1 2 2
GAIN =  ⋅ 
R1 TYPEII R ⋅C C +C
1 1 1 2
VOUT s ⋅ s + 
R ⋅C ⋅C
2 1 2

VCOMP
+
REFERENCE
1

GAIN (dB)
1
 C1 ⋅ C2
2π ⋅ R 2 ⋅ C 2 2π ⋅ R ⋅ 
20dB/DEC 2 C + C
1 2
1

2π ⋅ R 1 ⋅ C 1
R2
20 ⋅ log 
R
1
0 FREQUENCY (Hz)
20dB/DEC
0 FREQUENCY (Hz)
30
PHASE
90o PHASE
“BOOST”
60
90
3
Technical Brief 417
.
VIN
OSC DRIVER
PWM
LO
∆VOSC COMPARATOR DCR VOUT
 PHASE
+
CO
ESR
C1 DRIVER
C2 R2
R1
VCOMP

+
REFERENCE
s + 
1

R 2 ⋅ C 2 V IN 1 + s ⋅ ESR ⋅ C OUT
1
GAIN =  ⋅  ⋅  ⋅ 
SYSTEM R1 ⋅ C1 + ∆V 2
C 1 C 2 OSC 1 + s ⋅ ( ESR + DCR ) ⋅ C +s ⋅L ⋅C
s ⋅ s +  OUT OUT OUT
⋅ ⋅
2
R C C
2 1
FIGURE 7. CLOSED LOOP SYSTEM WITH TYPE II NETWORK
GAIN BANDWIDTH
PRODUCT
0.1FLC 0.5 FSW
0
MODULATOR 20dB/DEC
& FILTER GAIN CONVERTER
GAIN COMPENSATION
FLC FESR GAIN
BANDWIDTH
FREQUENCY
V IN
MODULATOR = 20 ⋅ log ∆V
Where: GAIN 
OSC
2 2
– 10 ⋅ log 1 – ( 2πf ) ⋅ L + ( 2πf ⋅ ( ESR + DCR ) ⋅ C
2 2
GAIN FILTER = 10 ⋅ log 1 + ( 2πf ⋅ ESR ⋅ C OUT ) ⋅
OUT C OUT OUT )
2 C1 ⋅ C2 2
GAIN – 20 ⋅ log [ 2πf ⋅ R ⋅ ( C + C ) ] – 10 ⋅ log 1 + 2πf ⋅ R ⋅ 
= 10 ⋅ log 1 + ( 2πf ⋅ R ⋅ C )
TYPEII 2 2 1 1 2 2 C 1 + C 2
o C1 ⋅ C2
PHASE TYPEII = – 90 + atan [ 2πf ⋅ R 2 ⋅ C 2 ] – atan 2πf ⋅ R2 ⋅ 
C 1 + C 2
FIGURE 8. TYPE II COMPENSATED NETWORK
4
Technical Brief 417
Type III Compensation Figure 11 shows the asymptotic Bode gain plot for the
Type III compensated system and the gain and phase
Figure 9 shows a generic Type III compensation, its transfer
equations for the compensated system. As with the Type II
function and asymptotic Bode plot. The Type III network
compensation network, it is recommended that the actual
shapes the profile of the gain with respect to frequency in a
gain and phase plots be generated through the use of a
similar fashion to the Type II network. The Type III network,
commercially available analytical software package that has
however, utilizes two zeroes to give a phase boost of 180o.
the capability to plot.
This boost is necessary to counteract the effects of an under
damped resonance of the output filter at the double pole. The compensation gain must be compared to the open loop
gain of the error amplifier. The compensation gain should
Figure 10 shows the closed loop system with a Type III
not exceed the error amplifier open loop gain because this is
compensation network and presents the closed loop transfer
the limiting factor of the compensation. Once the gain and
function.
phase plots are generated the system may need to be
The guidelines for positioning the poles and zeroes and for changed after it is analyzed. Adjust the poles and/or zeroes
calculating the component values are similar to the in order to shape the gain profile and insure that the phase
guidelines for the Type II network. margin is greater than 45o.
1. Choose a value for R1, usually between 2k and 5kΩ.
2. Pick a gain (R2/R1) that will shift the Open Loop Gain up
to give the desired bandwidth. This will allow the 0dB
crossover to occur in the frequency range where the
Type III network has its second flat gain. The following
equation will calculate an R2 that will accomplish this
given the system parameters and a chosen R1.
DBW ∆V OSC
R 2 =  ⋅  ⋅ R 1
F LC V IN
1
C 2 = 
π ⋅ R 2 ⋅ FLC
1
C 3 = 
π ⋅ R 3 ⋅ FSW
5
Technical Brief 417
C1
R3 C3 R2 C2
R1
VOUT

VCOMP
+
REFERENCE
s + 
1
 ⋅ s + 
1
R +R R ⋅C
2 2 ( R 1 + R 3 ) ⋅ C 3
1 3
GAIN  ⋅ 
TYPEIII = 
R ⋅R ⋅C C +C
1 3 1 2
s ⋅ s +  ⋅ s + 
1 1
R ⋅ C ⋅ C R ⋅C
2 1 2 3 3
1

R 1 ⋅ R 3 ⋅ C 1
1
 1
2π ⋅  2π ⋅ ( R 1 + R 3 ) ⋅ C 3 
R1 + R3 C1 ⋅ C2
2π ⋅ R ⋅ 
2 C + C
1 2
GAIN (dB)
R2
20 ⋅ log 
R1
0 FREQUENCY (Hz)
1

2π ⋅ R 2 ⋅ C 2 1

2π ⋅ R 3 ⋅ C 3
180
90
PHASE
180o PHASE
“BOOST”
0 FREQUENCY (Hz)
90
6
Technical Brief 417
VIN
OSC DRIVER
PWM
LO
∆VOSC COMPARATOR DCR VOUT
 PHASE
+ CO
C1 ESR
DRIVER
C2 R2 C3 R3
R1
VCOMP

+
REFERENCE
s + 
1
 ⋅ s + 
1
R1 + R3 R 2 ⋅ C 2 ( R1 + R3 ) ⋅ C3 V IN 1 + s ⋅ ESR ⋅ C OUT
GAIN =  ⋅  ⋅  ⋅ 
SYSTEM R1 ⋅ R3 ⋅ C1 C1 + C2 ∆V OSC 2
1 + s ⋅ ( ESR + DCR ) ⋅ C OUT + s ⋅ L OUT ⋅ C OUT
s ⋅ s +  ⋅ s + 
1
R 2 ⋅ C 1 ⋅ C 2 R 3 ⋅ C 3
ERROR AMP
DC GAIN
CONVERTER
GAIN
OPEN LOOP
ERROR AMP GAIN
GAIN (dB)
GAIN BANDWIDTH
PRODUCT
0
20dB/DEC
MODULATOR
& FILTER GAIN COMPENSATION
GAIN
FLC FESR
BANDWIDTH
FREQUENCY
2 C1 ⋅ C2 2
GAIN = 10 ⋅ log 1 + ( 2πf ⋅ R ⋅ C ) – 20 ⋅ log [ 2πf ⋅ R ⋅ ( C + C ) ] – 10 ⋅ log 1 + 2πf ⋅ R ⋅ 
TYPEIII 2 2 1 1 2 2 C + C
1 2
2 2
+ 10 ⋅ log 1 + ( 2πf ⋅ ( R + R ) ⋅ C ) – 10 ⋅ log 1 + ( 2πf ⋅ R ⋅ C )
1 3 3 3 3
o C1 ⋅ C2
PHASE TYPEIII = – 90 + atan [ 2πf ⋅ R 2 ⋅ C 2 ] – atan 2πf ⋅ R 2 ⋅  + atan [ 2πf ⋅ ( R 1 + R 3 ) ⋅ C 3 ] – atan [ 2πf ⋅ R 3 ⋅ C 3 ]
C 1 + C 2
FIGURE 11. TYPE III COMPENSATED NETWORK
7
Technical Brief 417
Example The dive in the phase is so sharp that the 90o phase boost of
the Type II network does not compensate the phase enough
The following example will illustrate the entire process of
to have sufficient phase margin. At approximately 6kHz, the
compensation design for a synchronous buck converter.
phase margin goes below 45o and never recovers. There is
Converter Parameters nothing more that the Type II system can do to improve the
Input Voltage: VIN 5V phase. The Phase of the compensation is at it’s peak when
Output Voltage: VOUT 3.3V the phase of the filter is at it’s minimum.
Controller IC: IC ISL6520A Another problem with the Type II compensation network in
Osc. Voltage: ∆VOSC 1.5V this example is that the compensation gain intersects and
Switching Frequency: fSW 300kHz then exceeds the gain of the error amplifier open loop gain.
Total Output Capacitance: COUT 990µF As the open loop gain of the error amplifier is the limiting
Total ESR: ESR 5mΩ factor to the compensation gain, the actual gain and phase is
Output Inductance: LOUT 900nH affected by the limit and will not exceed it.
Inductor DCR: DCR 3mΩ
Due to these issues, a Type III network will need to be
Desired Bandwidth: DBW 90kHz
implemented to compensate for the phase properly.
First, a Type II compensation network will be attempted. The
low ESR of the output capacitance and the low DCR of the The guidelines for the Type III network were then followed to
output inductor may make the implementation of a Type II produce the following component values:
network difficult. R1 = 4.12kΩ (chosen as the feedback component)
The guidelines given for designing a Type II network were R2 = 20.863kΩ
followed in order to calculate the following component R3 = 151.85Ω
values: C1 = 0.2587nF
C2 = 2.861nF
R1 = 4.12kΩ (chosen as the feedback component)
C3 = 6.987nF
R2 = 125.8kΩ
C1 = 8.464pF Again, these calculated values need to be replaced by
C2 = 2.373nF standard resistor values before the gain and phase plots can
be plotted and examined.
These calculated values need to be replaced by standard
resistor values before the gain and phase plots can be R1 = 4.12kΩ
plotted and examined. R2 = 20.5kΩ
R3 = 150Ω
R1 = 4.12kΩ
C1 = 0.22nF
R2 = 124kΩ
C2 = 2.7nF
C1 = 8.2pF
C3 = 6.8nF
C2 = 2.2nF
The gain plot of the Type III compensated system in Figure
Upon analysis of the bode plots in Figure 12, it can be seen
13 looks very good. The gain rolls off at 20dB/decade from
that the system does not meet the stability criteria previously
low frequency all the way to the 0dB crossover with a small
set. The bode plot for the gain is acceptable. The gain rolls
perturbation from the LC filter double pole resonant point.
off at 20dB/decade with a perturbation at the resonant point
The phase plot shows a system that is unconditionally
of the LC filter. After the perturbation, the gain again begins
stable.
to roll off about 20dB/decade until it crosses 0dB right
around 90kHz. The phase plot shows the problem with this
Type II system. The low ESR and DCR values create a very
sharp slope downward at the double pole of the LC filter.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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8
Technical Brief 417
OPEN LOOP
80
GAIN
COMPENSATION
60 COMPENSATION
GAIN
GAIN ENCROACHING
ON ERROR AMP
40
OPEN LOOP GAIN
Gain [dB]
0
BANDWIDTH
20 SYSTEM
GAIN
40
60
10 100 1000 10000 100000 1000000
Frequency
0
COMPENSATION
20 PHASE
SYSTEM
PHASE
40
60
Phase [degrees]
80
MODULATOR
& FILTER
100
PHASE
120
140
45° PHASE
160 MARGIN
180
10 100 1000 10000 100000 1000000
Frequency
9
Technical Brief 417
100
ERROR AMP
80 OPEN LOOP
GAIN
60
40
COMPENSATION
GAIN BANDWIDTH
20
20
MODULATOR & FILTER
GAIN SYSTEM
GAIN
40
60
10 100 1000 10000 100000 1000000
70
COMPENSATION
PHASE
MODULATOR & FILTER
20
PHASE
30
SYSTEM
PHASE
80
130
45° PHASE
MARGIN
180
10 100 1000 10000 100000 1000000
10