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Agenda
Introduction to ARM Ltd
ARM Architecture/Programmers Model
Data Path and Pipelines
AMBA
Development Tools
Confidential
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ARM Ltd
Confidential
2
ARM Powered Products
Agenda
Introduction to ARM Ltd
ARM Architecture/Programmers Model
Data Path and Pipelines
AMBA
Development Tools
Confidential
3
Architecture Revisions
ARMv7 (Future)
version
ARM1156T2F-S™
ARM1136JF-S™
ARMv6
ARM1176JZF-S™
ARM102xE XScaleTM ARM1026EJ-S™
ARMv5
ARM9x6E ARM926EJ-S™
® SC200™
ARM7TDMI-S™ StrongARM ARM92xT
V4
SC100™ ARM720T™
Confidential
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Processor Modes
The ARM has seven basic operating modes:
cpsr
spsr spsr spsr spsr spsr spsr
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Confidential
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Exception Handling
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By default, data processing instructions do not affect the condition code flags but
the flags can be optionally set by using “S”. CMP does not need “S”.
loop
…
SUBS r1,r1,#1 decrement r1 and set flags
BNE loop if Z flag clear then branch
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Confidential
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Branch instructions
Branch : B{<cond>} label
Branch with Link : BL{<cond>} subroutine_label
31 28 27 25 24 23 0
Cond 1 0 1 L Offset
The processor core shifts the offset field left by 2 positions, sign-extends it
and adds it to the PC
± 32 Mbyte range
How to perform longer branches?
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Syntax:
Confidential
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Using a Barrel Shifter:The 2nd Operand
Register, optionally with shift operation
Operand Operand Shift value can be either be:
1 2 5 bit unsigned integer
Specified in bottom byte of
another register.
Barrel
Shifter
Used for multiplication by constant
Immediate value
8 bit number, with a range of 0-
255.
ALU
Rotated right through even
number of positions
Allows increased range of 32-bit
Result constants to be loaded directly into
registers
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Confidential
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Single register data transfer
LDR STR Word
LDRB STRB Byte
LDRH STRH Halfword
LDRSB Signed byte load
LDRSH Signed halfword load
Syntax:
LDR{<cond>}{<size>} Rd, <address>
STR{<cond>}{<size>} Rd, <address>
e.g. LDREQB
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Agenda
Introduction to ARM Ltd
ARM Architecture/Programmers Model
Data Path and Pipelines
AMBA
Development Tools
18
Confidential
9
The ARM7TDM Core
ABE A[31:0] Address
Incrementer
P
C BIGEND
MCLK
nWAIT
Register Bank PC Update
nRW
Instruction MAS[1:0]
A
Decode Stage Decoder
L A B ISYNC
Instruction nIRQ
U Decompression nFIQ
Multiplier nRESET
B B and ABORT
B nTRANS
u u Read Data
nMREQ
u s Barrel s Register SEQ
Shifter Control LOCK
s nM[4:0]
Logic
Write Data nOPC
Register nCPI
32 Bit ALU CPA
CPB
DBE D[31:0]
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ARM7TDMI
ARM decode
Instruction Thumb→ARM Reg Reg
Shift ALU
Fetch decompress Read Write
Reg Select
ARM9TDMI
ARM or Thumb
Instruction Inst Decode Memory Reg
Shift + ALU Write
Fetch Reg Reg Access
Decode Read
FETCH DECODE EXECUTE MEMORY WRITE
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Confidential
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ARM10 vs. ARM11 Pipelines
ARM10
Branch ARM or Memory
Prediction Shift + ALU
Thumb Reg Read Access Reg
Instruction Instruction Write
Decode Multiply
Fetch Multiply
Add
FETCH ISSUE DECODE EXECUTE MEMORY WRITE
ARM11
Data Data
Address Cache Cache
1 2
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Agenda
Introduction to ARM Ltd
ARM Architecture/Programmers Model
Data Path and Pipelines
AMBA
Development Tools
22
Confidential
11
AMBA
Arbiter Reset
ARM
TIC
Remap/
External Bus Interface Timer
Pause
ROM External
Bridge
Bus
Interface
External
RAM On-chip Interrupt
Decoder RAM Controller
AMBA ACT
Advanced Microcontroller Bus AMBA Compliance Testbench
Architecture
ADK PrimeCell
Complete AMBA Design Kit ARM’s AMBA compliant
peripherals
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HCLK
HADDR A B C
HWRITE A B C
HWDATA A B
HRDATA A B
HREADY
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Confidential
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Agenda
Introduction to ARM Ltd
ARM Architecture/Programmers Model
Data Path and Pipelines
AMBA
Development Tools
25
Debugger (+ optional
trace tools)
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Confidential
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Confidential
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