Final Report Rash

VLSI 1
Company Profile
DCN SJCIT,Chickkaballapura
VLSI 2
SILICON GATEWAY [P] LTD.
ABOUT US
Silicon Gateway [P] Ltd. commenced its operations in July 1999, with an objective of
catering to present day Electronic and Logic Design requirements and to provide end-to
end Technological solutions.
At Silicon, our willingness to challenge all technological boundaries with right
combination of creative mind and innovative business acumen and strategies has got us
big successes till now.
Silicon Varsity, a specialized division focusing on University Technical Education,
Training & Product Marketing of various Electronic Hardware and related Software
Packages to all its esteemed customers in India and overseas.
OUR MOTTO
“Coming together is beginning
Working together is progress Winning together is success”
OUR VALUES
Silicon is built on trust, integrity, long term relationships and mutual growth with time-
tested methodologies and proven track record to ensure value based quality solutions on
time.
We believe in creation of healthy wealth and sound business ethics.
VLSI 3
OUR STRENGTHS
• Technology
• People
• Entrepreneurship
• Infrastructure
• Systems and Tools
• Domain Expertise and Technical Competence
• Alliances
• Track Record
• Methodology and Quality
LEADERSHIP through people

People are key assets in our range of training programs. Since the company’s inception,
Silicon is a fusion of highly skilled techno wizards, dedicated employees, expert
consultants and innovative brand builders to deliver effective and flawless high-end
technology training services to our customers.
This has been the driving force behind Silicon’s uninterrupted ascent to market leadership
in cutting edge technologies and operations.
QUALITY
The company delivers its high value addition, mission critical solutions through out the
world according to our customer’s precise requirements.
Silicon provides maximum possible package and surveys reliability, a commitment
backed up by highly motivated team to achieve service-par-excellence for every
individual and valued end user.
VLSI 4
SILICON – Services Design

Marketing
Training
Placement
SILICON - Design Services
Powered by vision and driven by experts, we are on a mission to shorten design cycle
time in today’s changing world with shortened product life.
Design turn around time and faster time to market must be the slogan.
Success in market is largely a function of time.
Silicon is one of the first VLSI Design Company to implement Fab-less design strategy to
its end users.
Silicon produces high quality programmable logic and ASIC Design on state of art 0.5µ-
to 0.12µ-process technology.
At Silicon, innovation is process and quality deliverables are the products.
Our design objectives will be to provide high performance, low cost and user-friendly
standard products that can be customized through software programs.
We achieve this by our core competences in

• Simplifying system level integration to enable reliable performance, intuitive
interfaces and industry standard solutions.
• Developing high volume application and solutions to maneuver through the
design process.
• Extending time-in-market through field upgrades.
Silicon’s Customers are from a wide variety of markets, which includes

Telecommunications, Computing, and Networking, Industrial Control, Instrumentation,
Consumer electronics, Defense and aerospace.
Silicon’s Design emphasize on strategic R & D including the expansion of core and IP
development, IC system’s design, Product engineering and embedded real time
applications.
VLSI 5
SILICON VARSITY – Training Division

Silicon Varsity training opened its doors for electronic designers and aspirants, with the
introduction of the most popular and sought after VLSI course in India-VHDL ESCORT.
This VHDL ESCORT training program has more than 2500 success stories.
From that point forward, Silicon Varsity has been India’s leading innovator in
professional training activities in the field of VLSI, PLDs, ASICs, DSP, Embedded
applications and Communication Electronics.
For SILICON GATEWAY [P] LTD.,

J.Ravishankar M.Tech.,
CEO
Product lines – Marketing Services
VLSI DESIGN / EDA TOOLS:

• Xilinx – EDA Tools and FPGA/CPLD Demo/Evaluation Boards
• Mentor Graphics – FPGA advantage

• CADENCE – EDA Tools
• Tanner EDA, MEMSCAP etc.
• Development Kits & Demo Boards – Xilinx FPGA & CPLDs – Virtex,
Spartan
EMBEDDED SYSTEMS DESIGN TOOLS:

• Vx Works - RTOS
• KEIL, Archimedes, Renaissance - Embedded tools

• NUCLEUS – RTOS & Embedded development kit
VLSI 6
• MICRO CHIP – PIC Embedded Micro Controllers
• Cygnal – Microcontroller and trainer kits
• DYNALOG - Simulators, 8051, 8085, 8086 Development Kits,

Communication kits etc.
• Cypress Semiconductors - Embedded Development System Products
• Hitachi – Micro Controller kits and semiconductor devices
DSP SOFTWARES AND HARDWARES:

• MATLAB and Simulink DSP Software Products – sole authorized
distributor from Cranes
• SP Development Kits – from TI &Analog Devices [AD].
SPICE TOOLS:
• EDWin /EDSpice – PCB Design & Simulation packages.
• PADS - High end & multi layer PCB design Tool
COMMUNICATION TRAINER KITS:

• Analog and Digital Communication Trainers Kits.
• Optical Fiber Training Systems.
• Microwave Test Benches.
• PC Based Hi-Tech Optical Lab Equipment’s.
TEST AND MEASUREMENT INSTRUMENTS:

• HP and Agilent Technologies
• LG & Yokogawa - CROs and Spectrum Analyzers

CBT’s:
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• Dynalog Make CBT’s on topics related to Electrical, Electronics,

Instrumentation, Telecommunication, Computer Science and Information
Technology Branches.
OTHER PRODUCTS:
• PC Based Universal Device Programmers
• PC based Logic Analyzer
• Decade Boxes: Resistance, Capacitance & Inductance
• All types of active, passive components and Test and Measuring
Instruments
DESIGN ISSUES
OF
VLSI 8
DIGITAL CIRCUITS
Following are the issue to be dealt with, while designing the Digital circuits.
Drive Capabilities ( Fan In & Fan Out)
Fan-out of digital IC is the no. of standard inputs of the same family that can be
driven by gate’s output while maintaining the its outputlevels within specified limits.that
is ,it specifies the maximum loading that a given gate is capable of handling.
Consider TTL gates and their output drive & input loading parameters. A standard
TTL gate is capable of handling 16 MA when output is low (IOL) and 400µ A when
output is high(IOH). The input loading is only 40µ A for input high(IIH) and 1.6 MA for
input low (IIL). And when driving gate o/p is high current 40µ A flows into the load gate
but when low,driving gate is sinking current from the load gate. There is a limit on the
amount of current that can be sinked (16 MA) into the driving gate and this limits the no.
of gates that can be driven. Here it is 16MA/1.6MA=10 .
Fan-in of the family of IC is the load represented by a single gate . The input
loading mentioned above is the fan-in of the TTL specification given above.
VLSI 9
Propogation Delay
It is a very important characteristic of logic circuits as it limits the speed
(frequency) at which they operate. The propagation delay of a gate is basically the time
interval between the application of an input pulse and the occurrence of the resulting
output pulse.
There are two propagation delays
TPHL, the time between a specified reference point on the input pulse and a
corresponding reference point on the output pulse , with the output changing from the
High level to the low level.
TPLH, the time between a specified reference point on the input pulse and a
corresponding reference point on the output pulse , with the output changing from the
low level to the High level.
When the TPHL &TPLH are not equal the larger value is the worst case delay. The
shorter the propagation delay the higher the speed of the circuit. Propagation delay occurs
due to the parasitic elements in the circuitary.
Setup Time (Ts)

It is the minimum interval required for the control levels to be maintained
constantly on the inputs prior to the triggering edge of the clock pulse in order for the
levels to be reliably clocked into the flip-flop. This is illustrated in figure for a D-FF.
D 50% point
C
50% point of triggering
edge
Set-Up Time
VLSI 10
Hold Time (Th)

It is the minimum interval required for the control levels to remain on the inputs
after the triggering edge of the clock pulse in order for the levels to be reliably clocked
into the FF. this is illustrated in fig. below for D-FF.
D 50% point
50% point on
triggering edge
C
Hold Time
Power Dissipation
The Power Dissipation of a logic gate equals the DC supply voltage Vcc times
the average supply current Icc. The Icc for a low gate output is higher than the Icc for
high gate output.
In the logic system, the total average supply current is determined by the sum of
the average supply currents (Icc) of each gate in the system. This establishes the
requirements for the power supply or battery used to power the system.
Power consumed is directly proportion to the supplied voltage Vcc and the frequency at
which ICs are operated. Power consumption increases as the delay decreases.
Noise Margin
The DC noise margin of a gate is a measure of its noise immunity, a gate’s
ability to withstand the fluctuations of the voltage levels (Noise) at its inputs. Common
sources of noise are variations of the Dc supply voltage, ground Noise, magnetically
coupled voltages from adjacent lines, and radiated signals. The term Dc noise Margin
applies to noise voltages of relatively long duration compared to a gate’s response time.
Low level noise margin is expressed as VNL= VIL(MAX) – VOL(MAX)
VNL = Low level noise margin
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VIL(max) = Maximum Low level input voltage

VOL(MAX) = Maximum Low level output voltage
High level noise margin is expressed as VNH= VOH(MIN) - VIH(MIN)
VNH = Low level noise margin
VIH(max) = Maximum Low level input voltage
VOH(MAX) = Maximum Low level output voltage
Interfacing gates of different families

Interfacing gates belonging to different families, gives rise to issues regarding the
voltage and current incompatibilities b/n the driving and driven gates as their voltage and
current profiles for defining their logic levels may vary. This is overcome by using
Pull Up & Pull Down resistors.
The concept is enhanced using the example of driving CMOS from a TTL
Standard gate. Valid logic levels are shown in table below.
TTL CMOS
Voltage/Current profile for 0 to 0.8 volts 0 to 1.5 volt
Logic Low (16 MA) (1 µ A)
Voltage/Current profile for 2.4 to 5 volts 3.5 to 5 volt
Logic High (400 µ A) (1 µ A)
Note that the output drive currents for the standard TTL are more than adequate to drive
CMOS inputs. However, the voltage profiles do not match. The low outputs from the
TTL are compatible because they fit within the wider low input band on the CMOS IC.
There is a range of possible high outputs from the TTL IC that do not fit within the high
range of the CMOS IC. This incompatibility could cause problems. These problems can
be solved by using a pull up resistors between gates to pull the high output of the TTL up
closer to +5 volts. A completed circuit for interfacing standard TTL to CMOS is shown
in below figure.
VLSI 12
Vcc= +5V
1 KΩ TTL is the driving gate and CMOS is the

I/P O/P driven gate
TTL CMOS
GND
If CMOS is used as a driving gate and TTL as the driven gate, then there is no
compatibility issues with higher logic voltage but low logic level voltage has to be pulled
down from 1.5 volts to below 0.8 volts. This is done by using pull-down resistor between
the output and the ground.
Crosstalk
Crosstalk within the chip is by EMI between any adjacent lines carrying the
signal. As frequency increases, EMI also increases as at RF frequencies and above
radiation occurs. EMI is avoided within the chip by putting adjacent buses in different
layers of the chip separated by metal layers. Today, chips are implemented in 32 to 36
layers. EMI is reduced by preventing radiation by avoiding sharp edges in connecting
lines onboard.
Clock Skew
If clock signals arrive at the flip-flops or at the registers in a system at different
times the clock skew is said to exist. But, to have a truly synchronous system, we must
ensure that all clock pulses arrive at the FFs simultaneously throughout the system so that
all FFs trigger at the same time. In buses clock skew is reduced by choosing proper
conducting material with low resistivity and low permittivity. Skew is further reduced by
adding delay compensators.
As the dimensions of the components decrease, the supplied voltage Vcc decreases and
operating frequency increases, and number of gate components increases.
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Implementation of all gates using Mux
AND Gate
A1 A2 Q
A1
0 0 0
0 1 0
1 0 0
1 1 1
OR Gate
A2
A1 A2 Q
0 0 1
0 1 1
1 0 1
1 1 0
NOT Gate
I/P Q
0 1
1 0
X-OR Gate
A1
0
A2
0
Q
0 Gnd (0)
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0 1 1
1 0 1
1 1 0
X-NOR Gate
A1 A2 Q
0 0 1
0 1 0
1 0 0
1 1 1
Implementation of gates using RAM

Gates can be implemented using RAM. If the no. of inputs is ‘n’ then output
result for all the 2n input combination are stored in 2n corresponding locations. And,
corresponding results are retrieved from the location by using input as the address lines.
Even, Any Boolean expression involving large no. of gates and any no. of inputs can be
easily implemented using RAM.
Example: Implementing AND Gate using RAM
VLSI 15
RAM 4 * 1
00 0
Two line
Address 01 0
10 0
1
11
VHSIC HARDWARE
DESCRIPTION LANGUAGE
(VHDL)
VLSI 16
Introduction
The VHSIC Hardware Description Language (VHDL) is an industry standard language
used to describe hardware from the abstract to the concrete level. VHDL is rapidly being
embraced as the universal communication medium of design. Computer aided
engineering, workstation vendors, FPGA vendors, and ASIC vendors throughout the
industry are standardizing on VHDL as input and output from their tools. These include
simulation tool, synthesis tools, place and route tools, and so on.
History
The requirements for the language was first generated in 1981 under the VHSIC program.
The number of US companies were involved in designing VHSIC chips for the
Department of Defense(DoD) .
At that time most of the companies were using different hardware description languages
to describe and develop their integrated circuits. As a result different vendors could not
effectively exchange designs with one another.A team of three companies, IBM, Texas
Instruments and Intermetrics, were first awarded the contract by the DoD to develop a
version of the language in 1983. Consequently ,the languge was transferred to IEEE for
standardization ion 1986. After a substantial enhancement to the language, made by a
team of industry, university and DoD representatives, the language was standardized by
VLSI 17
the IEEE in December 1987; This version of the language is known as the IEEE standard
1076-1987.
The language was revised every five years. Consequently the language was upgraded
with the new features, the syntax of many constructs was made more uniform, and many
ambiguities present in the 1987 version of the language were resolved. This new version
of the language is known as the IEEE std 1076-1993.
Capabilities
• The language can be used as a exchanged medium between chip vendor and CAD
tool users. Different chip vendors can provide VHDL descriptions of their
components to system designers. CAD tool users can use it to capture the
behavior of the design at a high level of abstraction for functional simulation.
• The language can also be used as communication medium between different CAD
and CAE tools.
• The languge supports hierarchy; that is a digital system can be modeled as a set of
interconnected components; each component, in turn, can be modeled as set of
interconnected sub components
• The languge supports flexible design methodologies; top down, bottom up or
mixed.
• The language is not technology specific, but is capable of supporting technology
specific features. It can also support various hardware technologies; for example
you may define new logic types and new components; you may also specify
technology specific attributes. By being technology independent, the same model
can be synthesized into different vendor libraries.
• It supports both synchronous and asynchronous timing models.
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• Various digital modeling techniques, such as finite state machine descriptions,

algorithmic descriptions and Boolean equations can be modeled using the
language.
• The language is publically available, human readable, machine readable and
above all it is not proprietary.
• It is an IEEE and ANSI standard; therefore, models described using this language
are portable. The government also has a strong interest in maintaining this as a
standard so that reprocurement and second sourcing may become easier.
• The language supports three basic different description styles; Structural,
dataflow, and behavioral. A design may also be expressed in any combination of
these three descriptive styles.
• It supports a wide range of abstraction levels ranging from abstract behavioral
description to very precise gate-level descriptions. It does not, however, support
modeling at or below the transistor level. It allows a design to be captured at a
mixed level using a single coherent language.
• Arbitrarily large designs can be modeled using the languge, and there are no
limitations imposed by the language on the size of a design.
• The language has elements that make large scale design modeling easier; for
example, components, functions, procedures, and packages.
• Test benches can be written using the same language to test other VHDL models.
• Nominal propagation delays, min-max delays, setup and hold timing, timing
constraints and spike detection can all be described very naturally in this
language.
• The generics and attributes in the models facilitate back annotation of static
information such as timing or placement information.
• Generics and attributes are also useful in describing parameterized designs.
• A model cannot only describe the functionality of the design but also contain
information about the design itself in terms of user-defined attributes, such as
total area and speed.
VLSI 19
• A common language can be used to describe library components from different

vendors. Tools that understand VHDL models will have no difficulty in reading
models from a variety of vendors since the language is a standard.
• Models written in this language can be verified by simulation since precise
simulation semantics are defined for each language construct.
• Behavioral models that conform to a certain synthesis description style are
capable of being synthesized to gate-level descriptiond.
• The capability of defining new data types provides the power to describe and
simulate a new design technique at a very high level of abstraction with out any
concern about the implementation details.
Basic building blocks of VHDL

• Entity :
All design are expressed in terms of entities. It is the most basic building block in
a design. The uppermost level of the design is the top level entity. If the design is
hierarchial, then the top level description will have lower level description contained in it.
This lower level description will be lower level entities contained in the top level entity
description .
• Architecture :
All entities that can be simulated have an architecture description. The
architecture describes the behavior of the entity. A single entity can have multiple
architectures. One architecture might be behavioral, while another might be a structural
description of the design.
• Configuaration :
A configuaration statement is used to bind a component instance to an entity-
architecture pair. A configuration can be considered like a parts list for a design. It
VLSI 20
describes which behavior to use for each entity- much like a parts list describes which
part to use for each part in the design.
• Package :
A package is a collection of commonly used data types and subprograms used in a
design. Think of a package as a tool box that contains tools used to build designs.
• Bus :
The term bus is usually brings to mind a group of signals or a particular method of
communication used in the design of hardware. In VHDL, a bus is a special kind
of signal that may have its drivers turned off.
• Driver :
This is a source on a signal. If a signal is driven by two tristate invertors, when
both invertors are active, the signal will have two drivers.
• Attribute :
An attribute is data that is attached to VHDL objects or predefined data about
VHDL objects. Examples are the current drive capability of a buffer or the
maximum operating temperature of the device.
• Generic :
A generic is VHDL’s term for a parameter that passes information to an entity.
For instance, if an entity is a gate level model with a rise and a fall delay, values
for the rise and fall delays could be passed into the entity with generics.
• Process :
VLSI 21
A process is the basic unit of execution in VHDL. All operations that are
performed in a simulation of a VHDL description are broken into single or
multiple processes.
Hardware Abstraction
VHDL is used to describe a model for a digital hardware device. This model
specifies the external view of the device and one or more internal views. The internal
view of the device specify the functionality or structure, while the external view specifies
the interface of the device through which it communicates with other models in its
environment. The figure below shows the hardware device and the corresponding
software model.
External view
Device Model Device
Digital model
system
Internal views
In VHDL, each device model is treated as a distinct representation of a unique device

called an entity. The above figure shows the VHDL view of a hardware device that has
multiple device models, with each device model representing one entity.
VLSI 22
Entity 1 Device Model 1
Entity 2 Device Model 2

Device
Entity N Device Model 3
Actual Hardware VHDL view
Even though entity 1 through N represents N different entities from the VHDL point of
view, in reality they represent the same hardware device.
The entity is thus a hardware abstraction of the description of the actual hardware device.
Each entity is described using one model, which contains one external view and one or
more internal view.
VLSI 23
Chip Family
Spartan-II 2.5V FPGA Family
Introduction
The Spartan-II 2.5V FPGA family gives users high performance, abundant logic
resource, and a rich feature set, all at an exceptionally low price. The six-member family
offers densities ranging from 15,000 to 200,000 system gates.system performance is
supported up to 200 MHZ.
Spartan-II devices deliver more gates, I/Os and features per dollar than other
FPGA’s by combining advanced process technology with a streamlined vertex based
architecture. Features include block RAM (to 56 Kbits), distributed RAM(to 75,264 bits),
16 selectable I/O standards and four DLLs. Fast, predictable interconnect means that
successive design iterations continue to meet timing requirements.
VLSI 24
This family is superior alternative to mask programmed ASICs. The FPGA avoids
the initial cost, lengthy development cycles and inherent risk of conventional ASICs.
Also, FPGA programmability permits design upgrades in the field with no hardware
replacement necessary (impossible with ASICs)
Features
• Second generation ASIC replacement technology
− Densities as high as 5,292 logic cells with up to 200,000 system gates.
− Advanced 0.25/0.22 µm 6-layer metal process
− Streamlined features based on vertex architecture.
− Unlimited reprogrammability.
− Very low cost.
• System level features

− SelectRAM hierarchical memory- 16 bits/LUT distributed RAM, configuarable
4K bit block RAM, fast interfaces to external RAM
− Fully PCI compliant
− Low-powered segmented routing architecture
− Full readback ability for verification/observability
− Dedicated carry logic for high-speed arithmetic.
− Dedicated multiplier support
− Cascade chain for wide-input functions
− Abundant registers/latches with enable, set, reset
− Four dedicated DLLs for advanced clock control
− Four primary low-skew global clock distribution nets
− IEEE 1149.1 compatible boundary scan logic
• Versatile I/O and packaging

− Low cost packages available in all densities
VLSI 25
− Family footprint compatibility in common packages

− 16 high-performance Interface standards
− Hot swap compact PCI friendly
− Zero hold time simplifies system timing
• Fully supported by Xilinx development system

− Foundation series: fully integrated software
− Alliance series: for use with third-party tools
− Fully automatic mapping, placement, and routing
General Overview
The Spartan-II family of FPGAs have a regular, flexible, programmable architecture of
configuarable logic blocks(CLBs), surrounded by a perimeter of programmable
input/output(IOBs). There are four delay locked loops(DLLs), one at each corner of the
die. Two columns of block RAM lie on opposite sides of the die, between the CLBs and
IOB columns. These functional elements are interconnected by a powerful hierarchy of
versatile routing channel as shown in figure.
VLSI 26
Bank Bank
0 1
Bank Bank
7 2
Bank Bank
6 3
I/O Blocks
(IOB)
Bank Bank
5 4
Architecture of Spartan-II chip

Input/Output Block
The Spartan-II IOB as seen in figure below features inputs & outputs that support
a wide variety of I/O signaling standards. The three IOB registers function either as edge
triggered D-flipflops or as level sensitive latches. Each IOB has a clock signal (CLK)
shared by the three registers and independent clock enable (CE) signals for each register.
In addition to the clock and CE control signals the three registers share a set /reset (SR).
For each register, this signal can be independently configured as a synchronous set , a
synchronous reset, an asynchronous preset, or an asynchronous clear.
VLSI 27
Input path A buffer in the Spartan-II IOB input path routes the input signal either
directly to internal logic or through an optional input flip-flop. An optional delay element
at the D-input of this FF eliminates pad-to-pad hold time. The delay is matched to the
internal clock distribution delay of the FPGA, and when used , assures that the pad-pad
hold time zero. Some standards I/P buffer utilizes a user supplied threshold voltage, Vref
and this imposes constraints on which standards can be used in close proximity to each
other.
VLSI 28
Output path It includes a 3-state O/P buffer that drives the O/P signal onto the pad. The
output signal can be routed to the buffer directly from the internal logic or through an
optional IOB output FF. In most signaling standards, the output high voltage depends on
an externally supplied Vcco voltage. This imposes constraint on the standards that can be
used in close proximity to each other. An optional weak-keeper circuit is connected to
each output. When selected, the circuit monitors the voltage on the pad and weakly drives
The pin High or Low to match the input signal. If the pin is connected to a multiple-
source signal, the weak keeper holds the signal in its last state if all drivers are disabled.
Maintaining a valid logic level in this way helps eliminate bus chatter.
I/O Banking Some of the I/O standards described above require Vcco and/or Vref
voltages. These voltages are externally connected to device pins that serve groups of
IOBs, called banks. Restriction exist about which I/O standards can be combined within a
given bank. Eight I/O banks result from separating each edge of the FPGA into 2 banks.
Each block has multiple Vcco pins which must be connected to the same voltage and
determined by the o/p standard in use. Within a bank, O/P standard may be mixed only if
they use the same Vcco. Some input standards require a user supplied threshold voltage
Vref. In this case, certain I/O pins are automatically configured as inputs for the Vref
voltage. About one in six of the I/O pins in the bank assume this role. Vref pins within a
bank are interconnected internally and consequently only one Vref voltage can be used
within each bank. All Vref pins in the bank, however, must be connected to the external
voltage source for correct operation.
Configurable Logic Block

The basic building block of the Spartan-II CLB is the logic cell(LC). An LC includes a 4-
I/P function generator, carry logic, and storage element. Output from the function
generatorin each LC drives the CLB output and the D I/P of the FF. Each CLB contains 4
LCs, organized in two similar slices; a single slice is as shown in figure below. CLB also
has logic that combines function generators to provide function of five or six inputs.
VLSI 29
Look-Up Tables Spartan-II function generators are implemented as 4-input Look Up

tables(LUTs). In addition to operating as a function generator, each LUT can provide a
16*1 bit synchronous RAM. Furthermore, the two LUTs within a slice can be combined
to create a 16*2 bit or 32*1 bit synchronous RAM, or a 16*1 dual-port synchronous
RAM, 16-bit shift register that is ideal for capturing high speed or burst mode data.
Storage Elements storage elements in the Spartan-II slice can be configured either as
edge triggered D-type FF or as level sensitive latches. The D I/Ps can be driven either by
function generators within the slice or directly from slice I/Ps, bypassing the function
VLSI 30
generators. In addition to CLK and clock enable signals, each slice has synchronous set
and reset signals(SR & BY). All control signals are independently invertible under are
shared by the 2 FF within the slice.
Additional logic The F5 mux in each slice combines the function generator outputs. This
combination provides either a function generator in the CLB by selecting one of the
F5-mux O/P. This permits the implementation of any 6 I/p function, and 8:1 mux, or
selected function of up to 19 I/Ps
Arithmetic logic Dedicated carry logic provides fast arithmetic carry capability for high
speed arithmetic functions. The arithmetic logic includes an Ex-or gate that allows a 1-bit
full adder to be implemented within an LC. In addition, a dedicated and gate improves
the efficiency of multiplier implementation. The dedicated carry path can also be used to
cascade function generators for implementing wide logic functions.
BUFTs Each Spartan-II CLB contains two 3-state drivers (BUFTs) that can drive on
chip buses.
Block RAM
Spartan-II FPGAs incorporate several large block RAM memories. This complement the
distributed RAM LUTs that provides shallow memory structures implemented in CLBs.
Block RAM memory blocks are organized in columns. All Spartan-II devices contain two
such columns, one along each vertical edge.
Programmable Routing Matrix

It is the longest delay path that limits the speed of any worst case design. Consequently,
the Spartan-II routing architecture and its place and route software were defined in a
VLSI 31
single optimization process. This joint optimization minimizes long path delays, and
consequently yields the best system performance, also reduces design compilation times
as architecture is software friendly, design cycles are correspondingly reduced due to
shorter design iteration times.
Local Routing resources provides the three type of connections
• Interconnection among the LUTs, FFs and general routing matrix(GRM).
• Internal CLB feed back paths that provide high speed connections to LUTs
within the same CLB, chaining them together with minimal routing delay.
• Direct paths that provide high speed connection between horizontally adjacent
CLBs, eliminating the delay of the GRM.
General Purpose Routing most Spartan-II signals are routed on the general purpose
routing, and consequently the majority of interconnect resources are associated with this
level of the routing hierarchy. The general routing resources are located in horizontal and
vertical routing channels associated with the rows and column CLBs
I/O Routing Spartan-II have additional routing resources around their periphery that
form an interface between the CLB array and the IOBs. This additional routing, called the
versaring, facilitates pin-swaping and pin-locking such that logic redesign can adopt to
existing PCB layouts.
Dedicated Routing Some classes of signal require dedicated routing resources to
maximize performance. In the Spartan-II, dedicated routing resources are provided for
two classes of signals
• Horizontal routing resources are provided for on-chip three-state buses. Four
partitionable bus lines are provided per CLB row, permitted multiple buses
within a row as shown in figure
• Two dedicated nets per CLB propagate carry signals vertically to the adjacent
CLB.
VLSI 32
3-state
lines
Global Routing resources distribute clocks and other signals with very high fan-out
through the device. These include 2 tiers of global routing resources refer to as primary
and secondary global resources.
• The primary global routing resources are four dedicated nets with dedicated
I/P pins that are designed to distribute high fan-out clk signals with minimal
skew. Each global clock net can drive all CLB, IOB, and block RAM clk pin.
The primary global nets may only be driven by global buffers. There are four
global buffers, one for each global net.
• The secondary global routing resources consist of 24 backbone lines , 12
across the top of the chip and 12 across the bottom. From these lines upto 12
unique signals per column can be distributed via the 12 long lines in the
column. These secondary resources are more flexible than the primary
resources since they are not restricted to routing only clock pin.
Clock Distribution
The Spartan-II family provides high speed, low skew clock distribution through
the primary global routing resources. Four global buffers are provided, two at the top
centre of the device and two at the bottom centre. These drive the four primary global
nets that in turn drive any clock pin. Four dedicated clock pads are provided, one adjacent
to each of the global buffers. The input to the global buffer is selected either from these
pads or from signals in the general purpose routing.
VLSI 33
Delay Locked Loop

Associated with each global clock input input buffer is a fully digital delay locked
loop(DLL) that can eliminate the skew between the clock input pad and internal clock
input pins through out the device. Each DLL can drive two global clock networks. The
DLL monitors the input clock and the distributed clock and automatically adjust the clock
delay element. Additional delay is introduced such that clock edges reach internal flip-
flop exactly one clock period after they arrive at the input. This closed loop system
effectively eliminates clock distribution delay by ensuring that clock edges arrive at
internal FF in synchronous with clock edges arriving at the input.
It also provides advanced control of multiple clock domains. The DLL provides 4
quadrature phases of the source clock, can double clock,or divide the clock by 1.5, 2, 2.5,
3, 4, 5, 8 or 16. It has 6 outputs.
VLSI 34
Xilinx ISE & Modelsim
EDA Tools [Software]
Introduction
Integrated Software Environment (ISE) is the Xilinx design software suite. ISE can be
used by a full spectrum of designers, from the first time CPLD designer to the
experienced ASIC designer transitioning to FPGA. This overview explains the general
progression of a design through ISE from start to finish.
VLSI 35
ISE enables you to start your design with any of a number of different source types.From
your source files, ISE enables you to quickly verify the functionality of these sources
using the integrated simulation capabilities, including ModelSim Xilinx Edition and the
HDL Bencher test bench generator. HDL sources may be synthesized using the Xilinx
Synthesis Technology (XST) as well as partner synthesis engines used standalone or
integrated into ISE. The Xilinx implementation tools continue the process into a placed
and routed FPGA or fitted CPLD, and finally produce a bitstream for your device
configuration.
FPGA Design Flow Overview
Each block in the design flow is explained in the following headings.
Design Entry
VLSI 36
A source is any file that contains information about a design. ISE supports many different
source types. You can create the following types of source files with ISE. After you
create your project and select a device and design flow, you can begin creating and
adding source files.
File Type File Description

Extension
User document .doc, .txt, A document that is not implemented with the
design.
VLSI 37
ABEL-HDL Module .abl Contains ABEL design code.

HDL Module .vhd Contains VHDL design code.
HDL Package .vhd Contains, definitions, macros, sub-routines,etc.
Can be referred to by the HDL module.
Verilog Module .v Contains Verilog design code.
VHDL Library .vhd Contains a collection of packages. Can be referred
to by the HDL module. Available in the Library
View of the Sources window.
BMM File .bmm A Block RAM Memory Map file. It is in ASCII
format and describes the organization of Block
RAM memory. The BMM file is used in Virtex-II
PRO Power PC designs.
MEM File .mem A MEM file is a memory file used as input for
Block RAM input. The MEM file is used in Virtex-
II Pro Power PC, and MicroBlaze designs.
Intellectual Property .xco Intellectual Property core file generated with
CoreGen
IP Architecture Wizard .xaw Intellectual Property source generated with the
Architecture Wizard
State Diagram .dia Creates a state diagram file. You can define the
state diagram using StateCAD.
Schematic .sch Creates a schematic file. You can define the
schematic diagram using ECS.
ABEL-Test Vector .abv
Verilog Test Fixture .v Test fixture is a Verilog source. Needs to be
associated with an existing Verilog source module
VHDL Test Bench .vhd Test bench is a VHDL source. Needs to be
associated with an existing VHDL source module.
Test Bench Waveform .tbw Test bench waveform for use with HDL Bencher
only.
Chipscope Definition and .cdc For use with ChipScope Pro - ChipScope Pro must
Connection File be installed.
Implementation Constraints .ucf User-specified logical constraints file.
File
• ISE Text Editor - The ISE Text Editor is provided in ISE for entering design code
and viewing reports.
• Schematic Editor - The Engineering Capture System (ECS) is a graphical user
interface (GUI) that allows you to create, view, and edit schematics and symbols
for the Design Entry step of the Xilinx® design flow.
VLSI 38
• CORE Generator - The CORE Generator System is a design tool that delivers
parameterized cores optimized for Xilinx FPGAs ranging in complexity from
simple arithmetic operators such as adders, to system-level building blocks such
as filters, transforms, FIFOs, and memories.
• Constraints Editor - The Constraints Editor allows you to create and modify the
most commonly used timing constraints.
• PACE - The Pinout and Area Constraints Editor (PACE) allows you to view and
edit I/O, Global logic, and Area Group constraints.
• StateCAD State Machine Editor - StateCAD allows you to specify states,
transitions, and actions in a graphical editor. The state machine will be created in
HDL.
Design Synthesis
You can view XST synthesis errors in the ISE error log
file. Your synthesized design can be viewed as a
schematic in the register transfer level (RTL) viewer.
This view will show gates and elements independent of
the targeted Xilinx device.
The View RTL Schematic process is available with the

following synthesis technology tools. Select one of the
following for information about using the RTL viewer
with your synthesis tool:
VLSI 39
Design Implementation
VLSI 40
Translate Block : Running Translate on a Design

Translate is the first step in the implementation process. The Translate process merges all
of the input netlists and design constraint information and outputs a Xilinx NGD (Native
Generic Database) file. The output NGD file can then be mapped to the targeted device
family.
Functional Simulation: Simulating a Post-Translate (Functional) Model

You can perform Post-Translate (functional) simulation prior to mapping your design.
This simulation process allows you to verify that your design has been synthesized
correctly and you can begin to identify any differences due to the lower level of
abstraction.
Floorplanning a Design
You can use the Xilinx Floorplanner to view and edit location constraints in your design.
Floorplanner can be used to graphically place a design into a target Xilinx FPGA.
You can manually or automatically place logic into a floorplan of the selected FPGA. In
the Xilinx modular design flow, you can use the Floorplanner to assign location
constraints for each module in your design.
The Floorplanner can be used at several points during the design process:
• Prior to Mapping
• Prior to Place and Route
• After Place and Route
Map block: Running the Map Process

You can run the Map process after your design has been translated. The Map process
creates an NCD file. The NCD file will be used by the PAR process for further
processing.
VLSI 41
Generating Post-Map Static Timing

You can optionally generate Post-Map static timing for your design. The report generated
by this process can be read and analyzed in the Xilinx Timing Analyzer.
Generating a Post-Map Simulation Model

You can generate a Post-Map simulation model that will contain a mapping for CLBs and
IOBs in your design. A module_map.vhd or module_map.v simulation file is
created.The simulation model generated by this process is used as input to ModelSim
Xilinx Edition (MXE), HDL Bencher, or your own installed simulation program.
Manually Placing and Routing (FPGA Editor)

You can use the Xilinx FPGA Editor to manually place and route your design. You can
place and route critical components before running the automatic place and route tools.
You can also manually place components that are unplaced in your design.
The FPGA Editor requires a native circuit description (NCD) file. An NCD file contains
the logic of your design mapped to components (such as CLBs and IOBs).The FPGA
Editor writes your changes to the NCD file and to a physical constraints file (PCF).
PAR block: Generating Post-Place and Route Static Timing

You can optionally generate post-place and route static timing that will help you
determine how well your design has met timing.
This process can be run automatically during the Place and Route process by setting the
"Generate Post-Place & Route Static Timing" property.
• If the Place and Route process is out of date, Project Navigator will rerun the
processes necessary update the design files before it generates post-place and
route static timing.
• You can view the Post-Place & Route Static Timing Report in Xilinx Timing
Analyzer.
VLSI 42
Generating a Post-Place and Route Simulation Model

You can optionally generate post-place and route simulation model that will help you
determine how well your design has been placed and routed. This process can be run
automatically during the Place and Route process by setting the "Generate Post-Place &
Route Simulation Model" property.
• A module_par.vhd or module_par.v simulation file is created.

• The simulation model generated by this process can be used as input to ModelSim
Xilinx Edition (MXE), HDL Bencher, or your own installed simulation program.
• If the Place and Route process is out of date, Project Navigator will rerun the
processes necessary update the design files before it generates a post-place and
route simulation model.
Viewing/Editing a Placed Design (Floorplanner)

You can view or edit your placed design in the Xilinx Floorplanner. Floorplanning is an
optional methodology that you can use to improve the performance of your design by
constraining critical paths or adjusting the automatic placement. Floorplanning is
particularly useful on structured designs and data path logic. The Floorplanner helps you
to determine where to place logic in the floorplan for optimal results. You can place data
paths at the desired location on the die.
• The Xilinx Floorplanner displays the module_name.ngd file.

• Updates made to your design are saved to the Floorplanner Netlist File (FNF) and
to the UCF file.
View/Edit Routed Design (FPGA Editor) Process

You can view or edit your routed design in the Xilinx FPGA Editor. The FPGA Editor
requires an NCD from the Map process. An NCD file contains the logic of your design
mapped to components (such as CLBs and IOBs).
VLSI 43
This process will enable you to finish placement and routing if the routing program does
not completely route your design. You can also place and route critical components
before running the automatic place and route tools.
• The FPGA Editor reads from and writes to a physical constraints file (PCF).
• When you create a constraint in the FPGA Editor, the constraint is written to the
PCF file whenever you save your design. When you use the FPGA Editor to
delete a constraint and then save your design file, the line on which the constraint
appears in the PCF file remains in the file but it is automatically commented out.
Verification: Running the Generate Programming File Process

(FPGA)
• BitGen - The BitGen program receives the placed and routed design and produces
a bitstream for Xilinx device configuration.
• iMPACT - The iMPACT tool generates various programming file formats, and
subsequently allows you to configure your device.
• XPower - XPower enables you to interactively and automatically analyze power
consumption for Xilinx FPGA and CPLD devices.
• Integration with ChipScope Pro.
You can run the Generate Programming File process after your FPGA design has been
completely routed. The Generate Programming File process runs BitGen, the Xilinx
bitstream generation program, to produce a bitstream (.BIT) or (.ISC ) file for Xilinx
device configuration.
• All processes necessary to successfully complete the Generate Programming File

process will run automatically.
• The bit stream is saved in your project directory as file_name.bit.
• You will see a green checkmark next to the Generate Programming File process if
it ran successfully.
VLSI 44
• You can view the Generate Programming File report module_name.bgn by

double-clicking on the Programming File Generation Report process.
Back-annotating Pin Locations

You can run the Back-annotate Pin Locations process after you have implemented your
design. The Back-annotate Pin Locations process reads the NCD file (for FPGA) or the
GYD file (for CPLD). Information about the location of pins and the logical pad names is
written out to the UCF file.
By default, PIN2UCF does not write conflicting constraints to a UCF file. Prior to
creating a PINLOCK section, if PIN2UCF discovers conflicting constraints, it writes
information to a report file, named pinlock.rpt.
The Back-annotate process resolves two types of constraints issues before locking pins:
1. Multiple pins that are constrained on the same net.

2. The same pin having multiple nets.
• All processes necessary to successfully complete the Back-annotate Pin Locations

process will run automatically.
• You will see a green checkmark next to the Back-annotate Pin Locations process
if it ran successfully.
• Pin-locking constraints are written to a PINLOCK section in the UCF file. The
PINLOCK section begins with the statement #PINLOCK BEGIN and ends with
the statement #PINLOCK END. The pinout information will be applied to all
subsequent design implementation processes that you run.
• You can view the Back-annotate Pin Locations Report module_name.lck by
double-clicking on the Back-annotate Pin Report process. This report shows
any pin assignment conflicts that may have occurred.
VLSI 45
MINI PROJECT
VLSI 46
Universal Code Converter
The universal code converter takes binary input (4 bits) and gives the output (8 bit) which
is either in BCD, Excess-3, Gray code or 2s complement depending on the selection user
makes. Hamming code is generated for every binary input.
Here inputs are, 2-bit menu input to select the kind of conversion needed, binary input to
be converted and outputs are 8 bit converted code and 7 bit hamming code.
BI
8
Binary to BCD
00
Menu
(2
bits) 01 8
M M Binary to gray
Decoder MUX
10 Binary to 8 OP
Excess-3 To
LEDs
(8 bits)
11
Binary 8
2s complement
Input of Binary OP
(4 bits)
BI
M
BI
Binary to Hamming code
Hamming code
(7 bits)
The following sections explain the functioning of each block in the Universal Code
Convertor
VLSI 47
Designing
Decoder
It takes the menu input and gives four bit output where each bit is connected to
enabling input of 4 code converting blocks. Any one of the 4 blocks are enabled at once.
Table below gives the enabled block for menu input.
Menu Conversion
00 To BCD
01 To Gray
10 To 2s complement
11 To Excess-3
Conversion Blocks
Binary to BCD is done by representing each decimal digit representing binary no. by the
binary weights of four bits (i.e 8421).
Binary to Gray is done by keeping the MSB of binary as it is and then going from left to
right, add each adjacent pair of binary digits to get the next gray code digit. Discard
carry.
Binary to 2s complement is done by complementing each binary bit and then adding 1 to
the complemented binary.
Binary to Excess-3 is done by taking BCD of binary and then representing each BCD
code in its excess three form. For a single BCD code Excess-3 code is got by adding 3(i.e
0011) to it.
Binary to Hamming code for 4 bit (A3,A2,A1,A0) binary hamming code is 7 bit
(H6,H5,H4,H3,H2,H1,H0). Here H0=A0, H1=A1, H2=A2, H4=A3. H6, H5, H3 are
parity bits satisfying even parity.
H6 checks H6, H4, H2, H0 to generate parity bit.
Hamming code output is given to the seven separate output pins.
VLSI 48
Multiplexing Block (MUX)

Here input is outputs from four conversion blocks i.e 32 bits (8 bits from each
block). The output is 8 bit that is connected to output pin. MUX selects output of
selected conversion block and directs it to the common output pins. Selection is driven by
the menu input.
VHDL Code
This code implements the decoder block
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decod is
Port ( sel : in std_logic_vector(1 downto 0);
enable : out std_logic_vector(3 downto 0)
);
end decod;
architecture dec of decod is

begin
process(sel)
begin
if (sel = "00") then
enable <= '1000';
elsif (sel = "01") then
enable <= '0100';
enable <= '0010';
enable <= '0001';
end if;
end process ;
end dec;
VLSI 49
This code implements the Binary to BCD conversion
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity binbcd is
Port ( x : in std_logic_vector(3 downto 0);
y1 : out std_logic_vector(3 downto 0);
y2 : out std_logic_vector(3 downto 0);
en : in std_logic);
end binbcd;
architecture bcd of binbcd is

begin
process(x,en)
begin
if(en= '1') then
if(x <= "1001" )then
y1 <= x;
y2 <= "0000";
else
y1 <= x- "1010";
y2 <= "0001";
end if ;
end if ;
end process ;
end bcd;
This code implements the Binary to Gray conversion
entity bingray is
Port ( a : in std_logic_vector(3 downto 0);
b : out std_logic_vector(3 downto 0);
en : in std_logic);
end bingray;
architecture gray of bingray is
begin
process (a,en)
begin
if(en='1') then
VLSI 50
b(3)<=a(3);
b(2)<=a(3) xor a(2);
b(1)<=a(2) xor a(1);
b(0)<=a(1) xor a(0);
end if;
end process;
end gray;
This code implements the Binary to 2s complement
entity bintc is
Port ( p : in std_logic_vector(3 downto 0);
q : out std_logic_vector(3 downto 0);
en : in std_logic );
end bintc;
architecture tc of bintc is
begin
process( p,en)
variable temp:std_logic_vector(3 downto 0);
begin
if(en = '1') then
temp(0):=not (p(0));
temp := temp+'1';
q<= temp;
end if;
end process;
end tc;
This code implements the Binary to Excess-3 conversion
entity binxs3 is
Port ( m : in std_logic_vector(3 downto 0);
n1 : out std_logic_vector(3 downto 0);
n2 : out std_logic_vector(3 downto 0);
en : in std_logic);
end binxs3;
architecture xs3 of binxs3 is
VLSI 51
begin
process(m,en)
variable temp:std_logic_vector(3 downto 0);
begin
if(en= '1') then
if(m <= "1001" )then
n1 <= m + "0011";
n2 <= "0011";
else
temp := m - "1010";
n1 <= temp + "0011";
n2 <= "0100";
end if ;
end if ;
end process ;
end xs3;
This code implements the Binary to Hamming code conversion
entity hamcode is
Port ( c : in std_logic_vector(3 downto 0);
d : out std_logic_vector(6 downto 0));
end hamcode;
architecture ham of hamcode is
begin
process(c)
variable pc6,pc5,pc3: integer:=0;
begin
if(c(0) = '1') then
pc6:=pc6+1;
pc5:=pc5+1;
pc3:=pc3+1;
end if ;
if(c(1) = '1') then
pc5:=pc5+1;
pc3:=pc3+1;
end if;
if(c(2) = '1') then
pc6:=pc6+1;
pc3:=pc3+1;
end if ;
if(c(3) = '1') then
pc5:=pc5+1;
VLSI 52
pc6:=pc6+1;
end if;
if (pc6 = 1 or pc6 = 3) then

d(6)<= '1';
else
d(6)<= '0';
end if;
if(pc5 = 1 or pc5 = 3) then

d(5)<= '1';
else
d(5)<= '0';
end if ;
if(pc3 = 1 or pc3 = 3) then

d(3)<= '1';
else
d(3)<= '0';
end if ;
d(0)<= c(0);
d(1)<= c(1);
d(2)<= c(2);
d(4)<= c(3);
end process;
end ham;
This code implements the Multiplexing block
entity mux is
Port ( ibcd : in std_logic_vector(7 downto 0);
igray : in std_logic_vector(7 downto 0);
itc : in std_logic_vector(7 downto 0);
ixs3 : in std_logic_vector(7 downto 0);
sel : in std_logic_vector(1 downto 0);
omux : out std_logic_vector(7 downto 0));
end mux;
VLSI 53
architecture Behavioral of mux is

begin
process(sel,ibcd,igray,itc,ixs3)
begin
case sel is
when "00" => omux <= ibcd;
when "01" => omux <= igray;
when "10" => omux <= itc;
when "11" => omux <= ixs3;
when others => NULL;
end case;
end process;
end Behavioral;
output
The above code was implemented. The simulated output is covered in the next
sheet. Converted output can be observed depending on the given menu and given binary
inputs.
VLSI 54
Conclusion
The Industrial training was focused on giving light into the issues to be taken care
of while designing the digital circuits. The VLSI designing, with the aid of VHSIC
Hardware Description Language (VHDL) which is an industry standard language used to
describe hardware from the abstract to the concrete level was learnt.
The hardware implementation of the codes were done using Spartan-II chip. Its
architecture and programming of the chip was demonstrated. The knowledge of Xilinx
Tools and Modelsim , an EDA tools were gained.
VLSI designing compacts the communication system circuit, and helps the
communication systems get portable to the maximum extent.
Bibliography
• VHDL by Douglas L. Perry
• VHDL by J.Bhaskar
• Digital Fundamentals by Floyd
• Digital Electronics by Tokheim
• Logic & computer Design Fundamentals by Morris Mano
• Spartan Chip Manual
• Website: www.xilinx.com

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VLSI 1

SILICON GATEWAY [P] LTD.

“Coming together is beginning

Working together is progress Winning together is success”

LEADERSHIP through people

SILICON – Services Design

We achieve this by our core competences in

Silicon’s Customers are from a wide variety of markets, which includes

SILICON VARSITY – Training Division

For SILICON GATEWAY [P] LTD.,

Product lines – Marketing Services

VLSI DESIGN / EDA TOOLS:

• Mentor Graphics – FPGA advantage

EMBEDDED SYSTEMS DESIGN TOOLS:

• KEIL, Archimedes, Renaissance - Embedded tools

• MICRO CHIP – PIC Embedded Micro Controllers

• Cygnal – Microcontroller and trainer kits

• DYNALOG - Simulators, 8051, 8085, 8086 Development Kits,

• Hitachi – Micro Controller kits and semiconductor devices

DSP SOFTWARES AND HARDWARES:

COMMUNICATION TRAINER KITS:

TEST AND MEASUREMENT INSTRUMENTS:

• LG & Yokogawa - CROs and Spectrum Analyzers

• Dynalog Make CBT’s on topics related to Electrical, Electronics,

Drive Capabilities ( Fan In & Fan Out)

Setup Time (Ts)

Hold Time (Th)

VIL(max) = Maximum Low level input voltage

Interfacing gates of different families

1 KΩ TTL is the driving gate and CMOS is the

Implementation of all gates using Mux

Implementation of gates using RAM

Example: Implementing AND Gate using RAM

• Various digital modeling techniques, such as finite state machine descriptions,

• A common language can be used to describe library components from different

Basic building blocks of VHDL

In VHDL, each device model is treated as a distinct representation of a unique device

Entity 1 Device Model 1

Entity 2 Device Model 2

Entity N Device Model 3

Actual Hardware VHDL view

• System level features

• Versatile I/O and packaging

− Family footprint compatibility in common packages

• Fully supported by Xilinx development system

Architecture of Spartan-II chip

Configurable Logic Block

Look-Up Tables Spartan-II function generators are implemented as 4-input Look Up

Programmable Routing Matrix

Delay Locked Loop

Xilinx ISE & Modelsim

EDA Tools [Software]

FPGA Design Flow Overview

Each block in the design flow is explained in the following headings.

File Type File Description

ABEL-HDL Module .abl Contains ABEL design code.

The View RTL Schematic process is available with the

Translate Block : Running Translate on a Design

Functional Simulation: Simulating a Post-Translate (Functional) Model

Map block: Running the Map Process

Generating Post-Map Static Timing

Generating a Post-Map Simulation Model

Manually Placing and Routing (FPGA Editor)