I – 8255 PROGRAMMABLE PERIPHERAL INTERFACE

8255 is a widely used programmable parallel I/O device. This is

also named as programmable peripheral input output port. 8255 is
designed to use with 8 bit, 16 bit and higher capability microprocessor.
This 8255 has 24 input/output lines, which can be individually
programmed. These I/O lines can be grouped as Group A and Group B.
Group A contains an 8-bit port A along with a 4-bit port C upper. Group
B contains an 8-bit port B along with a 4-bit port, c lower. The C upper
and C lower ports can be combined be use as an 8-bit port. Thus for on
8255 we can have either three 8 bit I/O ports or two 8 bit and two 4 bit
ports. All these ports can function independently either as input or as
output ports. This can be achieved by programming the bits of an internal
register called as Control Word Register (CWR). The internal block
diagram is shown in the fg.

The read/write control logic controls the 8-bit data bus buffer. The
read/write control logic manages all the internal and external transfers of
both the data and control words. RD, WR, A1, A0 and RESET ate the
input provided by the microprocessor to read/write control logic of 8255.

The bidirectional 8-bit data buffer is used to interface the 8255’s

internal data bus with the external system data bus. This buffer receives
or transmits data up on the execution of input or output instructions by
the microprocessor. The control word or the status information is also
transferred through the buffer.

Signal Descriptions of 8255

The Read/write control logic is having six signal lines. Which are
RD, WR, RESET, CS, A0 and A1

RD [READ] :- This control signal enables the read operation. When the
signal is low, the microprocessor reads data from a selected I/O port of
8255

WR [WRITE] :- This control signal enables the write operation. When

the signal goes low the MPU (microprocessor) writes into a selected I/O
port or the control register.

RESET :- This is an active high signal, A logic high on this line clears
the control word register and set all ports in the input mode. (that is , set
as input port by default after reset)

1
CS [CHIP SELECT] :- This is a Chip Select line. If the line goes low it
enables the 8255 to respond to RD and WR signals.

A1 – A0 :- These are address lines driven by the microprocessor. These

address lines are used for selecting any one of the three ports or a control
word.

CS A1 A0 Selected

0 0 0 Port A
0 0 1 Port B
0 1 0 Port C
0 1 1 Control Register
1 X X 8255 is not selected.

PA7 – PA0 :- These are eight port A lines that act either as input or output
lines depending up on the control word loaded into the control word
register.

PC7 – PC4 :- These are four Port C upper lines that can act as input or
output lines. This port can be used for the generation of handshake lines.

PC3 – PCo : - These are four port C lower lines that can act as input or
output lines. This port can also be used for the generation of handshake
lines.

PB0 – PB7 :- These are 8 port B lines which can be input or output lines
in the same way as port A

D0 – D7 :- These are the data bus lines that carry data or control word
to/from the microprocessor.

This 8255 is a widely used, flexible and economical I/O device that
can be used with almost all microprocessors when multiple I/O ports are
required. 8255 is a 40 pin IC.

2
MODES OF OPERATION OF 8255

All the functions of 8255 A is classified according to two modes: the Bit
Set/Reset (BSR) mode and the I/O mode. The BSR mode is used to set or
reset the bits in port C. The I/O mode is further divided into three modes:
Mode 0, Mode 1 and Mode 2. In Mode 0, all ports function as simple as
I/O ports. Mode 1 is a handshake mode whereby port A and port B use
bits from port C as handshake signals. In the handshake mode, two types
of I/O data transfer can be implemented: status checks and interrupt. In
Mode 2 port A can be set up for bidirectional data transfer using
handshaking signals from port C and port B can be set up either in Mode
0 or Mode 1.

1. I/O MODE

in this mode all 8255 ports will be function as programmable I/O

ports. It can be again classified into three as follows:

Mode 0 : Simple Input or Output

This is also called basic I/O mode. In this mode, ports A and B are
used as two simple 8-bit I/O ports and port C as two 4-bit ports. Each port
(or half-port in case of C) can be programmed to function as simply an
input or an output port. The input/output features in Mode 0 as follows:

1. Output is latched.
2. Inputs are not latched.
3. Ports do not have handshake or interrupt capability.
4. Any port can be used as input or output port.
5. 4-bit can combined used as a third 8-bit port.

Mode 1: Input or Output with handshake

This is also called strobe I/O mode. In Mode 1: handshake signals

are exchanged between the MPU and peripherals prior to data transfer.
The features of this mode include the following:

1. Two ports (A and B) function as 8-bit I/O ports. They can be

configured either as input or output ports.

3
 2. Each port uses three lines from port C as handshake signals.
The remaining two lines of port C can be used for simple I/O
functions.
3. Input and output data are latched.
4. Interrupt logic is supported.

In the 8255, the specific lines from port C used for handshake
signals vary according to the I/O function of a port. Therefore input
and output functions in Mode 1 are discussed separately.

MODE 1: Input Control Signals

The associated control signals are used for handshaking when ports
A & B are configured as inputs. Port A uses PC3, PC4, PC5 and PC0, PC1,
PC2. The functions of these signals are as follows:

STB (Strobed input): This signal is generated by a peripheral device

to indicate that it has transmitted a byte of data . The 8255, in response to
this signal, generates IBF and INTR.

IBF(input Buffer Full): This signal is an acknowledgement by the

8255A to indicate that it the input latch has received the data byte. This is
reset when the MPU reads the data.

INTR(Interrupt Request) :- This is an output signal that may be used to

interrupt the MPU. This signal is generated if STB,IBF and
INTE(Internal flip flop) are all at logic 1. this is reset by the falling edge
of the RD Signal.

INTE(Interrupt Enable): This is an internal flip flop used to enable

or disable the generation of the INTR. The 2 flip flops INTEA and INTEB
are set/reset using the BSR mode. The INTEA is enabled or disabled
through PC4 and INTEB is enabled or disabled through PC2.

MODE 1: Output Control Signals:

The signals when port A & B are configured as output ports as

follows:

OBF(Output Buffer Full):- This is an output signal that goes low when
the MPU writes data into the output latch of the 8255 A.
This signal indicates to an output peripheral that new data are ready to be

4
read. It goes high again after the 8255A receives an ACK from the
peripheral.

ACK (Acknowledge):- This is an input signal from a peripheral that

must output a low when the peripheral receives the data from the 8255A
ports.

INTR(Interrupt Request):- This is an output signal, and it is set by the

rising edge of the acknowledge signal. This signal can be used to
interrupt the MPU to request the next data byte for output. The INTR is
set when OBF, ACK and INTE are all one and reset by the falling edge of
WR.

INTE(Interrupt Enable):- This is an internal flip flop to a port and

needs to be set to generate the INTR signal. The two flip flops INTEA and
INTEB are controlled by bits PC6 and PC2 respectively, through the BSR
mode.

PC4,5:- These two lines can be set up either as input or output.

Mode 2: Bidirectional Data Transfer

This is also called strobe bi-directional I/O mode. This mode is

used primarily in applications such as data transfer between two
computers of floppy disk controller interface. In this mode, Port A can be
configured as the bidirectional port and port B either in Mode 0 or Mode
1. Port A uses five signals from port C as handshake signals for data
transfer. The remaining three signals from port C can be used as simple
I/O or as handshake for port B.

2. BSR MODE:

The BSR mode is concerned only with the 8 bit of port C, which
can be set or reset by writing an appropriate control word in the control
register. A control word with bit d7=0 is recognized as a BSR control
word. It does not alter any previously transmitted control word with bit
d7=1 : thus the I/O operations of ports A & B are not affected by the BSR
control word. In the BSR mode individual bits of port C can be used for
applications such as an on/off switch.

CONTROL WORD REGISTER

5
 The figure below shows the register called the control
register. The contents of this register called the control word specify an
I/O function for each port, that is the ports can function independently as
input or output ports, which is achieved by the Control Word Register
(CWR).

Bit D7 of the control register specifies either the I/O function or the
Bit Set/ Reset function. If the bit D7=1, bits D6-D0 determine the I/O
function in various modes. If bit D7=0, port C operates in the Bit
Set/Reset (BSR) mode. The BSR control word does not affect functions
of port A and B.

To communication with peripherals through the 8255, three steps are

necessary:

1. Determine the addresses of ports A,B and C and of the control

register according to the Chip Select logic and the address lines
A0 and A1.
2. Write a control word in the control register.
3. Write I/O instructions to communicate with the peripherals
through ports A, B and C.

8279 KEYBOARD/ DISPLAY CONTROLLER

Intel’s 8279 is a general purpose keyboard display controller that

simultaneously drives the display of a system and interfaces a keyboard
with the CPU leaving the CPU free for its routine task. The keyboard
display interface scans the keyboard to identify if any key has been
pressed and sends the code if the pressed key to the CPU. This also
transmits the data received from the CPU to the display device. The
controller performs both of these operations without involving the CPU.

The 8279 is a 40 pin drive with two major segments, Keyboard and
Display. The keyboard can be connected to a max of 64 – contact ky
matrix. Keyboard entries are denounced and stored in the internal FIFO
RAM and an interrupt signal is generated with each entry. The display
segment can provide a 16 character (byte) scanned display. This segment
contains 16 x 8 R/w memory (RAM), which can be used to read or write
information for the display purposes. This 16-byte display RAM can be
used either as an integrated block of 16 x 8 bits or 16 x 4 bits of 2 blocks.
The internal architecture of 8279 is shown in the fig.

6
 The keyboard display controller 8279 is provided with a) set of
four scan lines and eight return lines for interfacing keyboards.

b) a set of eight output lines for interfacing the display.

I/O CONTROL :- This I/O control block controls the flow of data to or
from the 8279. This A0. RD, WR Select the command, status or data
read/write operations carried out by the CPU with 8279.

DATA BUFFER:- This data buffer interface the internal bus of the 8279
with the external system bus. This can be used to transfer data, status/
control word.

CONTROL AND TIMING REGISTER :- These registers store the

keyboard and the display modes and other operating conditions
programmed by the CPU. These registers are writer with A0 = 1 and WR
= 0.

TIMING AND CONTROL UNIT :- Timing and control unit controls

the basic timings for the operation of the circuit.

SCAN COUNTER :- Scan Counter divide down the operating frequency

of 8279 to device scan keyboard and refresh display frequencies. The
scan counter has two modes to scan the key matrix and refresh the display
which are encoded scan mode and decoded scan more.

RETURN BUFFER AND DEBOUNCE AND CONTROL :- This

section scans for a key closure row wise. If a key closure is detected the
keyboard denounce unit denounces the key entry. After the denounce
period if the key continues to be detected the code of the key is directly
transferred to the FIFO RAM along with SHIFT and CONTROL key
status.

FIFO /SENSOR RAM AND STATUS LOGIC :- In keyboard or

strobed input mode this FIFO / Sensor RAM act as a 8 byte first in first
out RAM [FIFO RAM] . Each key code of the pressed key is entered in
the order of entry is read by the CPU. The status logic generates an
interrupt for each FIFO read operation.

In scanned sensor matrix mode this unit acts as sensor RAM. Each
row of the Sensor RAM is loaded with the status of the corresponding

7
row of the sensors in the matrix. If the sensor changes its state the IRZ
line goes high to interrupt the CPU.

DISPLAY ADDRESS REGISTER

The display address register hold the address of the word currently
being written or read by the CPU to or from the display RAM.

DISPLAY RAM:- This 16 byte display RAM contains the 16 bytes of

data to be displayed on the 16 seven segment displays.

SIGNAL DESCRIPTION OF 8279

DB0 – DB7 :- These are bidirectional data bus lines. The data and
command words to and from the CPU are transferred on these lines.

CLK :- This is a clock input used to generate internal timings required by

8279.

RESET:- This pin is used to reset 8279. A high on this line resets 8279.
After resetting 8279 is in sixteen 8 bit display, left entry display mode
and 2 key lock out mode.

CS [CHIP SELECT] :- A low on this line enables 8279 for the read or
write operations.

A0 :- A high on this line indicates the transfer of a command or status

information. A low on this line indicates the transfer of data. This can be
used to select one of the internal registers of 8279.

RD, WR [READ, WRITE] :- These signal allows the data buffer to

receive or send data over the data bus.

IRQ :- The interrupt line goes high when there is data in the
FIFO/Sensor RAM. This line goes low with each FIFO RAM read
operation. If the FIFO RAM again contain any key code entry to be read
by CPU this pin again goes high to generate an interrupt to the CPU.

SL0 – SL3 [SCAN LINES] :- These lines are used to Scan the key board
matrix are used to scan the key board matrix and to refresh the display.
These lines can be programmed as encoded or decoded using the mode
control register.

8
RL0 – RL7 :- These are the input lines one terminal of the key is
connected to this line and other terminal is connected to the scan lines.
These are normally high and pulled low when a key is pressed.

SHIFT :- The status if the Shift input is stored along with each key code
in FIFO; in scanned key board mode.

CNTL/STB CONTROL/STROBED I/P MODE:- In the keyboard

mode this line is used as a control input and is stored in the FIFO on a
key closure.

In the strobe input mode this line is a strobe line that enters the data
into the FIFO RAM.

BD [BLANK DISPLAY]:- This is an output pin and is used to blank the

display.

OUT A0 – OUT A3 and OUT B0 – OUT B3 :- These are the output lines
of two 16 x 4 or 16 x 8 internal display registers. The data from these
lines are synchronized with the scan lines to refresh the display. The two
4-bit ports can also be used as one 8 bit port.

Modes of Operation of 8279

I) Input or Keyboard Mode.

II) Output or Display Mode.

I) Input or Keyboard Mode

8279 provides 3 input modes.

Which are a) Scanned Keyboard Mode

b) Scanned Sensor Matrix Mode.
c) Strobed Input Mode.

a) Scanned Keyboard Mode :- This mode allows a key matrix to be

interfaced using either encoded or decoded scan. In encoded scan an 8 x 8
keyboard or in decoded scan a 4 x 8 keyboard can be interfaced. The code
of the pressed key along with the status of the control and shift is stored
into the FIFO RAM. This can be performed in 3 methods, which are

1) Scanned Keyboard Mode with 2 key LOCKOUT.

2) Scanned Keyboard with N – Key Rollover.

9
 3) Scanned Keyboard Special error Mode.

1) Scanned Keyboard Mode with 2 Key LOCKOUT.

In this mode of operation when a key is pressed a debounce logic

comes into operation. The other key are checked for closure during the
next two [debounce cycle] keyboard scans and if no other key is pressed
the first pressed key is identified and the key code of this identified key is
entered into the FIFO RAM along with the SHIFT and CONTROL status.
Provided the FIFO is not full. If the FIFO have no space then the data
will not be entered and the error flag is set. If the FIFO has one free byte
then the above code is entered and 8279 generates and interrupt to the
CPU to inform about the key closure. If other key is found closed during
the two scans no entry to the FIFO is made. If two key pressed with in a
debounce cycle no key is recognized.

2) Scanned Keyboard with N-Key Rollover

In this mode each key press is treated independently. When a key is

pressed the debounce circuit waits for keyboard scans and check whether
the key is still pressed. If it is still pressed the code of the pressed key is
entered into the FIFO RAM. Here any number of keys can be pressed
simultaneously or not, here the keys are sensed in the order of depression.

3) Scanned Keyboard Special Error Mode

This mode is valid under the N-key Rollover Mode. This mode is
programmed using error mode set command. If during a single debounce
period [debounce cycle] two keys are found pressed, that is considered as
simultaneous depression and an error flag is set in this case. This error
flag if set prevents the further writing in FIFO but allows the generation
of interrupts to CPU for FIFO READ. This error flag can be read by
reading the FIFO Status word. This error flag can be reset or the FIFO
can be cleared by using the clear command with CF = 1 [clear FIFO]

B] Scanned Sensor Matrix Mode

In this mode a sensor matrix can be interfaced with 8279 using

encoded or decoded scans. With encoded or decoded scans. With encoded
scan 8 x 6 sensor matrix or with decoded scan 4 x 8 Sensor matrix can be
interfaced. The sensor codes are stored in the sensor RAM. This can be
performed as

10
 1) Sensor Matrix Mode:- In the sensor matrix
mode 8 bit FIFO RAM act as an 8 x 8 memory matrix. The status
of the sensor matrix is fed in to sensor RAM matrix. Thus the
sensor RAM contains the Row wise and Column wise status of the
sensors in the Sensor Matrix. The IRQ line goes high if any
change in the sensor value is detected and this IRQ line is reset by
the data read operation.

2) Output or Display Mode :- 8279 provides two output mode for

the display

a) Display Scan
b) Display Entry

a) Display Scan

In this mode 8279 provide 8 or 16 character multiplexed display

and can be organized as dual 16 x 4 or single 16 x 8 display units.

b) Display Entry

This mode provides two options for data entry on the displays.
First one is known as left entry mode and the second as right entry mode.
This left entry mode is also known as typewriter mode and right entry
mode is known as calculator mode.

1) Left Entry Mode

In this mode data is entered from the left side of the display
unit. Address 0 of the display RAM contains the left most
display character and the address 15 of the RAM contains
the right most display character. The display RAM address is
on the auto increment mode. The first entry is displayed on
the left most display and the sixteenth entry on the right
most display. The seventeenth entry is again displayed at the
leftmost display section.

2) Right Entry Mode

In this mode the first display character is entered on the right
most display. The next entry is also placed on the right most
display by shifting the previous display by one display
position. The left most display character is shifted out of the

11
 display at the seventeenth entry and is lost ie., it pushed out
of the display RAM.

8251 PROGRAMMABLE COMMUNICATION INTERFACE

[ 8251 USART]

Programmable communication interface is used for the serial data

transmission. 8251 is a programmable communication interface. This is
a universal Synchronous / Asynchronous Receiver/Transmitter (USART).
This can be programmed to operate in any of the serial communication
mode. 8251 accepts data in the parallel format from the microprocessor
and converts them into serial data for transmission. It also receives serial
data and converts them into parallel and sends the data in parallel format
to the CPU. The modes of data transmission between two points can be
simplex, duplex or half duplex. The architecture of 8251 is shown in the
fig.

DATA BUFFER :- This data buffer interfaces the internal bus of

8251 with the system bus. This can transfer data and control word.

READ/WRITE Control Logic:- This READ/WRITE control logic

controls the operation of the peripheral depending on the operations
initiated by the CPU. This unit also selects one of the two internal
addresses i.e., control address or data address with the help of C/D signal.

Modem Control Unit: - This modem control unit handles the modem
handshake signals to coordinate the communication between modem and
the USART. Modem is used as a modulating/demodulating device.

Transmit Control: - This unit transmits the data byte received by the
data buffer from the CPU, for further serial communication. The transmit
rate is controlled by the T x C input frequency of this unit. This also
contain two status signal named T x RDY and T x EMPTY. Which the
CPU for handshaking can use?

Transmit Buffer: - This transmit buffer is a parallel to serial converter

that receives parallel byte of data from CPU for conversion into a serial
signal. This unit transmits this serial signal onto the communication
channel.

Receive Control :- This receive control unit decides the receive

frequency . Which does the R x C input frequency control? This unit

12
generates a R x RDY receiver ready signal that can be used by the CPU
for handshaking. This unit also detects the break in the data string while
8251 is in a synchronous mode and detects the synchronous characters in
synchronous mode. Using the SYNDET/BD pin.

Receiver Buffer :- This can be considered as a serial to parallel

converter which can receive the serial stream of data and convert it in to
parallel data format for transmitting it to the CPU.

Signal Description of 8251

D0 – D7 :- This 8 bit data bus used to read or write status, command

word or data from or to the 8251.

C/D [Control Word/ Data]:- This input pin informs the 8251 that the
word on the bus is either a data or control/status information. In the pin
is 1 control/status is on the bus, otherwise data is on the bus.

RD [READ] :- This is an active low input which is used to inform that

CPU is reading either data or status information from 8251.

WR :- This is an active low input which is used to inform that the CPU
is writing data or control word to 8251.

CS [Chip Select]: - This active low input is used to activate 8251. It is

high no read or write operation can be performed out on 8251.

CLK :- This CLK is used to generate the internal device timings. The
frequency should be 30 times greater than the receiver or transmitter data
bit transfer rate.

RESET :- A high on this set the 8251 A into an idle state. The device
will remain idle till this signal goes low and a new control word is written
into it.

T x C [Transmitter Clock Input] :- The transmitter clock input controls

the rate at which the character is to be transmitted. The band rate is equal
to the T x C frequency in synchronous transmission mode and in
asynchronous mode the band rate will be one of the three fractions, 1,
1/10 or 1/64 of the T x C

13
T x D [Transmitted Data Output] :- This output pin carries the serial
stream of the transmitted bits along with the information’s like start bit,
stop bit and parity bit.

R x C [Receiver Clock Input] :- This receiver clock input pin controls

the rate at which the character is to be received. In synchronous mode the
band rate is equal to R x C frequency and in asynchronous mode band
rate is one of the three functions ie, 1, 1/16 and 1/64th of the R x C
frequency.

R x D [Receiver Data Input] :- This pin receives a composite stream of

the data to be received by 8251 indicate that the 8251 or terminal is ready
to send data.

DSR [ Data Set Ready]:- This signal is used to reply 8251 for DTR
signal. By making this signal active the modem replies 8251 that it is
ready for the transmission of data.

RTS [Request to Send] :- This signal is used for the initiation of data
transmission. When both the modem and 8251 are ready for data
transmission then the 8251 initiate the data transmission by activating the
RTS signal.

CTS [Clear To Send] :- This is used to acknowledge 8251 for RTS

signal. A low CTS activates this signal.

RxRDY[Receiver Ready Output] :- This output line indicates that the

8251 contains a character to be read by CPU. To set the R x RDY signal
in synchronous and in asynchronous mode, the transmitted characters
must be assembled in the receiver and then be transferred to the data
output register. If the CPU before the assembly of the next data byte the
overrun condition error flag does not successfully read the data is set.

T x RDY [Transmitter Ready] :- This signal indicates to the CPU that

the internal circuit of the transmitter is ready to accept a new character for
transmission from CPU.

DTR [Data Terminal Ready] :- This signal is sent by the 8251 to the
modem to an active CTS signal enables the transmission logic of 8251.

T x E [Transmitter Empty] :- While transmitting if 8251 has no

characters to transmit the TxE output goes high and goes low when a

14
character is received from the CPU for further transmission. This can be
used to indicate the end of a transmission mode.

SYNDET/BD [Sync Detect/ Break Detect] :- The SYNDET pin is used

in the Synchronous mode for detecting the SYNC Characters. This can be
used as either input or output SYNDET.

In the asynchronous mode the pin acts as a break detect. This goes
high when the R x D pin remains low for two consecutive stop bit
sequences.

Operating Modes of 8251

The 8251 can be programmed to operate in various modes using its

mode control words. A set of control words can be written into the
internal registers to make it operate in the desired mode.

When 8251 is programmed as required then the T x RDY output

raise high to signal the CPU that 8251 is ready to receive a data byte,
which is to be converted to serial format and transmitted. This will go
low when the CPU writes a data to 8251. In the receiving mode the 8251
receive serial data byte and the R x RDY signal is raised high to inform
the CPU that 8251 has a character ready for it. After the CPU read
operation this signal goes low.

The control word of 8251 is divided into two functional groups.

1) Mode Instruction Control Word.

2) Command Instruction Control Word.

1) Mode Instruction Control Word.

This defines the general operational characteristics of 8251.

This must be written to configure 8251 after the reset operation. This can
be (a) asynchronous or (b) Synchronous mode instruction control word.
To change from one mode to another mode require a reset operation.

(a) Asynchronous mode:- This consists of asynchronous mode

transmission and reception.

[I] Asynchronous Mode (Transmission)

15
 In this mode when data characters are sent it adds start bit followed
by stop bits and parity bits. This sequence is then transmitted using the T
x D output pin on the falling edge of T x C.

[II] Asynchronous Mode (Receive)

In the receiving side if a start bit is marked as a valid start bit then
a bit counter starts counting. The bit counter locates the data bits, parity
bit and stop bit. If a parity error occurs then the parity error flag is set. If
an error in the frame is detected then framing error flag is set. When the
received character is loaded in the buffer R x RDY then raise high to
indicate CPU that a character is ready for it. An overrun flag is set in the
case of previous characters loss in the buffer by the overwriting of buffer
with new characters.

b) Synchronous Mode

This consists of Synchronous mode transmission and reception.

[I] Synchronous Mode (Transmission)

In this mode SYNC character are sent by the CPU initially. If in

any case the CPU buffer becomes empty. The SYNC character or
Characters are inserted in the data stream over T x D output. The Tx
EMPTY is raised high when SYNC characters are transmitted. The data
stream consists of the SYNC characters along with the data.

[II] Synchronous Mode (Receiver)

In this mode the character synchronous can be obtained internally

or externally. If this mode is selected then 'ENTER HUNT' command
should be included as first command instruction word written into 8251.
The content if the receiver buffer is compared with the first SYNC
character. If 8251 is programmed for two SYNC characters then the
subsequent received characters is also checked. When it match the
hunting stops and the SYNDET pin is set high.
In external synchronous mode, synchronization is achieved by
applying a high level on the SYNDET pin which forces the 8251 out of
HUNT mode.

2) Command Instruction Control Word.

16
 This controls the actual operations of the mode selected. The
operations like enable transmit/receive error reset and modem control.
Once the mode instruction has been written into 8251 then all control
words written with C/D =1 will load a command instruction. A reset
operation returns 8251 back to mode instruction format.

17