Sie sind auf Seite 1von 6

Prathyusha Konduri et al.

/ (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES


Vol No. 5, Issue No. 2, 195 - 200

Low Power RAM using Gate-Diffusion-Input


Technique : A Comparison with Static CMOS
Prathyusha Konduri Magesh Kannan.P
Student, M.Tech (VLSI Design), Asst Prof (Senior), VLSI Division,
SENSE, VIT University, Vellore SENSE, VIT University, Vellore
Tamil Nadu, India Tamil Nadu, India
prathyushakonduri@gmail.com mageshkannan.p@vit.ac.in

Abstract— Now a days in digital VLSI circuits, low power design this technique in D Flip-Flop and RAM. Section VI presents
has become one of the main concerns. In this paper a new the simulation results and section VII concludes the paper.

T
implementation of RAM in Gate-Diffusion-Input (GDI)
Technique is presented. This design allows reduction in power, II. CMOS LOGIC DESIGN TECHNIQUES
transistor count, access time and provides full swing. The design
is simulated in 0.18µm TSMC technology with the supply voltage To reduce the power consumption different CMOS logic
of 1.8V. design techniques like CMOS complementary logic, Pseudo
nMOS, Dynamic CMOS, Clocked CMOS logic (C2MOS),
Keywords- Low power; VLSI; Sub threshold region; GDI CMOS Domino logic, Cascade voltage switch logic (CVSL),
technique; Flip-Flops; RAM; Sequential circuits. Modified Domino logic, Pass Transistor Logic (PTL) have
ES I. INTRODUCTION
Power dissipation has become a prime constraint in high
performance applications, especially in portable and battery
operated ASIC systems so it is necessary to reduce power
consumption. Power consumption is proportional to square of
supply voltage [1]. Technology scaling can be used in which
been proposed [7].
One form of logic that is popular for in low-power digital
circuits is PTL [8]. The advantages of PTL over standard
CMOS design are
1) High speed, due to small node capacitances.
2) Low power dissipation, as a result of reduced
number of transistors.
3) Lower interconnection effect, due to smaller
the threshold voltage is scaled in proportion to the supply area.
In spite of these advantages of PTL, there are two
voltage. As technology scales, leakage currents have become
main drawbacks. One is the threshold voltage across the single
one of the main power consumers and this leads to increase in channel pass transistors results in reduced drive and hence
sub threshold leakage power. Many design architecture and slower operation at reduced voltages and the other one is,
techniques have been developed to reduce power dissipation since the high input voltage level is not VDD the PMOS
A
[1] – [3]. device in inverter is not fully turned off. In order to overcome
Of the various building blocks in digital designs one of the these problems some sort of PTL techniques have been
most complex and power consuming is the Flip-Flop. proposed [9-10].
Transmission gate CMOS (TG) uses transmission
Although several Flip-Flop designs have been proposed to
gate logic to realize complex logic functions using less
reduce power consumption, they are not suitable for operation number of transistors. It solves the problem of low logic level
in the sub-threshold region [4] – [6]. In addition these designs swing by using PMOS as well as NMOS.
require a large number of transistors, resulting in a large area, Complementary pass transistor logic (CPL) uses
NMOS pass transistor logic with CMOS output inverters.
IJ

not suitable for small, low-priced systems.


This paper presents the implementation of Full adder, D Small stack height and internal node low swing are important
Flip-Flop and RAM. Utilizing area and power efficient Gate- features but it suffers from static power consumption due to
the low swing at the gates of the output inverters.
Diffusion-Input (GDI) multiplexers, these topologies are Double pass transistor logic (DPL) uses
characterized by ultra-low power dissipation and small area. complementary transistors to keep full swing operation and
Section II presents different CMOS Logic design reduce the dc power consumption. This eliminates the need for
techniques, their drawbacks. Section III presents the restoration circuitry. One disadvantage of DPL is large area
comparison of Static CMOS and Gate-Diffusion-Input (GDI) due to the presence of PMOS transistors.
technique. Section IV and V presents the implementation of

ISSN: 2230-7818 @ 2011 http://www.ijaest.iserp.org. All rights Reserved. Page 195


Prathyusha Konduri et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES
Vol No. 5, Issue No. 2, 195 - 200

III. CMOS VS GDI Most of these functions are complex (6 -12 transistors) in
A new low power design technique that solves most of the CMOS as well as in PTL implementations but very simple
problems known as Gate-Diffusion-Input (GDI) is proposed. (only 2 transistors per function) in GDI design method.
This technique allows reducing power consumption,
propagation delay, and area of digital circuits. The GDI IV. IMPLEMENTATION OF D FLIP-FLOP
method is based on the simple cell shown in Figure.1. A basic The conventional D Flip-Flop implemented in GDI
GDI cell contains four terminals – G (common gate input of Technique is as shown in Figure.2. This is a positive edge
nMOS and pMOS transistors), P (the outer diffusion node of triggered.
pMOS transistor), N (the outer diffusion node of nMOS
transistor), and D (common diffusion node of both transistors)
[10].

T
Figure 2. Positive edge triggered D Flip-Flop
Figure 1. Basic GDI cell

Table I shows how different logic functions implemented with To reduce power a Double edge triggering is implemented.
GDI cell. ES In Double edge triggering is done on both edges of clock since
they effectively enable a halving of the clock frequency. A
TABLE I. LOGIC FUNCTIONS IMPLEMENTED WITH GDI CELL novel implementation of D Flip-Flop in GDI technique is
shown in Figure.3. It is based on the Master-Slave connection
N P G D Function
of two GDI D Latches. Each latch cell consists of four basic
„0‟ B A A‟B F1 GDI cells [11].
B „1' A A‟+B F2
„1‟ B A A+B OR
B „0‟ A AB AND
C B A A‟B+AC MUX
„0‟ „1‟ A A‟ NOT

GDI enables simpler gates, transistor count and lower


power dissipation in many implementations, as compared with
A
standard CMOS and PTL techniques. Table II shows the
implementations of AND, OR and XOR gates in GDI and
Figure 3. D – Flip flop implementation in GDI technique
CMOS.

TABLE II. AND, OR , XOR GATES IN GDI AND CMOS This D Flip-Flop design reduces power-delay product and
area of circuit but isn‟t always suitable for strong inversion
operation due to the threshold voltage drop, but this is
substantially reduced in sub-threshold operation.
IJ

V. IMPLEMENTATION OF RAM

A memory unit is a collection of storage cells together with


associated circuits needed to transfer information in and out of
the device. Memory cells can be accessed for information
transfer to or from any desired random location and hence the
name random-access memory (RAM) [12].

ISSN: 2230-7818 @ 2011 http://www.ijaest.iserp.org. All rights Reserved. Page 196


Prathyusha Konduri et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES
Vol No. 5, Issue No. 2, 195 - 200

A. Write and Read Operations


The two operations that RAM can perform are the write and
read operations. The write operation specifies a transfer-in
operation and the read signal specifies a transfer-out operation.
On accepting one of these control signals, the internal circuits
inside the memory provide the desired operation. The steps
that must be taken for the purpose of transferring a new word
to be stored into the memory are as follows: [12]
1. Apply the binary address of the desired word to the
address lines.
2. Apply the data bits that must be stored in memory to the
Figure 4. Write cycle
data input lines.
3. Activate the write input.
The memory input will then take the bits from the input data
and store them in the word specified by the address lines.

T
The steps that must be taken for the purpose of transferring a
stored word out of memory are as follows:
1. Apply the binary address of the desired word to the
address lines.
2. Activate the read input.
The memory unit will then take the bits from the word that has
been selected by the address and apply them to the output data
ES
lines. The contents of the selected word do not change after
the read operation; i.e. the word operation is nondestructive
[12].
The memory enable (sometimes called the chip select) is used Figure 5. Read cycle
to enable the particular memory chip in a multichip
implementation of a large memory. When the memory enable
is inactive, the memory chip is not selected and no operation is C. Internal construction
performed. When the memory enable is active, the read/write The internal construction of a random-access memory of m
input determines the operation to be performed [12]. words with n bits per word consists of m x n binary storage
cells and associated decoding circuits for selecting individual
words. The binary storage cell is the basic building block of a
B. Timing Waveforms
memory unit. The equivalent logic of a binary cell that stores
The operation of the memory unit is controlled by an one bit of information is shown in Figure.6 and the block
external device such as a central processing unit (CPU). The diagram in Figure.7 [12].
A
CPU is usually synchronized by its own clock. The memory
however, does not employ an internal clock. Instead, it‟s read
and write operations are specified by control inputs.
The access time of memory is the time required to select a
word and read it. The cycle time of memory is the time
required to complete a write operation. The CPU must provide
the memory control signals in such a way as to synchronize its
internal clocked operations with the read and write operations
of memory. This means the access time and cycle time of the
IJ

memory must be within a time equal to a fixed number of


CPU clock cycles. The memory cycle timing waveforms are
as shown in Figure. 4 and Figure. 5 [12].

Figure 6. Logic diagram of binary storage cell

The storage of the cell is modeled by an SR latch (Figure.7)


with associated gates to form a D latch. A binary storage cell
must be very small in order to be able to pack as many cells as
possible in the area available in the integrated-circuit chip
[12].

ISSN: 2230-7818 @ 2011 http://www.ijaest.iserp.org. All rights Reserved. Page 197


Prathyusha Konduri et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES
Vol No. 5, Issue No. 2, 195 - 200

Figure 7. SR Latch

The binary cell stores one bit in its internal flip-flop. It has
three inputs and one output. The select input enables the cell
for reading or writing and the read/write input determines the
cell operation when it is selected. A 1 in the read/write input
provides the read operation by forming a path from the flip-

T
Figure 9. Architecture of a 4 x 4 RAM
flop to the output terminal. A 0 in the read/write input
provides the write operation by forming a path from the input During the read operation, the four bits of the selected word
terminal to the flip-flop. The flip-flop operates without a clock go through OR gates to the output terminals. During the write
and is similar to an SR latch [12]. operation, the data available in the input lines are transferred
The logical construction of a small RAM is shown in into the four binary cells of the selected word. The binary cells
Figure.9. It consists of 4 words of 4 bits each and has a total of that are not selected are disabled and their previous binary
16 binary cells. Each block labeled BC represents the binary
ES values remain unchanged. When the memory-enable input that
cell with its three inputs and one output. A memory with four goes into the decoder is equal to 0, none of the words are
words needs two address lines. The 2 x 4 decoder with enable selected and the contents of all cells remain unchanged
input is as shown in Figure.8 [12]. regardless of value of the read/write input [12].
Commercial random-access memories may have a capacity
of thousands of words and each word may range from 1 to 64
bits. The logical construction of a large capacity memory
would be a direct extension of the configuration shown here.
A memory with 2k words of n bits per word requires k address
lines that go into a k x 2k decoder [12]. Each one of the
decoder outputs selects one word of n bits for reading or
writing. For low power the RAM is implemented in GDI
technique.

VI. RESULTS
A
Various CMOS logic design techniques have been
presented to reduce power consumption. The GDI D Flip-Flop
has been implemented in 0.18µm technology with the supply
voltage of 1.8V and the simulation results are as shown in
Figure.10.The GDI D Flip-Flop is positive-edge triggered.

Figure 8. 2 x 4 Decoder with enable input


IJ

The two address inputs go through a 2 x 4 decoder to select


one of the four words. The decoder is enabled with the
memory enable input. When the memory enable is 0, all
outputs of the decoder are 0 and none of the memory words
are selected. With the memory enable at 1, one of the four
words is selected, dictated by the value in the two address
lines. Once a word has been selected, the read/write input
determines the operation [12].

Figure 10. Simulation waveforms of Positive edge triggered D Flip Flop

ISSN: 2230-7818 @ 2011 http://www.ijaest.iserp.org. All rights Reserved. Page 198


Prathyusha Konduri et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES
Vol No. 5, Issue No. 2, 195 - 200

Figure.11 shows the waveforms of a double edge


triggered D Flip-Flop implemented in GDI Technique for
reduction in power consumption. Here triggering is done on
both edges of clock.

T
Figure 13. 2 x 4 Decoder with enable input simulation waveform

Figure 11. Simulation waveforms of Double edge triggered D Flip-Flop The binary storage cell simulation waveforms are
shown in Figure.14. The input given is 1011101110 and the
select input is held high which enables the cell for reading or
The Table III shows the results of GDI technique and GDI
writing. The read/write input determines the operation of the
in sub-threshold region in terms of transistor count and power
cell. A „0‟ in read/write provides write operation. A „1‟ in
dissipation implemented in the D flip-flop.
ES read/write provides read operation.
TABLE III
Double edge
Sequential Positive edge
triggered FF in
circuits triggered FF in GDI
GDI
(D Flip-Flop) Technique
Technique

No. of 26 18
transistors

Power 368 µW 151.7µW


dissipation

The implementation of 4 x 4 RAM has been presented and


simulated using mentor graphics in 0.18 µm technology. The
simulation waveforms of SR latch and 2 x 4 Decoder with
enable input is as shown in Figure.11 and Figure 12.
A
Figure 14. Memory cell simulation waveforms

The timing waveforms of the 4 x 4 RAM


implemented in GDI Technique are shown in Figure.15.
IJ

Figure 12. Simulation waveforms of SR Latch

Figure 15. Timing waveforms of 4 x 4 RAM

ISSN: 2230-7818 @ 2011 http://www.ijaest.iserp.org. All rights Reserved. Page 199


Prathyusha Konduri et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES
Vol No. 5, Issue No. 2, 195 - 200

The address inputs are given and the select signal of the REFERENCES
memory cell is held high based on the output of the decoder.
The inputs are given as patterns and read/write signal enables [1] Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic, “Digital
read or write operation. Integrated Circuits- A Design Perspective”,2 nd ed., Prentice Hall of
India Pvt Ltd, New Delhi,2006.
The access time of the proposed technique is calculated to [2] A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, “Low-power
be 1.232ns (shown in Figure.16) with the power dissipation of CMOS digital design”. IEEE J. Solid-State Circuits, vol. 27, pp. 473-
603.52µW whereas in CMOS logic the access time is 484, Apr. 1992.W.-K. Chen, Linear Networks and Systems (Book
style). Belmont, CA: Wadsworth, 1993, pp. 123–135.
1.9291ns with the power dissipation of 719.17µW. [3] A. P. Chandrakasan and R.W. Brodersen, “Minimizing power
consumption in digital CMOS circuits”. Proc. IEEE, vol. 83, pp. 498–
523, Apr. 1995.
[4] H.P. Alstad, S. Aunet, “Three Subthreshold Flip-Flop Cells
Characterized in 90 nm and 65 nm CMOS Technology,” DDECS,
2008.
[5] A. Chavan, G. Dukle, B. Graniello, E. MacDonald, “Robust Ultra-
Low Power Subthreshold Logic Flip-Flop Design for Reconfigurable
Architectures,” ReConFig, 2006.
[6] H. P. Alstad and S. Aunet, "Seven subthreshold flip-flops cells," in

T
Proc. IEEE NorCHIP 2007, Nov. 2007, pp. 1-4.
[7] N. Weste and K. Eshraghian Principles of CMOS digital design.
[8] W. Al-Assadi, A. P. Jayasumana, and Y. K. Malaiya, “Pass-transistor
logic design,” Int. J. Electron., vol. 70, pp. 739–749, 1991.
[9] I. S. Abu-Khater, A. Bellaouar, and M. I. Elmastry, “Circuit techniques
Figure 16. Read and write cycle waveforms for CMOS low-power high-performance multipliers,” IEEE J. Solid-
State Circuits, vol. 31, pp. 1535–1546, Oct. 1996.
[10] A. Morgenshtein, A. Fish, I.A. Wagner, “Gate-Diffusion Input (GDI) –
Table IV shows the comparison results of GDI RAM with A Power Efficient Method for Digital Combinational Circuits,” IEEE
Full Swing and CMOS RAM
ES Trans. VLSI, vol.10, no.5 pp.566-581, October 2002.
[11] A. Morgenstein, A. Fish, I. Wagner, “An Efficient Implementation of
TABLE IV D-Flip-Flop Using the GDI Technique,” ISCAS ‟04, pp. 673-676, May
2004.
RAM GDI Technique [12] M. Morris Mano and Michael D.Ciletti, “Digital Design”.
CMOS Logic
Implementation with Full Swing

Supply voltage 1.8V 1.8V

Technology 0.18µm 0.18µm

No. of transistors 972 1180

Power dissipation 603.52 µW 719.17µW K. Prathyusha completed her B.Tech in Electrical and
Electronics Engineering from Lakireddy Balireddy College of Engineering,
Mylavaram, Andhra Pradesh, India in 2009. She is now pursuing her Master
Access time(ns) 1.232ns 1.9291ns
of Technology (M.Tech) in VLSI Design at VIT University, Vellore, Tamil
Nadu, India. Her interest includes Digital Design, ASIC Design, VLSI
A
Delay (ρs) 522.8ρs 1036.4ρs
Testing, and she did some projects in the area of Low power in VLSI Design.
She is an active participant in technical events and presented projects at
VII. CONCLUSION national level.

In this paper different CMOS logic design families has been


reviewed and evaluated based on the performance metrics like
area, power, delay and transistor count. But the proposed
techniques have the disadvantages of transistor count, delay
and power dissipation. So a new technique, Gate-Diffusion-
IJ

Input (GDI) technique has been adopted for reducing the


transistor count with full swing. The GDI technique has been Magesh Kannan Parthasarathy was born in India,
implemented in D Flip-Flop and the comparison results have Tamilnadu in 1976. He received the B.E Degree in Electronics and
been shown. Communication Engineering, Govt College Engineering, Salem, Tamilnadu,
from the University of Madras, Chennai, in July 1997 and M.Tech Degree in
The implementation of 4 x 4 RAM has been presented in VLSI Design from SASTRA University, Tanjore, Tamilnadu, in 2005. During
GDI technique and can be extended to higher configurations. 2005-2009 he has been working for SASTRA University, Tanjore, Tamilnadu.
The future research activities may include integration of the Since 2009, he has been working for VIT University, Vellore, Tamilnadu. He
has published few papers in International Journals and International
proposed D Flip-Flop and RAM in complex digital systems, Conferences. His research interests include RF IC Design for Bio-Medical
combining sequential and combinational logic. applications and Robotics, Analog & Mixed Signal IC Design, High-Speed
and Low-Power Digital Integrated Circuits & Digital Signal Processor Design.

ISSN: 2230-7818 @ 2011 http://www.ijaest.iserp.org. All rights Reserved. Page 200

Das könnte Ihnen auch gefallen