Sie sind auf Seite 1von 89




Submitted by

Vikas Chandel

Registration no- 3060070105

Program- ECE (dual)

Section- C67T2

Under the guidance of

Faculty coordinator Industrial Coordinator

Mr. Vikramjit Singh Miss. Shivani Girdhar

Department of Electronics and Communication


Lovely Professional University, Phagwada.

July-December 2010

1 |Page

I hereby declare that the project work entitled “process learning of manufacturing of discrete
devices (transistors)” is an authentic record of my own work carried out at CDIL Semiconductors,
Mohali as requirements of Industry Internship project for the award of degree ECE, Lovely
Professional University Phagwara, under the guidance of Miss Shivani Girdhar (Industry
coordinator) and Mr. Vikamjit Singh (Faculty coordinator), during July to December 2010.

(Signature of student)

Name- Vikas Chandel

Registration no- 3060070105

Dated: ___________________________

I Certified That The Above Statement Made By The Student Is Correct To The Best Of Our
Knowledge And Belief.

Mr. Amarjit Singh

(Senior Engineer) Signature………………….


2 |Page

I would like to express my gratitude to all those who gave me the possibility to complete this
training. I want to thank the HR Department CDIL of Mohali for giving me permission to commence
this training in their plant. I have furthermore to thank the Senior Engineer, Mr. Amarjit Singh who
guided me with his remarkable knowledge and experience.

I am deeply indebted to my mentor Miss Shivani Gridhar and Mr. Amarjit Singh(Senior Egineer) for
their help, stimulating suggestions and support in completion of my project work.

I would like to give my special thanks to my university and department of electronics for giving me
an opportunity to do six months industrial training.

I am also grateful to my fellow trainee and all the operators and technicians for cooperation and help.

3 |Page

Topics Page no.

1. Company profile ………………………………………………………… 6

1.1 Organization overview ………………………………………………… 6

1.2 Mohali plant …………………………………………………………. 6

1.3 Group Companies …………………………………………………….. 7
1.4 CDIL’s Excellences …………………………………………………… 8

1.5 CDIL Facilities …………………………………………………….. 8

1.6 Product range …………………………………………………….. 9
2. Company structure ……………………………………………………. 11
2.1 Various departments and their functioning ………………………… 11
3. Transistor manufacturing process …………………………………………. 19
3.1 Introduction to transistor ………………………………………........... 19
3.2 Importance of transistor ……………………………………………..... 20
3.3 Usages of transistor …………………………………………………….. 20
3.4 Advantages …………………………………………………………….. 22
3.5 Limitations ……………………………………………………….......... 22
3.6 Categories of transistors ………………………………………………..... 23
3.7 Bipolar transistor ………………………………………………………… 24
3.8 FET …………………………………………………………………… 25
4. Wafer fabrication …………………………………………………………. … 27
4.1 Photolithography ……………………………………………………… 28
4.2 Photoresists …………………………………………………………. 29
4.3 Photolithography pattern ………………………………………………… 29
4.4 Etching ……………………………………………………… 30
4.5 Wet chemical etching …………………………………………………… 31
4.6 Examples ……………………………………………………………….. 32
4.7 Plasma etching ………………………………………………………….. 33

4 |Page
4.8 Diffusion and ion-implantation …………………………………………… 31
4.9 Comparison of diffusion and ion-implantation …………………………….. 32
5. Assembly processes of transistor ………………………………………………….. 33
5.1 Wafer dicing ………………………………………………………………….. 34
5.2 Die bonding ………………………………………………………………….. 37
5.3 Wire bonding ……………………………………………………………….. 40
5.4 Moulding ………………………………………………………………….. 42
5.5 Dip- tining ………………………………………………………………. 43
6. Testing …………………………………………………………… ……………. 45
6.1 Testing procedure of to-92 transistor …………………………………….. 46
6.2 Testing procedure of to-126 transistor ……………………………………. 47
6.3 Testing PARAMETERS …………………………………………………. 48
6.4 Manual testing …………………………………………………….. 49
6.5 Profile projector ………………………………………………………. 50
6.6 Machine used in testing ……………………………………………. ……. 50
6.7 Concept of forcing and sensing …………………………………….. ………. 50
6.8 Introduction to tester ………………………………………………. ………. 51
6.9 Description of system software ………………………………………. ….. 60
6.10 Characteristics of transistor’s parameters …………………………… ….. 71
6.11 Rejection in testing ……………………………………………………. 71
6.12 Transistor specification ………………………………………………… 72
6.13Test options ………………………………………………………………. 74
7. Marking ……………………………………………………………. ………. …. 77
7.1 Tape and tube packing ………………………………………………. …. 80
7.2 Taping machine …………………………………………………………… 82
8. Shorting …………………………………………………………………… . 84
9. Finish good store …………………………………………………. …………. 85
10 Summary of training ………………………………………………………… 86
11. Bibliography ……………………………………………………… ……… . 87

5 |Page
1. Company profile


Continental Device India Limited (CDIL) is proud to have pioneered the manufacture of Discrete
Semiconductor Devices in India, way back in 1964.CDIL is one of the leaders in the Indian
electronics sector, dedicated to the Development, Manufacture, Marketing, including International
marketing of a wide range of electronic components.

The product range includes Semiconductors, Sub-Assemblies and Modules, digital

Electronics etc.
CDIL pioneered the manufacture of Silicon Transistors and Diodes in India. The plants located at
New Delhi (Head Office), Mohali and Faridabad is equipped with the state-of-the-art manufacturing
facilities and computerized Quality Control equipment
Relentless stress on quality with “Build it right the first time” is the company’s guiding motto.
Organization is committed to the Total Quality Management (TQM) concept where the organization
emphasis of every employee, starting from top management, is on Customer Delight.
The Company was the first Electronic Components Manufacturer in India to have received the ISO
9001 certification (in 1992) and the IECQ certification (in 1991).CDIL Mohali gets its inspiration
and guidance from the New Delhi unit to commit to the concept of TQM (Total Quality
Management) where the emphasis of every employee is on customer’s delight.


The Mohali unit holds pride of being a part of CDIL group of companies with the Flag-ship company
Continental Device India Ltd. (CDIL) being located at New Delhi. The Mohali unit was earlier
located in Chandigarh. Commercial production at this base started in the year of 1977.The whole unit
was shifted to Mohali in the year of 2000 and the commercial production started on January 25,
2001.CDIL Mohali currently gets its orders from CDIL-New Delhi, to manufacture or to design,
develop and manufacture discrete semiconductors. The Human Resource Department is highly
efficient in maintaining coordination and control among all the sections.
CDIL Mohali was honored with the prestigious award for excellent in TQM. The company is making
serious efforts to implement 5'S. In Oct 2007, ISO-9001:2000 extended the certification for CDIL

6 |Page
Mohali for the next three years. The company is now preparing for ISO-TS: 16949 certification. The
company has received many awards in the field of productivity, export and overall excellence in the
field of semiconductors.

1.3 Group companies

1) CDIL(HK)Ltd.(HongKong)

For enhanced sales and logistic support close to CDIL’s customers in S E Asia, China as well as
other international customer locations, CDIL (HK) Ltd., has been set-up. Sales and Warehousing
activities are undertaken. In addition to New Delhi, shipments can be effected from Hong Kong per
customer preference and logistic advantage


A manufacturer of Wire Wound Components, Laminated Transformers, Ferrite

Transformers/Toroids, Current transformers and Reed Relays. Delta Electronics also provides
Quality Customized Solutions, undertaking design and development of customer specials for
applications ranging from miniature Toys to Telecom and Medical Equipment/Instruments.

CDIL has bagged numerous awards and received recognition from the industry and Government
bodies for excellence in production, Research and Development, Quality, Valued Partner / Best
Vendor, Export Performance, Safety. A short selection of the Awards and Recognition are listed:


ELCINA award for Excellence in Quality for the years 1999 -2000, 2000 -2001.

ELCINA award for Outstanding Export Performance for the year 2000 - 2001.

SONY INDIA Award for "Quality" for the year 1999-2000.

BHARTI TELECOM Award for "Vendor Appreciation" for the year 1998-99.

Crompton Greaves Award for "Valued Vendor" for the year 1998-99.

Rajiv Gandhi National Quality Award, 1998 in the field of Electrical & Electronic Industry.

SONY INDIA Award for Quality for the year 1998-99.

The ESC Special Award for "Excellence in Exports" for Electronic Components under the category
Establishing Indian Brand in Foreign Markets, for 1997-98.
7 |Page
The Government of National Capital Territory of Delhi State Award for Export Excellence for
the year 1996-97 under the category Manufacturing Exporters (Electronics).

BHARTI TELECOM Award for "Best Vendor" for the year 1996-97.

The ESC Special Award for Excellence in Exports under the category Innovation of new product in
the field of electronic components in 1996.

The ELCINA Award for "R&D" in 1996.

Institute of Directors award for "Quality" in 1993.


CDIL has a completely vertically integrated Semiconductors Manufacturing Facilities with over
30,000 sq.meters of clean room area. This includes wafer fabrication to final testing with a high level
of automation, manufacturing a comprehensive range of Transistors, Diodes, Rectifier Diodes,
Bridges, Linear Voltage Regulators, Schottky Barrier Rectifiers, Thyristors and suppliers to
OEM of Dice/Diffused Silicon Wafers (4"), manufactured in a wide variety of conventional leaded
insertion mount and surface mount packages.

a) Over 30,000 sq meters of environmentally controlled clean room area devoted to

manufacturing semiconductor devices.

b) Engineering and technical resource group of around 300 people totally committed to the
highest standardsofquality.

c) A captive wafer fabrication facility providing total quality control and ownership of the

d) An in-house R&D facility with many developments and new processes to its credit.

e) Capability of processing a comprehensive range of discrete components.

f) In-house wafer fabrication facility gives CDIL an advantage to cater to specific customer

g) Quick turnaround on account of a completely integrated manufacturing facility, from wafer

fabrication to assembly to test.

8 |Page
h) State of the art manufacturing facility for the manufacture of semiconductor devices with the
use of state-of-art equipment and machinery from industry leaders in Japan, Switzerland,
USA, Germany etc

i) An eco-sustaining production system under an enlightened Environment Management Policy.

j) A technically qualified team of people to respond to customer requirements globally.


Conventional Products

Dice/Chips - Diffused Silicon Wafers for Transistors

Type : Small Signal Transistors, Power Transistors and Darlington Transistors in both
NPN and PNP.

Technology : Silicon Planar Bipolar

Passivation : Si3N4

Wafer Size : 4" wafers with primary flat

Die Sizes : 14 x 14 mil2., 16 x 16 mil2., 20 x 20 mil2., 24 x 24 mil2., 26 x 26 mil2., 30 x 30

(typical) mil2.,40 x 40 mil2., 60 x 60 mil2., 70 x 70 mil2., 80 x 80 mil2., 100 x 100 mil2., 112
x 112 mil2.


1. TO-92.
Small signal transistors,

Power Dissipation 0.1 - 0.9 W

Voltage Rating 800 Volts

9 |Page
Current Rating 6 Amperes

2. TO-126
Power transistors,

Power Dissipation 36 - 40 W

Voltage Rating 400 Volts

Current Rating 4 Amperes

3. TO-220 Medium power transistor,

Power Dissipation 50 - 130 W

Voltage Rating 1000 Volts

Current Rating 64 Amperes

4. TO-247(3L) High power transistor,

Dissipation175 - 310 W

Rating 1200 Volts

Current Rating 75 Amperes

Metallization : Front side metallization aluminum (Al) and back side metallization gold (Au) for
eutectic die attach and wire bondable type assembly.

Probing : 100% electrically probed with bad dice inked.


10 | P a g e
2.1 Description of various departments of CDIL organisation










X. DTA(Domestic Traffic Area)

XI. EHTP(European Hardware Technology Park)



I. Department: PERSONNEL

Responsibility: This department is responsible for checking routine attendance of current employees,
recruiting new employees, joining formalities completion, organizing training programme needed for
employee benefit etc.

II. Department: PURCHASE

Responsibility: This department is responsible for all the necessary purchase required in any of the
department. All the requests (indents) for purchase are made online & approval is also online. Hence paper
work is minimised. After approval from higher authorities the department makes the purchase. First the
material is brought at GIN (Goods inward note) & is sent to concerned person. If the material required is
found OK then it is accepted & otherwise sent back on GON (Goods outward note).

III. Department: ACCOUNTS

11 | P a g e
Responsibility: This department deals with all money matters as opening of salary A/C for employees,
claiming of tour bills & other money claims whichever applicable.

IV. Department: EXCISE

Responsibility: This department is responsible for checking if there is any need of excise duty to be paid on
material, which is being dispatched. Basically, Excise duty is to be paid when any material is manufactured
for purpose of direct sales & it is 16% of met value at which material is to be sold. But if all the manufactured
material is to be exported then no excise duty is to be paid.


Responsibility: This department is responsible for all the data processing being done, maintenance of
computers, networking of all the computers at various departments. There are two servers for this purpose:
Data Server, Email Server.

Data Server: This server is used for computerisation & networking of all the departments.

Email Server:

 This Sever is used for sending Inter office & Intra office messages, data etc.
 It is also used for sending Email, Net surfing etc.

VI. Department: QUALITY
Responsibilities: Quality department is responsible for maintaining the quality management systems that
conforms to the ISO 9001:2000 standards. Hence improving the quality of material manufactured. As quality
is best way to crush competition, So quality tests are performed on regular bases during work in progress &
after the process is complete. A specified Quality control procedure is followed for quality check from
incoming material to final dispatch.
6.1 CDIL Quality Policy

Continental Device India Limited is committed to provide Semiconductor Devices and Solutions by
Delighting its Customers by understanding, meeting and exceeding their expectations. Institutionalizing
Continual Improvement through Quality Management System in all work processes. Looking after the Safety
of Employees and Product Safety Throughout the organization. Quality is not just another goal; it is our basic
strategy for survival and future growth.

CDIL is committed to providing high quality semiconductors to its customers. Device reliability is thoroughly
monitored through a wide variety of tests conducted during the various stages of product manufacture. The
battery of tests provides valuable data on defect trends and product anomalies. A system of 'Failure Analysis'
and 'Corrective Action' is in place and rigidly implemented.

12 | P a g e
At CDIL, quality and reliability are built into the product by rigorous control of all
operations encompassing design through customer application support.
6.2 Quality tests are divided into three broad categories:

1) IQC – Incoming Quality Check

Quality control is responsible to carry out inspection of all incoming material, operation supplies used in
production. Only QC qualified material shall be used in production.

2) IPQC – In process Quality Check

In process inspection shall be carried by QC as per Quality plan issued by them

3) QA – Quality Assurance.
Final inspection testing shall be carried out as per the procedures established by QC. Only material that meets
the requirements and qualified by QC, will be shipped to the customer.

Apart from this, QC has to ensure that all the test and measuring instruments are calibrated. The Equipment
Maintenance Head maintains list of test and measuring instruments along with calibration status.


Objective: Main objective of engineering department is to improve the production & quality of material at
reduced cost.

a) Whenever a new device is to be prepared process control sheet (PCS) is prepared & is forwarded to
production department. PCS contain all the information about the machine setup & processes
involved in production of the device.

b) Along with PCS, work instruction is also prepared. Work instructions contain all the specification &
timings required at each setup & how the test is to be performed at various stages of production.

c) After getting reliability reports production is started & if there is some breakdown of machine or some
profile is to be changed then an Engineering Change Note (ECN) is prepared for required change
needed for the production of device. ECN is sent to higher authorities after getting it approved from
Production & Quality department.


13 | P a g e
Objective: Production Planning means what to make & when to make. But it depends on customer
requirement. Actually PPC Delhi deals with all the Production planning & dispatch of raw material.
Production Plan is sent on weekly basis.


a) This department is responsible for forwarding production plan along with special specification of the
material if needed. Orders are received from Delhi Unit.
b) On every morning the daily production report, traveller wise report, Chip stock report & work in
progress reports are sent to Delhi.
c) Various monthly & weekly reports are also sent to Delhi & week starts on every Tuesday.
d) This department also supplies Raw material to Production Department.


Various Sections in Manufacturing are as follows:

a) TO – 92 (DB + WB)
b) TO – 126 (DB + WB)
c) TO – 220 (DB + WB)
d) To-247 (DB + WB)
e) Moulding
f) Dip tin, & cleaning
g) Testing + PC

Responsibilities: This department is responsible for production of transistors of TO – 92, TO – 126, TO –220

Production of TO – 92, TO-126 & TO-220:

In production line basically two processes are there:

 Die Bond
 Wire Bond

1) Die Bond:

Pick & place robotic arm is used to pick chip from the wafer & then place it on the lead frame. In this M/C the

14 | P a g e
point to be monitored is temperature settings at which bonding occurs & timing consideration for pick &
place. Usually the temperature of melting of mixture of Gold & Silver is low than the melting temperature of
Individual of both. The bond formed is EUTECTIC. Machines used are of ESEC 2005. Mixture of Nitrogen
& Hydrogen gas is used to avoid the oxidation of copper lead frame, which may oxidize in presence of heat &

2) Wire Bond:

In this process a gold wire is used to connect the chip placed on lead frame during Die Bond process with the
Emitter & Base of transistor. Machines used are of ASM AB 308A & 309.Nitrogen gas is used to remove
fumes produced as a result of heating necessary for wire bonding. Since if fumes are there video display is not
possible. After Wire Bond process the material is handed over to Moulding / Dip Tin section (as required) for
further processing.

3) MOULDING (for TO-92, TO-220& TO-126):

In moulding section the lead frame is fitted in Epoxy material. There are seven moulding machines. Following
process is followed in moulding section.

1) Loading of epoxy material in Ultrasonic Oven.

2) Loading of Lead frames for pre heating.
3) Loading of pre heated epoxy material & lead frames on moulding machine.


1) After moulding, the moulded material is kept in oven for 7 hours & at temperature of 155-175oC for
2) Deoxidisation in NaOH solution for 5 minutes and then water wash.
3) Dambar cutting.
4) Dip Solder & subsequent washing in hot surf water, hot water,raw water, demonized water & then in
Isopropyl alcohol. The temperature of hot water is 50 – 70 0C & wash time is one minute.

5) Drying in Oven.
6) Bottom Cutting
7) Visual Sorting.

15 | P a g e

In CDIL Mohali testing of only TO-126 & TO-92 is done. Three machines are for TO-92 testing & one
machine is for TO-126 testing. Testing may be 100% or 200% depending on customer requirement.

Regarding machines of testing, each machine is having one tester and two handlers. Program setting is done in
tester. Tester sends all controlling signals to handler. Thus tester acts as master & handler as slave. Since each
device has different characteristics & specifications thus separate program is made for every device depending
on its data sheet and other special requirements from customer side. Every device is tested for both data sheet
specifications & internal specifications.

Some of data sheet specifications are as follows

1) Absolute Maximum Ratings

2) Thermal Resistance
3) Dynamic Characteristics
4) Electrical Specifications
5) Pulse Test
6) Switching Characteristics
Some of internal specifications are as follows
• Die Attach Test
• Wire Bond Test

Internal specification tests are performed just to check the quality of tested devices and then choose
the best quality device.
Process of production completes after testing & material is dispatched to NRN. for further processing
( Marking & Final packing etc.


Responsibilities: Maintenance department deals with all the maintenance of various equipments being used.
Following are types of maintenance carried out:

a) Breakdown Maintenance
b) Preventive Maintenance
c) Proactive Maintenance
d) Schedule Maintenance (Overall Maintenance)
e) Calibration

16 | P a g e
EQUIPMENT MAINTENANCE – ‘Equipment Maintenance’ refers to those activities that are required to
keep the equipment operating so that it continues to meet the specifications.

1. Corrective Maintenance- It is carried out when equipment fails or does not work satisfactorily.

2. Preventive Maintenance- It is carried out to reduce the likelihood of failure to the minimum.

3. Contract out Maintenance- In this type of maintenance, contract terms are agreed upon by the supplier of
the equipment and user’ and may include both corrective and preventive maintenance.

Planning is required for routine maintenance activities to prevent deterioration, to measure deterioration by
inspection and measurement and to restore equipment to optimum performance levels by carrying out repairs
and maintenance. While doing routine maintenance it is necessary to inspect the equipment, test it and repair
it if required. Past history of the equipment in the form of records should be checked to diagnose
deterioration; records themselves should be verified for maintainability and updating according to the activity.
Procedures and criteria’s should be acted upon for routine maintenance. Test standards should be verified for
validity. Repair and maintenance standards and maintenance plans should be upgraded.

Goals of equipment maintenance

a) Zero Breakdown
b) Zero Defects
c) Increase Outputs (Production, Quality, Delivery, Morale, Safety, Cost)
d) Decrease Inputs (Man, Material, Machine, Money)

The basic intention is to keep the machines in good working conditions and to detect potential problems
before they generate breakdowns. It can only be successful with total employee participation and teamwork.

2) Preventive maintenance
Preventive maintenance is the periodic inspection to detect conditions that might cause breakdowns,
production stoppages or detrimental loss of function combined with maintenance to eliminate,
control or reverse such conditions in their early stages. It is preventive medicines for the equipment.
In due course of the preventive maintenance, we must ensure following common things for all

a) Standards for measurements of critical parts e.g. play in the bearings to be crosschecked using
standard zigs, resistance value against critical presets on the machines to be verified to prevent the
sudden losses.

17 | P a g e
b) Through cleaning and lubrication of parts e.g. proper cleaning of the vacuum solenoids plays an
important role at die bond machine to prevent minor losses. Lubrication of the lead screw at wire
bond helps us to reduce the setting times of the elevators on the machine.
c) Maintenance Techniques and skills – Complete process of preventive maintenance can be divided into
the small group activities among the different skilled persons to make it effective.
d) Check procurement and work arrangements– Hard to get spare parts and works to be done by outside
manufactures and contractors. Maintenance team should make details of the machine along with the
production considering the past history of the equipment and the stoppages. .
e) Determine work to be required – The most important task in preparing maintenance plans is
identifying all the jobs to be performed. This list must be revised annually. Required work may
include breakdown records, work orders received from the shop flour or salty also.
f) Select work to be done – Rank work in the order of its importance and establish priorities.
g) Estimate work schedule, times, costs and intervals – Use the annual production plans and equipment
performance bench marks to estimate the number of shutdown days and the time required for the
maintenance work and confirm these figure against the budget. This is the most elaborated way of
performing the PM schedule with the control inputs.

XI. Department: FACILITIES

Responsibility: To provide basic utilities e.g. Water, Electricity, Specified atmospheric condition to carry out
smooth production. Facilities department is responsible to ensure that proper cleanliness is maintained. This
includes humidity level, temperature and dust level.

Following equipment are used to provide basic utilities to the plant:

 Step Down Transformer 11KV/415V

 Oil Circuit Breaker 11KV,400A
 LT Distribution Panel
 DG Set for back up Supply 550KVA
 UPS to avoid interruption of Supply 75 KVA
 DI Water Plant 4.5KL/hr
 Gas Supply Lines N2 & N2 + H2 (80 + 20 & 92 + 8)
 Air Handling Unit 160 TR
 Air Conditioning Unit
 And various Pumps & Dryers

18 | P a g e

To make discrete components, below are the three major areas:

Wafer Assembly Testing and

fabrication Finish Good

In Step-1, raw silicon is doped to form the junction. Other processes like diffusion, masking, metal
sintering are used to form the components.

The processed wafers are passed for assembly to make it useable in the required application.

In assembly area, die bonding, wire bonding and molding are used to make a transistor discrete

Finally, in testing area, the transistor undergoes final testing, marking and packing to final customer
end user.

Before describing about manufacturing processes of transistors, I would like to explain a brief
introduction of transistors and its categories.


In electronics, a transistor is a semiconductor device commonly used to amplify or switch electronic

signals. A transistor is made of a solid piece of a semiconductor material, with at least three
terminals for connection to an external circuit. A voltage or current applied to one pair of the
transistor's terminals changes the current flowing through another pair of terminals. Because the
controlled (output) power can be much larger than the controlling (input) power, the transistor
provides amplification of a signal.

The transistor is the fundamental building block of modern electronic devices, and is used in radio,
telephone, computer and other electronic systems. The transistor is often cited as being one of the
greatest achievements in the 20th century, and some consider it one of the most important
technological breakthroughs in human history. Some transistors are packaged individually but most
are found in integrated circuits.

19 | P a g e

The transistor is considered by many to be the greatest invention of the twentieth-century, or as one
of the greatest. It is the key active component in practically all modern electronics. Its importance in
today's society rests on its ability to be mass produced using a highly automated process (fabrication)
that achieves astonishingly low per-transistor costs.

Although several companies each produce over a billion individually-packaged (known as discrete)
transistors every year, the vast majority of transistors produced are in integrated circuits (often
shortened to IC, microchips or simply chips) along with diodes, resistors, capacitors and other
electronic components to produce complete electronic circuits. A logic gate consists of up to about
twenty transistors whereas an advanced microprocessor, as of 2006, can use as many as 1.7 billion
transistors (MOSFETs). About 200 million transistors were built in year 2008 for each man, woman,
and child on Earth.

The transistor's low cost, flexibility and reliability have made it a ubiquitous device. Transistorized
mechatronic circuits have replaced electromechanical devices in controlling appliances and
machinery. It is often easier and cheaper to use a standard microcontroller and write a computer
program to carry out a control function than to design an equivalent mechanical control function.


BJT used as an electronic switch, in grounded-emitter configuration.

The bipolar junction transistor, or BJT, was the first transistor invented, and through the 1970s, was
the most commonly used transistor. Even after MOSFETs became available, the BJT remained the
transistor of choice for many analog circuits such as simple amplifiers because of their greater
linearity and ease of manufacture. Desirable properties of MOSFETs, such as their utility in low-
power devices, usually in the CMOS configuration, allowed them to capture nearly all market share
for digital circuits; more recently MOSFETs have captured most analog and power applications as
well, including modern clocked analog circuits, voltage regulators, amplifiers, power transmitters,
motor drivers, etc.

20 | P a g e
The essential usefulness of a transistor comes from its ability to use a small signal applied between
one pair of its terminals to control a much larger signal at another pair of terminals. This property is
called gain. A transistor can control its output in proportion to the input signal, that is, can act as an
amplifier. Or, the transistor can be used to turn current on or off in a circuit like an electrically
controlled switch, where the amount of current is determined by other circuit elements.

The two types of transistors have slight differences in how they are used in a circuit. A bipolar
transistor has terminals labeled base, collector and emitter. A small current at base terminal (that is,
flowing from the base to the emitter) can control or switch a much larger current between collector
and emitter terminals. For a field-effect transistor, the terminals are labeled gate, source, and drain,
and a voltage at the gate can control a current between source and drain.

Charge will flow between emitter and collector terminals depending on the current in the base. Since
internally the base and emitter connections behave like a semiconductor diode, a voltage drop
develops between base and emitter while the base current exists. The size of this voltage depends on
the material the transistor is made from, and is referred to as VBE.

a) Transistor as a switch

Transistors are commonly used as electronic switches, for both high power applications including
switched-mode power supplies and low power applications such as logic gates.

It can be seen that once the base voltage reaches a certain level, the current will no longer increase
with increasing VBE and the output will be held at a fixed voltage. The transistor is then said to be
saturated. Hence, values of input voltage can be chosen such that the output is either completely off,
or completely on. The transistor is acting as a switch, and this type of operation is common in digital
circuits where only "on" and "off" values are relevant.

b) Transistor as an amplifier

The common emitter amplifier is designed so that a small change in voltage in (Vin) changes the
small current through the base of the transistor and the transistor's current amplification combined
with the properties of the circuit mean that small swings in Vin produce large changes in Vout.

21 | P a g e
It is important that the operating parameters of the transistor are chosen and the circuit designed such
that as far as possible the transistor operates within a linear portion, otherwise the output signal will
suffer distortion.

Various configurations of single transistor amplifier are possible, with some providing current gain,
some voltage gain, and some both.

From mobile phones to televisions, vast numbers of products include amplifiers for sound
reproduction, radio transmission, and signal processing. The first discrete transistor audio amplifiers
barely supplied a few hundred mill watts, but power and audio fidelity gradually increased as better
transistors became available and amplifier architecture evolved.

Modern transistor audio amplifiers of up to a few hundred watts are common and relatively

Some musical instrument amplifier manufacturers mix transistors and vacuum tubes in the same
circuit, as some believe tubes have a distinctive sound.


The key advantages that have allowed transistors to replace their vacuum tube predecessors in most
applications are:

1) Small size and minimal weight, allowing the development of miniaturized electronic devices.
2) Highly automated manufacturing processes, resulting in low per-unit cost.
3) Lower possible operating voltages, making transistors suitable for small, battery-powered
4) No warm-up period for cathode heaters required after power application.
5) Lower power dissipation and generally greater energy efficiency.
6) Higher reliability and greater physical ruggedness.
7) Extremely long life. Some transistorized devices have been in service for more than 30 years.
8) Complementary devices available, facilitating the design of complementary-symmetry
circuits, something not possible with vacuum tubes.
9) Insensitivity to mechanical shock and vibration, thus avoiding the problem of micro phonics
in audio applications.

22 | P a g e

1) Silicon transistors do not operate at voltages higher than about 1,000 volts (SiC devices can
be operated as high as 3,000 volts.
2) High power, high frequency operation, such as used in over-the-air television broadcasting, is
better achieved in electron tubes due to improved electron mobility in a vacuum.
3) On average, a higher degree of amplification linearity can be achieved in electron tubes as
compared to equivalent solid state devices, a characteristic that may be important in high
fidelity audio reproduction.
4) Silicon transistors are much more sensitive than electron tubes to an electromagnetic pulse,
such as generated by a nuclear explosion.

3.6 Transistors are categorized by:

1) Semiconductor material : germanium, silicon, gallium arsenide, silicon carbide, etc.

2) Structure: BJT, JFET, IGFET (MOSFET), IGBT, "other types"
3) Polarity: NPN, PNP (BJTs); N-channel, P-channel (FETs)
4) Maximum power rating: low, medium, high
5) Maximum operating frequency: low, medium, high, radio frequency (RF), microwave (The
maximum effective frequency of a transistor is denoted by the term fT, an abbreviation for
"frequency of transition". The frequency of transition is the frequency at which the transistor
yields unity gain).
6) Application: switch, general purpose, audio, high voltage, super-beta, matched pair
7) Physical packaging: through hole metal, through hole plastic, surface mount, Metal Can,
power modules
8) Amplification factor hfe (transistor beta)

Thus, a particular transistor may be described as: silicon, surface mount, BJT, NPN, low power, high
frequency switch.

The 'BC' letters in a common transistor name like BC547B means:

Prefix class Usage

BC Small signal transistor ("all round")

23 | P a g e
BF High frequency, many MHz

BD Withstands higher current and power

BA Germanium


BJT was the first type of transistor to be mass-produced. Bipolar transistors are so named because
they conduct by using both majority and minority carriers. The three terminals of the BJT are named
emitter, base and collector. The BJT consists of two p-n junction: the base/emitter junction and
base/collector junction. (However you cannot create a BJT by wiring together 2 diodes). "The [BJT]
is useful in amplifiers because the currents at the emitter and collector are controllable by the
relatively small base current. In an NPN transistor operating in the active region, the emitter-base
junction is forward biased (electrons and holes recombine at the junction), and electrons are injected
into the base region. Because the base is narrow, most of these electrons will diffuse into the reverse-
biased (electrons and holes are formed at, and move away from the junction) base-collector junction
and be swept into the collector; perhaps one-hundredth of the electrons will recombine in the base,
which is the dominant mechanism in the base current. By controlling the number of electrons that
can leave the base, the number of electrons entering the collector can be controlled. Collector current
is approximately β (common-emitter current gain) times the base current. It is typically greater than
100 for small-signal transistors but can be smaller in transistors designed for high-power

24 | P a g e
Bipolar transistors can be made to conduct by exposure to light, since absorption of photons in the
base region generates a photocurrent that acts as a base current; the collector current is
approximately beta times the photocurrent. Devices designed for this purpose have a transparent
window in the package and are called phototransistors.


The field-effect transistor (FET), sometimes called a unipolar transistor, uses either electron (in N-
channel FET) or holes (in P-channel FET) for conduction. The four terminals of the FET are named
source, gate, drain, and body (substrate). On most FETs, the body is connected to the source inside
the package, and this will be assumed for the following description.

In FETs, the drain-to-source current flows via a conducting channel that connects the source region
to the drain region. The conductivity is varied by the electric field that is produced when a voltage is
applied between the gate and source terminals; hence the current flowing between the drain and
source is controlled by the voltage applied between the gate and source. As the gate–source voltage
(Vgs) is increased, the drain–source current (Ids) increases exponentially for Vgs below threshold,
25 | P a g e
and then at roughly quadratic rate where VT is the threshold voltage at which drain current begins) in
the "space-charge-limited" region above threshold. For low noise at narrow bandwidth the higher
input resistance of the FET is advantageous.

FETs are divided into two families: junction FET (JFET) and insulated gate FET (IGFET). The
IGFET is more commonly known as metal–oxide–semiconductor FET (MOSFET), from their
original construction as a layer of metal (the gate), a layer of oxide (the insulation), and a layer of
semiconductor. Unlike IGFETs, the JFET gate forms a PN diode with the channel which lies
between the source and drain. Functionally, this makes the N-channel JFET the solid state equivalent
of the vacuum tube triode which, similarly, forms a diode between its grid and cathode. Also, devices
operate in the depletion mode, they both have a high input impedance, and they both conduct current
under the control of an input voltage.

Metal–semiconductor FETs (MESFETs) are JFETs in which the reverse biased PN junction is
replaced by a metal–semiconductor Scotty-junction. These, and the HEMTs (high electron mobility
transistors, or HFETs), in which a two-dimensional electron gas with very high carrier mobility is
used for charge transport, are especially suitable for use at very high frequencies (microwave
frequencies; several GHz).

Unlike bipolar transistors, FETs do not inherently amplify a photocurrent. Nevertheless, there are
ways to use them, especially JFETs, as light-sensitive devices, by exploiting the photocurrents in
channel–gate or channel–body junctions.

FETs are further divided into depletion-mode and enhancement-mode types, depending on whether
the channel is turned on or off with zero gate-to-source voltage. For enhancement mode, the channel
is off at zero bias, and a gate potential can "enhance" the conduction. For depletion mode, the
channel is on at zero bias, and a gate potential (of the opposite polarity) can "deplete" the channel,
reducing conduction. For either mode, a more positive gate voltage corresponds to a higher current
for N-channel devices and a lower current for P-channel devices. Nearly all JFETs are depletion-
mode as the diode junctions would forward bias and conduct if they were enhancement mode
devices; most IGFETs are enhancement-mode types.

26 | P a g e

Wafer fabrication generally refers to the process of

building integrated circuits on silicon wafers. Prior to
wafer fabrication, the raw silicon wafers to be used for
this purpose are first produced from very pure silicon
ingots. Picture no. 1 shows silicon wafer.

Following Processes are used in fabrication of Transistor


1. Crystal growth technique

2. Pattern generation and photo masking
3. Photolithography
4. Formation of capital layer
5. Formation of insulating layer or thermal oxidation
6. Metallization and interconnections
7. Etching Process

A wafer is a thin slice of semiconductor material, such as silicon crystal, used in the fabrication of
integrated circuits and other micro devices. The wafer serves as the substrate for micro electronics
devices built in and over the wafer and undergoes many micro fabrication process steps such as
doping or ion implantation, etching, deposition of various materials, and photolithography

Wafers are formed of highly pure (99.9999% purity),nearly defect-free single crystalline material
.One process for forming crystalline wafers is known as Czochralski growth invented by the Polish
chemist Jan Czochralski. In this process, a cylindrical ingot of high purity monocrystalline silicon is
formed by pulling a seed crystal from a ‘melt’. Dopant impurity atoms such as boron or phosphorus

27 | P a g e
can be added to the molten intrinsic silicon in precise amounts in order to dope the silicon, thus
changing it into n-type or p-type extrinsic silicon.

The ingot is then sliced with a wafer saw (wire saw) and polished to form wafers. The size of wafers
for photovoltaic is 100 – 200 mm square and the thickness is 200 - 300 μm. In the future, 160 μm
will be the standard. Electronics use wafer sizes from 100 - 300mm diameter. (The largest wafer
made has a diameter of 450mm but isn't in production yet).

1. Czochralski Process is a Technique in Making Single-Crystal Silicon

2. A Solid Seed Crystal is Rotated and Slowly Extracted from a Pool of Molten Si
3. Requires Careful Control to Give Crystals Desired Purity and Dimensions
4. The Silicon Cylinder is Known as an Ingot
5. Typical Ingot is About 1 or 2 Meters in Length
6. Can be Sliced into Hundreds of Smaller Circular Pieces Called Wafers
7. Each Wafer Yields Hundreds or Thousands of Integrated Circuits

4.1 Photolithography

Photolithography is a technique that is used to define the shape of micro-machined structures on a

wafer. The first step in the photolithography process is to develop a mask, which will be typically be
a chromium pattern on a glass plate. Next, the wafer is then coated with a polymer which is sensitive
to ultraviolet light called a photoresist. The photoresist is then developed which transfers the pattern
on the mask to the photoresist layer.

4.2 Photolithography Photoresist

There are two basic types of Photoresists Positive and Negative.

a) Positive resists.

Positive resists decomposes ultraviolet light. The resist is exposed with UV light wherever the
underlying material is to be removed. In these resists, exposure to the UV light changes the chemical
structure of the resist so that it becomes more soluble in the developer. The exposed resist is then
washed away by the developer solution, leaving windows of the bare underlying material. The mask,
therefore, contains an exact copy of the pattern which is to remain on the wafer.

28 | P a g e
b) Negative resist

Exposure to the UV light causes the negative resist to become polymerized, and more difficult to
dissolve. Therefore, the negative resist remains on the surface wherever it is exposed, and the
developer solution removes only the unexposed portions. Masks used for negative photoresists,
therefore, contain the inverse (or photographic "negative") of the pattern to be transferred.

4.3 Photolithography Patterning

The last stage of Photolithography is a process called ashing. This process has the exposed wafers
sprayed with a mixture of organic solvents that dissolves portions of the photoresist .

Conventional methods of ashing require an oxygen-plasma ash, often in combination with halogen
gases, to penetrate the crust and remove the photoresist. Usually, the plasma ashing process also
requires a follow-up cleaning with wet-chemicals and acids to remove the residues and non-volatile
contaminants that remain after ashing. Despite this treatment, it is not unusual to repeat the "ash plus
wet-clean" cycle in order to completely remove all photoresist and residues.

4.4 Etching

Etching is the process where unwanted areas of films are removed by either dissolving them in a wet
chemical solution (Wet Etching) or by reacting them with gases in a plasma to form volatile products
(Dry Etching).

Resist protects areas which are to remain. In some cases a hard mask, usually patterned layers of
SiO2 or Si3N4, are used when the etch selectivity to photoresist is low or the etching environment
causes resist to delaminate. This is part of lithography - pattern transfer.

29 | P a g e
4.5 Wet Chemical Etching

Wet etches:

- are in general isotropic (not used to etch features less than ≈ 3 µm)

- achieve high selectivities for most film combinations

- capable of high throughputs

- use comparably cheap equipment

- can have resist adhesion problems

- can etch just about anything

4.6 Example Wet Processes

1. For SiO2 etching

- HF + NH4F+H20 (buffered oxide etch or BOE)

2. For Si3N4

- Hot phosphoric acid: H3PO4 at 180 °C

30 | P a g e
- need to use oxide hard mask

3. Silicon

- Nitric, HF, acetic acids

- HNO3 + HF + CH3COOH + H2O

4. Aluminum

- Acetic, nitric, phosphoric acids at 35-45 °C


4.7 plasma etching

1. Plasma is a partially ionized gas made up of equal parts positively and negatively charged
2. Plasmas are generated by flowing gases through an electric or magnetic field.
3. These fields remove electrons from some of the gas molecules. The liberated electrons are
accelerated, or energized, by the fields.
4. The energetic electrons slam into other gas molecules, liberating more electrons, which are
accelerated and liberate more electrons from gas molecules, thus sustaining the plasma.

4.8 Diffusion and Ion Implantation

WN-Junction Fabrication (Earliest method)

1. Process: Opposite polarity doping atoms are added to molten silicon during the Czochralski
process to create in-grown junctions in the ingot. Repeated counter doping can produce
multiple junctions within the crystal.
2. Disadvantages: Inability to produce differently doped areas in different parts of the wafer.
The thickness and planarity of grown junctions are difficult to control. Repeated counter
dopings degrade the electrical properties of the silicon.
3. Diffusion

1) A uniformly doped ingot is sliced into wafers.

31 | P a g e
2) An oxide film is then grown on the wafers.
3) The film is patterned and etched using photolithography exposing specific
sections of the silicon.
4) The wafers are then spun with an opposite polarity doping source adhering only to
the exposed areas.
5) The wafers are then heated in a furnace (800-1250 deg.C) to drive the doping
atoms into the silicon.

4. Ion Implantation
1) A particle accelerator is used to accelerate a doping atom so that it can penetrate a
silicon crystal to a depth of several microns
2) Lattice damage to the crystal is then repaired by heating the wafer at a moderate
temperature for a few minutes. This process is called annealing.

4.9 Comparison of Diffusion and Ion Implantation

1) Diffusion is a cheaper and more simplistic method, but can only be performed from the
surface of the wafers. Dopants also diffuse unevenly, and interact with each other altering the
diffusion rate.
2) Ion implantation is more expensive and complex. It does not require high temperatures and
also allows for greater control of dopant concentration and profile. It is an anisotropic process
and therefore does not spread the dopant implant as much as diffusion. This aids in the
manufacture of self-aligned structures which greatly improve the performance of MOS

32 | P a g e

These are following processes used in assembly area of plant.















33 | P a g e
Wafer dicing is the process by which die are separated from a wafer of semiconductor following the
processing of the wafer. The dicing process can be accomplished by scribing and breaking, by
mechanical sawing (normally with a machine called a dicing saw) or by laser cutting. Following the
dicing process the individual silicon chip are encapsulated into chip carriers which are then suitable
for use in building electronic devices such as computers, etc.

During dicing, wafers are typically mounted on dicing tape which has a sticky backing that holds the
wafer on a thin sheet metal frame. Once a wafer has been diced, the pieces left on the dicing tape are
referred to as die, dice or dies. These will be packaged in a suitable package or placed directly on a
printed circuit board substrate as a "bare die". The area that has been cut away are called die streets
which are typically about 75 micrometers (0.003 inch) wide. Once a wafer has been diced, the die
will stay on the dicing tape until they are extracted by die handling equipment, such as a die bonder
or die sorter, further in the electronics assembly process.

The size of the die left on the tape may range from 35 mm (very large) to 0.5 mm square (very
small). The die created may be any shape generated by straight lines, but they are typically
rectangular or square shaped.

1) Semiconductor material used in wafer materials

Si- Silicon

Ge- Germanium

GaP- Gallium Phosphide

GaAs- Gallium Arsenide

InAs- Indium Arsenide

BN- Boron Nitride

GaN- Gallium Nitride

2) Properties of silicon

i. Basic Parameters

34 | P a g e
Energy gap 1.12 eV
Energy separation (EΓL) 4.2 eV
Energy spin-orbital splitting 0.044 eV
Intrinsic carrier concentration 1·1010 cm-3
Intrinsic resistivity 3.2·105Ω·cm
Effective conduction band density of states 3.2·1019 cm-3
Effective valence band density of states 1.8·1019 cm-3

ii. Donors and Acceptors

Ionization energies of shallow donors (eV):

As P Sb
0.054 0.045 0.043

Ionization energies of shallow acceptors (eV):

Al B Ga In
0.072 0.045 0.074 0.157

iii. Temperature Dependences

Temperature dependence of the energy gap

Eg = 1.17 - 4.73·10-4·T2/(T+636) (eV),

where T is temperature in degrees K.

Temperature dependence of the direct band gap EΓ2

EΓ2 = 4.34 - 3.91·10-4·T2/(T+125) (eV)

Intrinsic carrier concentration

ni=(Nc·Nv )1/2·exp(-Eg/(2kBT])

Effective density of states in the conduction band

Nc=4.82·1015·M·(mc/mo)3/2·T3/2 = 4.82·1015·M·(mcd/mo)3/2·T3/2 (cm-3),

Nc=6.2·1015·T3/2 (cm-3),

35 | P a g e
M = 6 is the number of equivalent valleys in the conduction band.
mc = 0.36mo is the effective mass of the density of states in one valley of conduction band.
mcd = 1.18mo is the effective mass of the density of states.

3) Properties of Germanium

i. Basic Parameters

Energy gap 0.661 eV

Energy separation (EΓ1) 0.8 Ev
Energy separation (ΔE>) 0.85 eV
Energy spin-orbital splitting 0.29 eV
Intrinsic carrier concentration 2.0·1013 cm-3
Intrinsic resistivity 46 Ω·cm
Effective conduction band density of states 1.0·1019 cm-3
Effective valence band density of states 5.0·1018 cm-3

ii. Donors and Acceptors

Ionization energies of shallow donors (eV):

As P Sb Bi Li
0.014 0.013 0.010 0.013 0.093

Ionization energies of shallow acceptors (eV):

Al B Ga In Tl
0.011 0.011 0.011 0.012 0.013

iii. Temperature dependences

Temperature dependences of the energy gap:

Eg = 0.742- 4.8·10-4·T2/(T+235) (eV),

where T is temperature in degrees K.

Temperature dependence of the direct band gap EΓ1:

36 | P a g e
EΓ1 = 0.89 - 5.82·10-4·T2/(T+296) (eV),

Effective density of states in the conduction band:

Nc = 4.82·1015·M·[mc/mo]3/2·T3/2 (cm-3), or Nc = 1.98·1015·T3/2 (cm-3)

M = 4 is the number of equivalent valleys in the conduction band,
mc = 0.22mo is the effective mass of the density of states in one valley of the conduction band.


Die Attach (also known as Die Mount or Die Bond) is the process of attachi8ng the silicon chip to
the die pad or die cavity of the support structure (e.g., the lead frame) of the semiconductor package.
In other words the chips diced from a wafer is attached to the centre pad of the substrate called the
die attach pad.

There are two common die attach processes, i.e., Adhesive die attach or Soft solder die attach and
eutectic die attach. Both of these processes use special die attach equipment and die attach tools to
mount the die. Another process of die attach is manual die attach which is done by solder dispenser.

Lead frame before die bond Chip or die attach to lead frame after die bond

1)Brief description of the process

1. This is the process in which chip is attached to the lead frame.

37 | P a g e
2. Three type of bonding processes are used :

a.) Eutectic Bonding -In this, back metal (Gold) and upper silicon layer make a paste at a
temperature of 363degC.The chip is dumped to the collector of lead frame to bond the die.

b.) Solder bonding-In this type, solder is used as a media for bonding. We can see the photo of soft
solder die attach. Following are the inputs required in the machine to make a die bond.
• Furnace-This gives required temperature profile to the media for die attach.

• Gases-N2:H2 provides the inert atmosphere to the furnace to avoid any oxidation.N2 gives
the curtain effect to the zones.

• Air-Compressed air is used for indexing the lead frame.

• Vacuum-This is requires to pick the die from the lead frame.

2) Basic Bonding tools being used are:

(a)Ejector needle-It is used to eject the chip from the mylar.

(b)Rubber Tip/Collet-These precise tools sre used to pick and place the die on the lead frame passing
in the furnace.

Selection of tools is being done as per the chip size.

Basic Quality checks, like die shear test, heat to thermal resistance are being checked in process.
In Die attach process; we can make different type of configurations like Side collector, Center
collector by choosing different type of lead frames. This selection is based on the international
standards for different device names.
This process is carried out on fully automatic bonding machines (Model ESEC,TOSOK),with lead
frame loaded in the magazines. Each machine can achieve 5-6 thousands die bonded units per hour.

38 | P a g e
Basic defects seen after this process are Non-flat chipping, less/excess solder thickness, voids, low
die shear strength etc.

3) Common problems in die attach process: -

a) Die attach voids: - This type of failure occurs during the attachment of chip on
the lead frame with the help of collect. During the attachment of chip if there would be a time gap in
placing the chip at the lead frame then some air bubbles sticks with the solder and voids occur. Only
2-5% voids are tolerable. The voids results in the low shear strength and low thermal conductivity.
Total absence of voids may mean high strength but it may also induce large dies to crack.

b) Solder Shortening: - Due to incorrect die attach material viscosity, incorrect

adhesive dispensation the electrical shortening between exposed metal lines, bond pads, bonds or
wires as a result of adhesive dripping on the surface of the die occurs, which his called solder

c) Bond Lifting : - This occurs often due to the resin bleeding of the die attach material into the
bond pads or lead figure inhibiting good inter-metallic formation.


Wire bonding is the process of providing electrical connection between the silicon chip and the
external leads of the semiconductor device using very fine bonding wires. The wire used in wire
bonding is usually made either of gold (Au) or aluminum (Al), although Cu wires are starting to gain
attention in the semiconductor manufacturing industry. There are two common wire bond processes:
Au ball bonding and Al wedge bonding.

During gold ball bonding, a gold ball is first formed by melting the end of the wire (which is held by
a bonding tool known as a capillary) through electronic flame off (EFO).

39 | P a g e
During aluminum wedge bonding, a clamped wire is brought in contact with the bond pad.
Ultrasonic energy is then applied to the wire for a specific duration while being held down by a
specific amount of force, forming the first wedge bond between the wire and the bond pad. The wire
is then run to the corresponding lead finger, against which it is gain pressed. The second bond is
again formed by applying ultrasonic energy to the wire.

Lead frame after wire bond after wire bond

Brief description of the process

This is the process in which Emitter and Base of chip are connected to the leads of the lead frame.

Two types of bandings are used :

(a)Thermosonic Bonding-In this type, temperature and EFO (Electronic flame off) is used to melt the
wire tip to make the bonding. It is used for Cu and Au wire bonding. It is low temperature process
for which the source of energy for metal welding is a transducer vibrating the bonding tool parallel to
the bonding pad. In this process the wire is threaded through a hole in the wedge. The wedge is
lowered and wire is pressed tightly between the wedge and the bond pad. Normally the first bond is
made to the die and second to the lead frame. This forward bonding is preferred because it is less
susceptible to edge shorts between the die and the wire. After the second bond, wire is cut using a

(b)Ultrasonic Bonding-In this, ultrasonic energy is used to bond the wire. It is used in Al wire
bonding. It combines ultrasonic energy with the ball bonding capillary technique. The process is
similar but in this bonding, the capillary is not heated and lead frame temperatures are maintained
between 100-150. During gold wire bonding a gold ball is first formed by melting the end of the
wire, which is held by a bonding tool known as a ‘capillary’.

40 | P a g e
Different sizes (0.7mil to 8mil) and type (Au/Cu/Al) of wires are used for bonding. The selection is
being done based on the current carrying capacity of the chip and also the conductivity of the wire is

Die bonded lead frames loaded in magazines are passed through fully automatic wire bond machines.
Basic models in this are ASM309,ASM339, EAGLE60, TOSOK and Orthodyne (Al. Bonding)
.Machine UPH varies from 3000 to 10000 based on the model.
In process Quality checks are loop height, Ball diameter, Hook pull test and the Ball shear test.
Basic defects seen after this process are lead of pin/ chip, wire broken, ball overlap, tight loop, bond
short, etc.
Area of bonding is also defined on the chip as well as on the lead as per the specified drawing.
Refer attached are the typical Bonding units in TO126 package. We can see the basic bond structure
in the photo to understand the concept.
In Cu bonding process, we provide inert atmosphere additionally to avoid oxidation.
Selection of wire type also contributes to the price of each unit, to meet the market competition.
Basic inputs in the process are temperature (in case of thermosonic bonding) air to index the lead
frame and N2 for cooling.
Basic tools required are the Capillary (which carries the wire during bonding)

Brief description of the process

41 | P a g e
Before moulding after moulding


This is the process in which chip is encapsulated with the plastic compound (Epoxy) to make the
device safe from the outside environmental conditions.
This process gives the particular shape to the package. we can see lead frame in TO-126 package
after moulding process in above diagram.

Plastic compund (Epoxy) is used in form of pallets. These pallets are preheated and then injected
through the mould machines.
After this, epoxy flows through the particular cavities designed to give the shape to the package.
In basic operation, preheated lead frames are loaded on a frame & fixed between the moulds. After
this, epoxy is injected & flows to the cavities by using hydraulic plungers.
In this process temperature at each point of cavity is maintained to have the uniformity in the
package outlook.
The basic defects seen after moulding process are metal flash, pin hole, unfilled epoxy, mould shift
The shelf period of the epoxy is also maintained in the process to avoid the defects in the process.In
this process, basic operator discipline of handling the wire bonded lead frame is also maintained to
avoid wire press(which can short the junction).The basic accessories used are gloves, wrist band,
claw(to pull the lead frame out ot the magazine) and the face mask.
In metal-can packages, device encapsulation is being done using welding process to the metal caps.
Caps are used to cover the device.

Lead frames are then kept in oven for 7 hours to cure the compound .
In the moulding output, we also get some epoxy flash on the package,it is seen on the top called Gate
epoxy and also on the sides which effects the cosmetic look of the device. This flash of Epoxy is
removed using degatting and deflash process.In degatting moulding,leadframes are scrubbed on
Emory paper to remove the gate. After this,devices are kept in NaOH chemical which makes the
epoxy flash loose on the edges.
This is finally passed through high pressure water beams to completely clean the epoxy flash.

Some precautions that must be observed while performing the operation are:

42 | P a g e
• Wristbands, facemasks and gloves should be worn.
• Material handling must involve least number of touches/ lead frame.
• Mould cleaning with NaOH must be practiced as per schedule.
• The operator must examine the moulds each time before and after cleaning with air blast


Brief description of the process

Before Dip Tin before Dip Tin after Dambar and RBC

After deflash, dambar cutting is done by pneumatic press using punch and insert as tools. As we
know that the lower portion of the lead frame is copper so we need to cover this with solder, so that it
can be easily mounted on PCB.CDIL is using two main processes:

(a)Electroplating-In this process, lead frames are attached to metal hooks which are further
connected to cathode. High current is passed through the chemical bath. Solder stickers are attached
to the anode which ultimately after reaction gets deposited on the copper leads of the lead frame.

(b)Hot Diptin-In this, lead frames are first cleaned with the copper dioxide to remove the oxidation
layer from the leads. After this, leads are dipped into flux, solder bath and finally washed with hot
surf water and IPA.In this process, it is important to maintain the temperature of the bath to have
uniform solder layers on the leads.
We have seen basic defects in the process holes, rough solder, solder missing and solder balls.
After this, lead frames undergoes 100% sorting to remove all mechanical defects.Then, bottom Rail
cutting is done to have devices in simulated form.Now pre-test Qualification is done on the Curve

43 | P a g e
Tracer to check the basic transistor action of the component on sample basis.Life shelf of basic
cutting tools(Punch, Insert) is maintained as per the production. All cutting and dip tinning processes
are semi-automatic. After this, all the devices are ready for testing.

Rejection criteria for dip tinning process:

a) Joined leads: Leads short during lead finish operation.

b) Black leads: Visually dull appearance can be seen with naked eye.

c) Solder on heat sink: No. extra solder on heat sink should be visible with naked eye.


Flow chart for material in Testing:

Material to end customer is dispatched in two basic types of pickings. I.e. Bulk form and tube or tape
form. The flow of material is different for these two different packing types.

Bulk material Tape or tube material

Untested material Untested Material

44 | P a g e
100% testing 100% testing

Marking QA Electrical

QA Visual Marking

QA electrical Tube pack or taping

Packing Sorting

Post pack Qualification QA visual

QA electrical

Post pack Qualification

Let us understand the basic production system for tube/tape packed material.

Now untested material after merging is ready for testing. The equipment used for testing is
combination of Handler and Tester. Software (test program) is programmed into the tester to define
7each device sequentially for testing and is interfaced with the tester to get the right path for sorting
of good and reject parts. We can refer the copy of the test program in Annexure I.

Each new device before testing is followed with BUY-OFF procedure to ensure anti-mix up.

First of all the operator set the wiring connections as per the device configuration and cleans the
machine for fresh lot testing. Control Program is connected to the devices under testing. Sometimes
we also define the priority of devices to be extracted from the lot, if more than one device is to be
made from a single lot.

After finishing the setup of device under testing, operator regularly monitors the yield of each lot on
different testers.

Testing is electrical sorting of the produce. After all the stages of manufacturing the material in case
of TO-247/TO-92 packages travels to this stage. Here the devices are loaded into testers’ traveller
wise. Testers are used to test the devices for the parameters as per the specification of a particular
device. Forward and reverse biasing characteristics of the transistors are checked on the testers.
Testers have an electromechanical vibrator that is used for moving the material into a chute that has
test fingers to hold the device. The tester applies voltages to devices and checks the performance for
forward & reverse bias. As different kinds of devices are used we have to use different programs for

45 | P a g e
testing them. The programs become different in the sense that we need to apply different voltages
and check different resulting values for the same characteristics.

In C.D.I.L. there is three types of parameters which are tested:-

1. Parameters in Data Sheet

2. Internal Spec’s
3. Special Request From Customer


1) Parameter testing by handler machine for 100% surety

2) Printing by Han’s laser machine

3) Manual testing by quality department
4) Taping by taping machine
5) Profile projector checking for right value angles, lead bend etc.
6) Sorting
7) Ammo packing
8) M.I.F


1) Parameter testing by handler machine for 100% surety

2) Printing by Han’s laser machine & tube packing.

3) Manual testing by quality department
4) Now there is direct sorting no taping and no indexing.
5) Profile projector checking for right value angles, lead bend etc.
6) Sorting

46 | P a g e
7) Packing
8) M.I.F


First time testing of device is called 100% testing it is mainly called production testing Second time
testing of device is called 200% testing. In these process maximum parameters voltages and currents
are given to a device for microseconds or millisecond depending upon program.

IP-tester is specially made for testing of high power package (To-247). IP-tester is attached with
TESEC handler. The program is making on IP-tester. Handler is basically automatic testing machine
which test the devices according to program. Program is making according to costumer demand and
also according to device. There is a data sheet of every device, in which standard range of
parameters is written.
Mainly following Parameters are checked:

1) Current Gain (Hfe)

Hfe is nothing but the gain .The gain may be of two types .

I) DC gain (Hfe)
II) AC gain (Achfe)
Where only Hfe is written that means the gain is DC

GAIN may be defined as the ratio of Ic (collector current) to the Ib (Base current).

Hfe = Ic/Ib.

During the measurement of gain, Ic and Vce are forced and Ib is sensed. Moreover we know that Hfe=Ic / Ib.
In this way the gain is measured. In the case of Achfe, the only difference is that Ac is superimposed on the
biasing signal and in the same way Ib is measured.

2) Saturation Voltages (Vcesat, Vbesat)

Define as voltage between two junctions when device is in saturated state.
Vbesat:- Saturation Voltage between base & emitter.

Vcesat:- Saturation voltage between collector & emitter.

47 | P a g e
During the measurement of Vesat, both Ic and Ib are forced and emitter is grounded, the voltage is sensed
between collector and emitter. Similarly is case of Vbesat.

3) Breakdown voltages( Bvceo, Bvebo)

Defined as voltage at which a device gets breakdown.
Bvceo (Breakdown voltage b/w collector and emitter)
Bebo (Breakdown voltage b/w collector and emitter)
Bvcbo (Breakdown voltage b/w collector and base)
Similarly Vces, Vcer, Vcex
During the measurement of Vceo, the current i.e.Ic is forced at the collector and voltage i.e.Vmax is
also applied. The voltage is sensed b/w collector and emitter i.e. At Cv terminal. Similarly in the case
of Vebo, Vces, Vcex.

4) Leakages (Iceo, lebo )

Defined as reverse current b/w two junction while the third junction can be open, shorted etc.
Iceo (Leakage current between collector and emitter with base open)
Iebo (Leakage current between emitter and base with collector open)
Icbo (Leakage current between collector and base with emitter open)
Ices (Leakage current between collector and emitter with base short)
Icex (Leakage current between collector and emitter with x- supply b/w emitter and base)
Icer (Leakage current between collector and emitter with resistor b/w emitter and base)
During the measurement of Iceo, Vc i.e. Voltage is applied at the Ci terminal i.e. Ei terminal.
Similarly, in the case of Iebo and Icbo, but in the case of Ices the only difference is that emitter and
base are shorted and in case of icex, there is an X- supply b/w emitter and base while in case of Icer,
there is a resistance b/w emitter and base. However the measuring conditions are same as discussed
5) Forward voltage:
It can be defined as the forward voltage between any two junction e.g. Base and emitter, base
and collector etc.
Vfbe(forward voltage between base and emitter)
Vfec(forward voltage between emitter and collector)
Vfbc(forward voltage between base and collector)
During the measurement of Vfbe, Ib is forced at the base and emitter is grounded. The voltage is
measured between base and emitter. Similarly in case of Vfec and Vfbc.

48 | P a g e
6) Dvbe (Delta Vbe)
This parameter is used to check the die attach quantity of the device. Delta is used to get the
difference of two tests. In this test three biasing signals are used i.e. Ic, Vce and Ie. However the
bias 3 i.e Ie is forced only for small interval of tme to heat the device.Then the voltage is measured
before and after forcing this third bias signal. This value of difference in Vbe is directly related to die
attach strength of device.
7) DEF:-
This parameter is used to just define a value to be used in further is some test.
8) DELTA:-
This parameter is used where only limit is to be changed and the measuring condition is kept same.
This parameter is used to get the ratio of two tests.
10) SAME:-
This parameter is used where only limit is to be changed and the measuring condition is kept same.


The procedure of manual testing is very simple and straight. It contains only two major parts: - one is
“Manual Deck” and other is “Socket” which is connected with wires. First of all, transistor is
inserted in the socket and then press enter key the result will display on the manual deck.


Measurement is done optically. The main feature of profile projector is that , its not connected to any
computer that is, Program-med. It has DRO (Digital Read Out).The transistor is inserted and its
character is to be displayed. If its characteristics are matched then it is ‘OK’ according to their
mechanical measurements i.e. alpha, angle, Lead bend etc.


In this department, there are mainly three types of machine are which are as follows.
1. Handler
2. Han’s Laser

49 | P a g e
3. Taping


It is very important to know about the concepts of forcing and sensing in the measurement of all the

As we have seen that there are only three terminals or measuring points in a transistor but there are
six cables which are used during the measurement or testing of the device. These are called Kelvin
contacts. There are two wires at every junction, one for forcing and other for sensing. The wires for
sensing and forcing are shorted at the device end.(i.e. Ci and Cv shorted.Ei and Ev are shorted and Bi
and Bv are also shorted).but there is one thing to remember that forcing is always done at Ci, Ei and
Bi and sensing is done from Cv, Ev and Bv terminal.

Now, what is this forcing and sensing? Forcing is nothing but only to force some kind of signal, it
can be current or voltage, into the junction and sensing is just to measure these signal.

Now main reason behind this is that we should never measure from the point where current is

Now there are different forcing and sensing functions for every parameters e.g. in Vfbe forcing
function is Ib and sensing function is Vfbe. In Hfe forcing function is Ic and Vce and sensing is Ib.


Handler has following three parts:-

1. Parts Feeder Unit

2. Test Head Unit

3. Sorter & Control Unit (main unit)

Block diagram:-

50 | P a g e




Semiconductor tester

A tester is an electronic system which tests a device by sending current and voltage signals

Through it to check its various parameters e.g. forward voltage, breakdown voltage, leakage current


Please see below the general view of test handler model 786-HT.Let us understand the basic
operation of the equipment. Equipment has 5 basic assemblies

(a) Parts Feeder unit: This unit has capacity of 2500 devices. It is a vibratory bowl operated by
the electromagnetic coils. Devices due to vibration in the feeder step-up on the tracks in anti-
clockwise direction. Reverse devices are being fallen into the bowl with the designed
clearance on the top side trap.
(b) Counter Unit: It counts the number of devices falling into each individual bin. Counter of
any bin can be reset. At start of each lot, all the counters clear to monitor the yield of a lot
(c) Test Head: this unit is basically responsible for the sequential indexing of the parts to the
test finger. Sequential; indexing is internally controlled by cam assembly and the sensors.
The description of the test head is as below:

Number of test stations 2 stations

51 | P a g e
Contact finger construction flat springs with Kelvin contacts,

Holder fixed in place and shielded

Contact finger material /life

For solder or gold plated leads steel/1*10^6 duty cycle minimum

For silver or tin plated leads copper/3*10^5 duty cycles minimum

Contact finger capacity 5A, 700V

Contact finger capacitance 2pF

Contact finger maximum leakage 1nA @ 500V

Contact finger connection socket or soldered

(d) Sorter unit: The sorter is installed in the center of rotary table. Sort detection and full bin
detection ensure a highly reliable sorting operation. A pulse motor driven revolving metal
chute is capable of both clockwise and anti-clockwise motion, automatically selected for
minimum distance.

Maximum rotation time 190ms

Maximum rotation angle 172.8deg

Sort detection sensor at bottom of rotary chute


Quantity 25 uniformly shaped metal bins all removable

From front of handler

Capacity 6000 devices per bin

52 | P a g e
Full bin detection sensor near top of each bin

Control Unit

The control unit includes the control circuitry and the operation panel with switches,
indicators, and alarms necessary for operation.

Alarm sound

The Alarm circuit is controlled by a read switch for intermittent or continuous alarm sound.

Physical characteristics

53 | P a g e
Outer dimensions 1050mm (w) * 700mm (d) * 1330 (h)

Net weight 260kg

Installation both castors and seated bolts


Main frame shadow blue

Front panel ivory

(e) Rotary chute: Cam controlled pins serve as mechanical gates. The devices are carried by
gravitation with air acceleration optional. Device detects sensors detect indexing errors, such
as two devices passing through a gate together.


1. Rotary switch:
• AUTO (Automatic mode operation): With the rotary switch in this position,
pushing the START switch starts the handler into automatic operation. The handler
continuous to operate, pausing only for test time, until the STOP switch is pushed.
• MANU (Manual mode operation): With the rotary switch in this position, pushing
the START switch causes the index motor rotate to and stop at the test stop position.
The test start signals are then transmitted to the testers. When the final test end signal
is transmitted back, the sorter rotates the rotary chute to the bin designed by the tester
bin signal, and the handler stops. At this point, the TEST switch may be operated to
repeat testing.
• SELF CHECK AUTO (self check automatic mode operation): This mode is used
to check the automatic operation of the handler without using the tester. No test start
signal is produced, and the sorter responds to the position of the SORTER CHECK
switches instead of a tester bin signal.

54 | P a g e
• SELF CHECK MANU (self check manual mode operation): This mode is manual
version of SELF CHECK AUTO.

2. START SWITCH (self check mode operation): This switch starts the handler into

3. STOP SWITCH: This switch stops the handler when in automatic mode operation. It may
also be used to turn off alarm sound.

4. TEST SWITCH: This switch is used in MANU mode to repeat testing of devices remaining
at their test positions and still in contact with contact fingers. Pushing this switch sends the
test start signals to the testers and the handlers wait for the final test end signal. However, no
test start signal is produced for a test station if no device is in test position or for the 2nd test
station if the device failed at 1st test station.

• FEED: With the switch, in this position, the parts feeder continuously feeds the
• AUTO: With the switch, in this position, the pool sensor on the chute controls the
parts feeder, turning it on and off to keep the proper quantity of devices lined up in
the chute.
• STOP: With the switch, in this position, the parts feeder is turned off.


• SORTER CHECK START SWITCH: This switch is used when checking the
handler positioned at SELF CHECK AUTO or SELF CHECK MANU. Pushing the
sorter check START SWITCH causes the sorter to rotate and stop at the bin selected
by the bin1-24/ or bin 0 switches. Then pushing the handler START switch will
cause the device at 2nd test station to drop into the selected bin.
• BIN 1-24 SWITCHES: This switch selects the bin from 1-24 if bin 0 switch

55 | P a g e
• BIN 0 SWITCH: This switch determines if the bin selected will be bin 0 or the bin
selected by the bin 1-24 switch.

• ON OFF SWITCH: This switch activates or deactivates alarm sound.
• FEEDER ALARM INDICATOR: This indicator gives indication when the
quantity of devices in the parts feeder has dropped too low.
• SORT ALARM INDICATOR: this indicator gives signal when the sorter pulse
motor does not come to the required stop position after being actuated by the
necessary number of pulses.
• NO PASS INDICATOR: this gives the indication when the expected device did
not pass through the sort detect sensor which is located at the bottom of rotary
• FULL BIN INDICATOR: When the full bin alarm goes on, one of these indicators
will light to show which bin has been detected as full.

8. FEEDER CONTROL: This controls the vibrating control of the parts feeder.
• POWER SWITCH: This switch turns the power to the handler on and off.
• MAIN FUSE: This is a 10A fuse to protect the entire circuitry.
• FEEDER MOTOR FUSE: This is a 5A fuse to protect the parts feeder and index
• MAIN Neon INDICATOR: This indicator is off when the main fuse has blown.
• FEEDER MOTOR Neon INDICATOR: This indicator is off when the feeder
motor fuse has blown.
• HOUR METER: This meter shows the integral number of hours that the handler
has so far been powered.


1. Preparation
• Supply the parts feeder with the devices. The parts feeder may contain up to 2500 devices.

56 | P a g e
• Set the rotary switch to AUTO or MANU if a tester is connected to the handler or to SELF
CHECK or SELF CHECK MANU if no tester is connected.
• If the rotary switch has been set to a SELF CHECK mode, set the SORTER CHECK
switches for the desired bin.
• If the rotary switch has been set to AUTO or MANU, check that the tester is properly
connected to the handler.
• Set the feeder switch to AUTO.
• Set the alarm ON-OFF switch to ON
• Turn ON the power switch. When this switch is turned ON, the handler carries out a
resetting operation with the sorter slowly rotating (0.5rps) to reach the retest bin (bin 0).
• Check to see if any alarm indicator has turned ON.
• Adjust the parts feeder vibration with the feeder control.

2. Auto-handler operation
• After pushing the start switch, a device is indexed past the index pin at the bottom of the
chute and reaches the 1st test station. Any device between the 2 test stations falls to the 2 nd test
• The contact fingers then make device contact and the index motor stops.
• In AUTO or MANU mode, 40ms after the index motor has stopped, a test start signal is
generated for the device in each test station.
• The index motor remains stopped for at least 50ms. If the end of this time, the device from
the 2nd test station during the previous index has already passed by the sort detect sensor, the
handler is ready for next step.
• If during the previous index cycle, a device had been in the 2nd test station and if by the end of
the 50ms after the index motor has stopped, no device has yet been detected past the sort
detect sensor, the handler waits and will not go to previous step.
• A device passing by the sort detect sensor causes the counter to count. The device counted is
the one tested during the previous index cycle and not the device being tested in the current
index cycle. The counter does not operate while the handler is in SELF CHECK mode.
• In AUTO or MANU mode upon arrival of the test end signal and bin signal, the sorter rotates
to the bin designated by the tester bin signal. In a self check mode since there are no tester
signals, the sorter rotates to the bin selected by the SORTER CHECK switches.

57 | P a g e
• One set of contact fingers separates from the device in the first test station for the device to
go to the 2nd test station. The other set of contact finger separate from the device in the 2 nd test
station for the device to enter the sorter. In MANU or SELF CHECK MANU mode, the
START switch must be pushed for the handler to continue. The index motor moves to the
machine stop position. The contact finger separate from each device to let the device in the
first station fall to a point midway between the 1st and 2nd test stations and the device in the
2nd test station to enter in sorter.

• The device which has fallen into the sorter travels through the rotary chute and a class chute
into a bin.

• In the AUTO or SELF CHECK AUTO mode the handler automatically returns to 1st step
(except for pushing the START switch which is no longer necessary) for repetition. To stop
the handler, push the STOP switch. The handler will then stop after releasing the device in
each test station. The device in the 2nd test station falls to the sorter, while the device in 1 st test
station falls to a station midway between the test stations.


1. Polarity NPN/PNP

2. Test stations 3(standard), maximum 5 stations may test with different program

3. Main memory 64K RAM

4. Program storage main memory (minimum 40 and maximum 50 blocks)

Host CPU

5. Capacity of test program

(a) Test plan 125 tests maximum
(b) Sort plan 125 sorts maximum

58 | P a g e
(c) Test max per sort 125 tests per sort

6. Test method CPU comparison

7. Bin or sort counter 6 digits

8. Capacity of counter
(a) Bin or sort counter 24 bin
(b) Sort limit counter 24 bin
(c) Sampling counter 24 bin
(d) Tested counter 100 tests
(e) Failed counter 100 tests

9. Operating time
(a) Test time 0.01us-9.99s
(b) Relay switching time 5ms per a test
(c) CPU time about 1.5ms (depend upon test time)

10. CPU Z80

11. Data out capability both test and bin count result

12. Power requirements 50 or 60Hz

13. Dimensions 600mm(w)*700mm(d)*1050(h)

14. Resolution of computation truncated after 3 digits

15. Environmental requirements

(a) Temperature 25deg C

59 | P a g e
(b) Humidity below 60%

We can understand the tester equipment model 8101-TT/A in two parts i.e. software and hardware.
Tester has option to test all the discrete components like transistor, diodes, FET, Dual gate FET,
thyristor, and opto-coupler and voltage regulator.


The software allows the 8101-TT to be connected to external software. With a new timer board,
testing at the tester end can be controlled externally. Test results can be logged in a special ASCII
format, and test files can transferred to the external computer and vice versa.

A test file consists of test plan and sort plan. It contains all the test and sort conditions required to
evaluate and sort devices into designated bins. A sort contains the tests that must pass or fail in order
to qualify. A bin number is also assigned to each sort. After a test file is joined to a station, its sorting
order can be rearranged. Sort limiting and sampling are allowed, sampling replaces yielding.

Both branch and cover option are available to change the entered testing sequence. Depending upon
the result of a test, a conditional branch and/or cover option can be executed. Both pass and fail
program can be programmed, for example BOP=23 and COF=25 are allowed. By careful
programming, redundant tests may be skipped to reduce testing time.

Before a sort is qualified for testing, all the tests in that sort are first checked if any test is tested and
failed earlier. The sort is disqualified if one test had failed.

Before a test is sent to the hardware, the system checks the result area. A test is skipped if it was
tested/covered with its PF result identical as the set requirement. However, the sort will disqualify if
they are different.

Depending upon the type of sorts (And, Or or All), the system determines whether the sort is
satisfied or disqualified, or continuous to execute the rest of the tests in that sort.

Software mode organization

Eight modes are implemented with an additional TERM mode

60 | P a g e
• Editor (#)
• Sort (%)
• Cassette (*)
• Logger (!)
• Item (/)
• Alarm (+)
• Maintenance (@)
• Term (<) (mode 2 only)
Command summery
Summary below indicates that the output device options are available to the commands:


>A ALRM Mode



>I ITEM Mode



>S SORT Mode



>D0 DATA Out

>D Delete file name

>DL Default list

>DT Default time

>F/ File directory list

61 | P a g e
>RN Rename file name

>$$TT Change to Mode-1 operation

>$$HP Change to Mode-2 operation


#E Enter new test program

#P/ Print test program

#C Correct test program

#Q goto READY Mode

Correct mode function

C Change

D delete

I Insert

P Print

Sp Next

_ Previous

. Repeat

Q goto Editor Mode


%CH Clear Halt

62 | P a g e
%CL Clear lock station

%CS Clear sort limit

%J Join default

%JB Join TBB Type

%JM Join multiple

%JS Join TBS file

%L/ List station

%LM/ List multiple

%OS Open-sort limit

%P/ Print priority list

%SL Set lock station

%SP Set priority list

%SS Set sort limit

%ZS Zero sort limit (clear)

%Q goto READY mode


*C Copy system program

*D Delete file

*I Initialize

*L List directory

*LF/ List free area

63 | P a g e
*R Read file

*RN Rename file name

*S Save system and test programs

*W Write files

*WA Write all files

*QA goto READY mode


!C Clear all counter

! CB Clear bin counter

! CS Clear sampling counter

! CT Clear test counter

!D Display bin

! DT Display test

!F Find

! HA Halt all counter

! HB Halt bin counter

! HS Halt sampling counter

! HT Halt test counter

! L/ set logging

! MC Monitor clear

! MS Monitor set

64 | P a g e
! PB/ print bin counter

! PS/ Print sampling counter

! PT/ Print test counter

! RA Resume all counter

! RB Resume bin counter

! RS Resume sampling counter

! RT Resume test counter

!S Set sampling

!Q goto READY mode


+CC Clear continuous-fail alarm

+CS Clear sort limit alarm

+F Find

+SC Set continuous fail

+SS Set sort limit alarm

+W Wait for alarm

+Q go to READY mode


/2/ Bias-2 Item table

/C/ Condition table

65 | P a g e
/Q goto Ready mode


@C Change

@D Data log

@E Edit

@F Fix

@L Loop

@S Skip

@T Test

@U Update

@sp next T#

@- Previous T#

@. Repeat T#

@Q goto READY mode


<<Esc>H Halt testing

<<Esc>P pause testing

<<Esc>C Continue testing

<GS Get station status

<TS Test start station

<DM Dump test program to 8101-TT

66 | P a g e
<DC Dump test program to cassette

<LM load test program from 8101-TT


This command checks and changes the system default time table. The default test time may range
from 001us to 9.99s. To make the new test time active by default when the system software is
loaded, change the default time table before making a system copy.


9.99 And below =120ms

10.0nA to 99.9nA =80.0mS

100nA to 999nA =30.0mS

1.00uA to 9.99uA =20.0mS

10.0uA to 99.9uA =2.50mS

100uA to 999uA =1.00mS

1.00mA to 9.99nA =380uS

10.0mA to 99.9mA =380uS

100mA to 999mA =380uS

1.00A and above =380uS

Find below the general instructions for making test program and defining the guard band for the
electrical parameters, for transistor testing.

67 | P a g e
Short plan on monitor screen

a) Test for contact fail of the device at test fingers, the typical format is:


b) Test for catastrophic failure viz. short, open, low voltage mix-up and BC’s.
For short, the forward voltage will be near to zero and leakage current will be maximum. For
open devices, the forward voltage will be maximum and the current will be zero.

T2 VFBE <300mV Ib=100uA Y

T3 SAME <1.00V T#2

T4 SAME <13.0V or 18.0V T#2

If the value of VFBE is <300mV then device is said to be E-B short

1V-13V polarity mix-up

>13V or 18V open

c) Test for intermittent failure viz. to check mechanical bond strength.

T5 VFBE <1.18V Ib=150mA

d) Test for ICEO is used to segregate BC’s/CE short, the typical format for this command is
T6 ICEO <900nA *VCE= --

68 | P a g e
*VCE depends upon VCEO. If VCEO is <100.0V, VCE should be 60% of VCEO and if
VCEO>100.0V, VCE should be 80% of VCEO.

6. Test for ICBO, the typical format is like:

T7 ICBO <200nA *VCB= --

*VCB will be as per the rated VCBO of the device.

7. Test for IEB, the typical format is like

T8 IEB <500nA

*VEB will be as per the rated VEBO of the device.

8. Test for specs given in CDIL data sheet. These tests are specified in data sheet. Typical format

T9 BVCEO >104V Ic=1mA Vmax=350V

T10 BVCBO >104V Ic=100uA Vmax=350V

T11 BVEB >5.2V Ie=100uA Vmax=025V

Minimum of 4% guard band is to be taken for breakdown voltages. Forcing current is 1mA for
VCEO, 100uA for VCBO and VEB as per the datasheet. Vmax is always in 3digits.

9. Guard band for VCESAT, VBESAT and BTON should be minimum 10mV. The test
conditions for VCESAT, VBESAT and BTON should be as per the data sheet. Typical
format is like:
T12 VCESAT <980mV Ic=2A Ib=200mA

T13 VBESAT <980mV Ic=2A Ib=200mA

T14 BTON <980mV VCE=4A Ib=500mA

69 | P a g e
10. Guard band for HFE (D.C. gain) should be 5% w.r.t. the specs available in data sheet. The
test conditions for HFE should be as per the data sheet. The typical format is like:
T15 HFE >43 VCE=2V Ic=150mA Y

T16 SAME <238 T#15

T17 HFE >27 VCE=2V Ic=500mA

11. Test for die attach quality using PRE4 and DVBE command for DVBE spec, typical format is
T18 PRE4 <1.00 B-3=150mA B-4=040uA

T19 DVBE >045mV VCE=10V Ic=10mA 10msec

T20 SAME <075m T#19

12. Beta ratio is included for device which have NF<4db. The typical format is like:
T21 HFE >10.0 VCE=10V Ic=100uA Y

T22 HFE >10.0 VCE=10V Ic=1mA Y

T23 DIVID >400m T#21 T#22


(a) Breakdown Voltages: BVceo, Bvcbo, Bvces, Bvebo: These are the potential voltages
between the junctions e.g.: Breakdown voltage between collector and emitter when base is
open. This category is specified in the reference data sheet of the device.
X-axis is voltage/division and y-axis is current/division. We are checking BVCEO>100V@1mA .

b) Forward Voltages: Vfbe, Vfec, Vfbe: We can see the characteristics of catastrophic failures
as below:
c) Leakages: Iceo, Icbo, Ieb, Ices.

a) Open: Plain, wire bond fresh, lead off pin, broken wire

70 | P a g e
Open device characteristic on curve tracer

b) Beta collapse: Units with high leakages will show breakdown voltage as per below

Beta collapse on curve tracer

c) Short: CE, CB, EB short. In case of EB short, VCEO=VCBO. For CE short, BVCEO=0

Short device graph on curve tracer

d) Good unit: Unit which satisfies all the parameters

71 | P a g e
Good device graph on curve tracer



ICE: 000pA~ 0.2%+3pA

VCE: 1.00V~999V 3pA 10mV
9.99Ma 0.4%+10mA

ICB: 000pA~ 0.2%+3pA

VCB: 1.00V~999V 3pA 10mV
9.99mA 0.4%+10mA

IEB: 000pA~ 0.2%+3pA

VCE: 1.00V~999V 3pA 10mV
9.99mA 0.4%+10mA

Leakage ICEX: 000pA~ 0.2%+3pA 3pA 10mV

VCE: 1.00V~999V
current 9.99mA 0.4%+10mA 1mV

HILCE : 0.4%+1nA
VCE : 1.00~20.0V 1nA 10mV
000pA~20.0A 0.2%+10mV

HILCB : 0.4%+1nA
VCB : 1.00~20.0V 1nA 10mV
000pA~20.0A 0.2%+10mV

HILEB : 0.4%+1nA
VEB : 1.00~20.0V 1nA 10mV
000pA~20.0A 3.0%+10mV

Breakdown BVCE : IC : 0.4%+10mA 10mV 1nA

Voltage 0.00V~999V 100nA~500mAVmax 0.4%+1nA

72 | P a g e
: 0.00V~999V

BVCB : IC : 100nA~500mA 0.4%+10mA

10mV 1nA
0.00V~999V Vmax : 0.00V~999V 0.4%+1nA

BVEB : 0.00V- IC : 100nA~500mA 0.4%+10mA

10mV 1nA
999V Vmax : 0.00V~999V 0.4%+1nA

IC : 100nA~500mA 0.4%+1nA
BVCEX : 10mV 1nA
Vx :+/-100mV~+/- 0.4%+10mA
0.00V~999V 1mV
20.0V 0.5% +1mV

VCE : 1.00~20.0V 3pA 10mV
IB : 000pA~20.0A 0.2%+10mA
IC : 100nA~20.0A 1nA
0.4% +1nA

HFE : 10-12~999K VCE : 1.00~20.0V 0.2%+10mV 10-12 10mV

DC Gain
(IB:000pA~20.0A) IC : 100nA~20.0A 0.4%+1nA 1nA

RHFE : 10-12~999K
VCE : 1.00~20.0V 3%+10mV 10-12 10mV
(IB :
IC : 100nA~20.0A 0.4%+1nA 1nA

VCESAT : 000mV IC : 100nA ~ 20.0A
0.4%+1nA 1mV 1nA 1nA
~ 20.0V IB : 100nA ~ 20.0A
0.4% +1nA

Saturation VBESAT : IC : 100nA ~ 20.0A
0.4%+1nA 1mV 1nA 1nA
Voltage 000mV~ 20.0V IB : 100nA ~ 20.0A
0.4% +1nA

RVSAT : 000mV~ IC : 100nA ~ 20.0A
0.4%+1nA 1mV 1nA 1nA
20.0V IB : 100nA ~ 20.0A
0.4% +1nA

73 | P a g e

Special test items are the items that have zero test title, i.e. only CPU time is incurred. If any of the
referenced test is not yet tested, the system would automatically test it first.

The special test items are:

(1)CONT: the contact checks the Kelvin contacts on the device. The result is either pass or fail.
For example:


(2)SAME: The same test compares the specified test with the limit. This reduces testing time.
For example:

T2 VCESAT >19.0mV Ic=2.0mA Ib=2.00mA 2.50mS

T3 SAME <21.0Mv T#=2

(3)ADD: The add test compares the sum of the results of two earlier tests with the limit. The
sum is obtained by adding the result of the first test with the second test, i.e. result= T#a +
For example:

T5 ADD <100 T#a=3 T#b=4

(4)MULTI: The multiple test compares the multiplied of the results of two earlier tests with the
limit. The multiplied result is obtained by multiplying the result of the first test with the
second test, i.e. result= T#a * T#b.
For example:

T5 MULTI <100 T#a=3 T#b=4

(5)DELTA: The delta test compares the absolute difference of the results of two earlier tests
with the limit. The absolute difference is obtained by subtracting the result of the first test

74 | P a g e
with the second test, i.e. result= T#a - T#b.
For example:

T5 DELTA <100 T#a=3 T#b=4

(6)DIVID: The divide test compares the ratio of the results of two earlier tests with the limit.
The ratio is obtained by dividing the result of the first test with the second test, i.e. result=
T#a/ T#b.
For example:

T5 DIVID <100 T#a=3 T#b=4

(7)DEF: the define test defines a limit value between 001K to 999K as the result of the result. It
is normally used for mathematical operations by other special items. A constant can be
For example:

T5 DEF 1.00


The following options are available for testing:

(1)Branch option: the branch option consist of branch-on-pass and branch-on-fail, and may be
used to reducing test time by skipping certain tests based on the result of some tests to change
the execution sequence. It is applicable to TBB.
(a) When the test is passed: if the branch-on-pass option is set, then testing will branch to the
specified test skipping those tests between the current test and the specified test. If the
BOF option is set, no action will be taken.
(b) When the test is failed: if the branch-on-fail option is set, then testing will branch to the
specified test skipping those tests between the current test and the specified test. If the
BOP option is set, no action will be taken.
(2)AR-Auto range: This option provides auto ranging if the result excluding the range is not
between 099 to 998.
The auto range function works as follows:

75 | P a g e
(a) When the test result is over, the measurement is set to the next higher range and the test is
repeated. If necessary, this action is carried out a maximum of 3 times to obtain a test
result less than 999.
(b) When the test result is between 009 to 098, the measurement is set to the next lower range
and the test is repeated. If necessary, this action is carried out a maximum of 3 times to
obtain a test result less than 098.
(c) When the test result is 008 or less, the measurement is set to second lower range and the
test is repeated. Depending on the next result, step (b) or (c) may be repeated. If
necessary, this action is carried out a maximum of 3 times to obtain a test result between
099 to 998.


The sort plan section of a test file contains all the sorts (max 125) and their sorting information.

Each sort consists of sort name, bin number, test requirements (up to 125 tests), and the type of sort

1) Entering format: the entering procedure is given below and illustrated by the example:

1. Enter the sort name or “E” to terminate. It is illegal to terminate anew file at S#1.
2. Enter a bin number followed by a SP or CR to continue.
3. Enter the test requirements as follows:
When entering more than one test, two tests must be separated by a SP or comma.


76 | P a g e
2) Sort name:

Each sort name accepts its characters. Maximum spaces are not allowed. Following are the reserved
sort names:

S1, S2 ,……………..S125 except when same as S#

1, 2 ,………………….125 except when same as S#

B1, B2 ……………B250 reserved for bin numbers

L1, L2,……………..L32 reserved for priority levels

E reserved for terminate a mode

A reserved for logging mode

3) Types of sorts:

1. AND sort: AND sorts are conventional classified sorts. To qualify an AND sort, a device
must pass T#1 AND T#2 AND T#3 and so on. In other words, a device must pass every test
in an AND sort to qualify that sort. No special character is required at the beginning of the
sort name.
2. OR sort: to qualify an OR sort, a device must pass T#1 OR T#2 OR T#3 and so on. In other
words, a device must pass only one test in an OR sort to qualify that sort. A plus sign ‘+’ is
required at the beginning of the sort name.
3. ALL sorts: all the tests in ALL sort are testes regardless of the result status of each test. To
qualify an ALL sort, a device must pass every test in that sort. An ampersand sign ‘&’ is
required at the beginning of the sort name.
4. REJECT sort: A sort automatically becomes REJECT sort when no test exists in that sort. A
REJECT sort qualifies unconditionally and it is normally placed at the end of the priority list
to collect devices that fails to qualify any of the other sorts. The absence of a REJECT sort in
the PL will cause the system to issue the default reject bin 250 when name of the sorts

77 | P a g e
Lots after qualification are now subject to marking. By CO2 Han’s laser marking machines, devices
are marked as per the control drawing specifications. Process is also followed by Buy-Off and
regular process audits for correct marking. We can see below a typical drawing for marking in case
of TO126 package.

After 100% testing, marking on devices is done by HAN'S Laser.

Han’s Laser: It is made of SYNRAD, COHERENT CO2 laser system on the basis of control
software system. Its main features are high laser technology, sophisticated mechanical system,
electronic technology and computerized system.

78 | P a g e
Marking using Han’s laser

It consists of laser power case, 3D dynamic driver optical system, cooling system, software operating
system and work table. Laser beam with wave length 10.6um from laser is extended by extender lens,
and then cast on the reflector of X-axis and Y-axis two scanner through Zn Se optical lens group. The
scanner swings quickly under computerized control and scan laser beam in plane X and Y 2D
directions. Laser beam focuses on the surface of the product being marked and form some tiny, high
energy density laser speckles, thus every high energetic laser pulse ablates on the product surface and
hence marking is completed. This course duplicated by computerized control, pre-edited marking
contents as words and pictures are marked on the product surface permanently.

100% electrically qualified devices are marked as per the specifications defined in the marking
diagrams. We can see the typical marking in the photograph, in this, "JB" denotes the plant code, "8"
stands for year 2008 and "03" stands for week of the year. This is being done for the traceability of the
manufacturing date.
Unique advantages of laser marking are as following:-

1. It can mark bar code, serial numbers and characters, graphs, image etc.

2. The marking will not fade away on account of environmental factors.(e.g. damp, acid or alkaline
atmosphere), but will stay permanently. They can also be protected from counterfeit.

3. Top marking quality:- due to non contact machining, the product will not damage.

4. High efficiency- it can easily be controlled by computers to achieve automation. No need to

unnecessary to stop the machine for a rest or increase the temperature to solidify. One or more
group of characters and pattern can be marked each time or several parts can be marked at the same

5. Low processing cost:- The continuous processing in large amount scan eventually make cost of
each part very low so as to bring about benefits, although the lump-sump investment is very high.

All the above advantage makes it very difficult to counterfeit. Especially the colored mark is different
shades of color. When the common metallic material are marked, reverse effect can be resulted in
because the different shades & thickness of ablated lines can make the color and reflectivity. There
exist a reverse color effect & sub luminous effect on the glass & plastic material.

79 | P a g e
Before Marking After Marking

The equipment is appropriate laser marking machine for TO-92,TO-126,TO-247 transistor. It is made
up of three parts, the first one is CO2-F10 LASER GENERATOR; the second is an industrial PC and
software; the last one is the double vibrating bowls automatic feeding system.

It has tightly constructed packed good features, high automation level and the best produce efficiency
than others in the same trade. It also economizes energy, stability dependable and operation


After marking, material goes to taping+2nD 100% testing to catch any catastrophic failure. Here the tail
end of first lot get mixed partially with second lot to get standard 2K output quantity for each tape. We
can refer the basic forming structure below with the required specifications

In the process all specifications mentioned in the below diagram are periodically checked for quality
output. The average UPH in the equipment is 8-10K. Each taping machine is attached with the tester
and catastrophic caught units get chopped in the machine.

80 | P a g e


F1 F2






The machine is used for the backend process of TO-92 package. In order to use the test –completed
apparatus in the automatic inserting machine, the entire process of forming, testing, taping, and
packing are automated and therefore the machine enables high speed and precision.


Taping machine is classified into following parts:
1. Hopper, bowl feeder and rail feeder: Hopper is the initial part to insert the product. The toggle

81 | P a g e
switch is used near the feeder for ON/OFF/AUTO with the photo sensor which senses the
amount of product on the feeder. When the toggle switch is set ON, the hopper compulsorily
vibrates and when OFF, its vibration is also compulsorily off.
Bowl feeder is a device for supplying a product to a rail feeder. Toggle switch is used with the
bowl feeder for its operation. When the toggle switch is set to AUTO, the rail feeder left sensor
is ON and thereby the bowl feeder starts vibrating and when the sensor is OFF, the bowl feeder
stops. After bowl feeder, rail feeder is used for transporting a product received from the bowl
feeder to the inserting point by using an AC motor and silicon belt.

2. Inserting part: The part is for inserting the product from the feeder to the drum consecutively.
OVER TAKE detects the inserting status of the product. The over take part is connected to a
photo sensor which detects the inserting status of the product.

3. Adhesive tape part: adhesive tape is placed on the central back part of the upper panel of the
machine. PXS1 is proximate sensor for detecting the adhesive tape and if the sensor is ON, we
need to replace the tape.

82 | P a g e
4. Forming part: Drum rotates in clockwise direction, each drum hole goes through the inserting
point and thereby inserting the product one by one. The product inserted rotates in clockwise
direction and meet the forming block at 9 o’clock position of the drum if we regard the drum as
a clock. This block is to form the lead of a product.

5. Sealing part: The heat sealing part is placed in 12 o’clock position of the drum, from which the
hot air comes out. Here the product adhered between the carrier tape and adhesive tape.

6. Open/touch testing part: open/touch testing part is used to examine if the TO-92 package is
defective or not. This switch is placed on the front panel. The operator needs to select the select
switch according to the type of TR (NPN/PNP) and the arrangement of the lead (EBC, CBE,
ECB). If it is a defective product, the red LED will turned ON, both the two LED’s will turned
ON in the same way during the automatic test period by the machine.

7. Counting part: the upper count sensor is set to face the head part of the taped product. The
photo fiber sensor checks the presence of a product and if there is a product, it increases one
point of the counting value on the operation panel. If there is no product, it increases one
omission count value. The total value is added into the front count panel and therefore if the

83 | P a g e
omission occurs twice in a row, the machine stops.

8. Ammo packing part: The tapped product had been embossed in every unit of 25 products in the
previous step. This is to ship the product in a box and last work is made at the ammo packing
After inserting the product into the bowl, select the power ON toggle switch of the feeder and the
linear feeder properly. The bowl feeder and linear feeder operate normally regardless of the start of the
machine once the main power is supplied thereto. If the photo sensor placed on the left and right sides
of the rail (linear feeder) are covered by the product and turned off, the bowl feeder stops. When the
rail is loaded with products from its inserting points, the machine can be started. A defective product
would not be transported so smoothly between the bowl feeder and the rail.

Taping machine

Manual mode:
In the manual mode, the machine operates only when the START switch is pressed. Manual mode can
be used for the initial operation or instruction of the machine.

Auto mode:
Select AUTO on the main screen and presses the START switch once, the machine instantly starts to
operate normal. In this case, all the blocks of the machine perform their own function and machine will
keep operating unless an error is detected.

After completing the taping process, material undergoes 100% manual visual inspection.

84 | P a g e

Various defects observed in sorting are:



3.Double print

4.Broken epoxy

5.Lead Bend

6.Tin Missing

7.Yellow Heat Sink

8.Gate Scratch

9.Improper Damber Cutting


After complete processing, tape/tube packed boxes are scanned with bar code for the traceability of
the material & then handed over to finished good store. Here the material is kept device wise in
different racks. All the racks are identified for proper nomination & location. After getting the
dispatch advice from the marketing section, material is handed over to shipping area. In this area as
per invoice, qty inner boxes are further packed to outer cartons with complete address to final
destination. We can see the storage of tapes in the below picture.

85 | P a g e
MIF:- M.I.F stands for material in finish good . When material is packed then it’s final Qty is
forward with the help of CDIL on line web system and all material is hand over to finish good store.


10) Summary of training

I would like to express that the industrial training has given me lot of exposure and confidence to
face the odd situations out

I would like to share that I have not only learned the manufacturing process of discrete components,
but enhanced my knowledge on different automatic machine operations. During my course of
training, I learn as how to expand my capabilities by working in a good atmosphere with the
operators, colleagues and interaction with the seniors.

I also learn that how line people are maintaining material inventories, the strength emerging out as a
team work, follow-up on well define systems meeting different international standards and the spirit
of motivation to meet each and every requirement of the customer, whether it is delivery in very
short durations or any specific support.

86 | P a g e
I felt myself very homely in such a clean and disciplined environment of the company. Company has
not only given me the right exposure on the latest technology being used to manufacture
semiconductor in the world, but fulfill all my needs on better understanding of the different

I have also observed the other parallel activities, being carried out on the shop floor for the continual
improvement in each work area viz. 5S to improve the work culture and traceability, Kaizen for
small-small improvement activities, suggestion schemes to motivate the staff, award scheme to
explore the abilities of the staff, projects to improve the yields at each stage and the different cost
cutting engineering activities.

I would definitely like to mention here that company is looking at the different global requirement
scenarios in this field and had set a “mark” in the world market for its excellence service and
quality product.

It is difficult to forget the moments of my training, when I feel myself totally involved in the work,
as a part of the process. In such a healthy atmosphere, I got full opportunity to learn the maximum
peaks. Company has provided me all the inputs like machine manuals, demonstration on each
process by the concerned area experts, technical DO &DON’TS and the confidence to handle the
different equipments.

It was here that I got to learn how relationship building help in improving the task & teamwork
enhances your self-confidence. I felt a new phase of my career in the semiconductor manufacturing
industry and learned as how to solve the problems in a practical manner. In fact I understood how
formation/foundation of a professional engineer is being carried out.

My view of analyzing the world had also grown conservative and I am feeling myself more
strengthened in technical as well as administrative aspects. My attitude in handling the new
challenges was also emphasized and I steps towards the new era of learning.


1. The Art of Analog Layout by Alan Hastings 2001 Prentice-Hall

2. Semiconductor Devices by Mauro Zambuto 1989 McGraw-Hill

3. Semiconductor Manufacturing Technology by Quirk and Serda 2001 Prentice-Hall




87 | P a g e









“B-96/97 , Phase-VII, Industrial Area, S.A.S. Nager, PUNJAB”

88 | P a g e
89 | P a g e