PIC MICROCONTROLLER -16F877

Processor Architecture
•
• CISC
 Large amount of instructions each carrying out a different permutation
of the same operation
 Functionality of the instructions is more dependent upon the
processor’s designer

• RISC
 Fundamental set of instructions
 More control for users to design their own operations

Harvard Vs. Von Neumann Block Architectures

• Von Neumann Architecture

 Common memory for program and data
 Simple chip design
 Execution of an instruction can take multiple cycles

• Harvard Architecture
 Separate memory space program and data
 Instructions are executed in one cycle
 Easier timing of loops and delays

•
•
•
•
 •
• Von Neumann Architecture example
Mov acc, reg
Cycle 1 Read instruction
Cycle 2 Read data out of Ram and
put into
Acc

• Harvard architecture example

Mov acc, reg
Cycle 1 Execute previous instruction
Read “move acc, reg”
Cycle 2 Execute “move acc, reg”
instruction

PIC use the Harvard Architecture

• PIC Microcontrollers main features:

• Harvard Architecture
• RISC Feature
• CPU pipelines instruction fetching and execution in order to achieve an
execution of one instruction at every cycle

Instruction pipeline

• The pipeline is used to process the instrs.taken from program store.

• PIC uses pipe line is used which has independent fetch,decode & execute
stages.
•
 Flash
Program Counter
ROM
(13 bits)
Program
Memory
Address
8192
x 14 bits
Stack RAM
0000 – 1FFF 13 bits File
x8 Registers
Instructions levels 368
X 8 bits

000-1FF
Instruction Register
File Address

Program address

Working (W)
Register File Select
Literal Register
Arithmetic & Logic
Unit
Status bits
Status (Flag)
Op- Register Data Bus
code (8 bits)

EEPROM
Instruction MCU 256 bytes
Decode & control
CPU control lines
Ports, Timers
ADC, Serial I/O

Timing control

Clock Reset
Port A B C D E
Features –PIC16F877
• Instruction Pipeline:
• The instruction pipeline is a two-stage pipeline which overlaps the fetch and
execution of instructions.
• The fetch of the instruction takes one TCY, while the execution takes
another TCY.
• Due to the
overlap of the fetch of current instruction and execution of previous
instruction, an instruction is fetched and another instruction is executed every
single TCY.
Single Cycle Instructions
• With the Program Memory bus being 14-bits wide, the entire instruction is
fetched in a single machine cycle (TCY).
• The instruction contains all the information required and is executed in a
single cycle.
• There may be a one cycle delay in execution if the result of the instruction
modified the contents of the Program Counter.
• This requires the pipeline to be flushed and a new instruction to be fetched.
Reduced Instruction Set
• When an instruction set is well designed and highly orthogonal (symmetric),
fewer instructions are required to perform all needed tasks.
•
• With fewer instructions, the whole set can be more rapidly learned.
Reduced Instruction Set
• When an instruction set is well designed and highly orthogonal (symmetric),
fewer instructions are required to perform all needed tasks.
• With fewer instructions, the whole set can be more rapidly learned.
Register File Architecture
• The register files/data memory can be directly or indirectly addressed.
• All special function registers, including the program counter, are mapped in
the data memory.
MEMORY
• Program Memory
• Register File Memory (Data RAM)
Program Memory
• Used for storing compiled code
• Each location is 14 bits long
• Every instruction is coded as a 14 bit word
• PC can address up to 8K addresses because PC for PIC16F877 is 13bit.
Program Memory Organization
• Mid-Range MCU devices have a 13-bit program counter capable of addressing
an 8K x 14 program memory space.
• The width of the program memory bus (instruction word) is 14-bits.
• Since all instructions are a single word, a device with an 8K x 14 program
memory has space for 8K of instructions.
• This makes it much easier to determine if a device has sufficient program
memory for a desired application.
USE OF PCLATCH
• To jump between the program memory pages, the high bits of the Program
Counter (PC) must be modified.
• This is done by writing the desired value into a SFR called PCLATH
(Program Counter Latch High).

• If sequential instructions are executed, the program counter will cross the page
boundaries without any user intervention.
• For devices that have less than 8K words, accessing a location above the
physically implemented address will cause a wraparound.
• That is, in a 4K-word device accessing 17FFh actually addresses 7FFh. 2K-
word devices (or less) do not require paging.
DATA Memory
• Consist of 2 Components
 General Purpose Register (GPR) Files (RAM)
 Special Purpose Register (SPR) files OR SFR

Data Memory Organization

• Data memory is made up of the Special Function Registers (SFR) area, and the
General Purpose Registers (GPR) area.
• The SFRs control the operation of the device, while GPRs are the general area
for data storage and scratch pad operations.
• The data memory is banked for both the GPR and SFR areas.
• The GPR area is banked to allow greater than 96 bytes of general purpose
RAM to be addressed. SFRs are for the registers that control the peripheral
and core functions.
• Banking requires the use of control bits for bank selection.
• These control bits are located in the STATUS Register (STATUS<7:5>).
• Figure shows one of the data memory map organizations, this organization is
device dependent.
General Purpose Registers (GPR)
• Some Mid-Range MCU devices have banked memory in the GPR area.
• GPRs are not initialized by a Power-on Reset and are unchanged on all other
resets.
• The register file can be accessed either directly, or using the File Select
Register FSR, indirectly.
• Some devices have areas that are shared across the data memory banks, so a
read / write to that area will appear as the same location (value) regardless of
the current bank.
• We refer to this area as the Common RAM.
Special Function Registers (SFR)
• The SFRs are used by the CPU and Peripheral Modules for controlling the
desired operation of the device.
• These registers are implemented as static RAM.
• The SFRs can be classified into two sets, those associated with the “core”
function and those related to the peripheral functions.
• All PIC MCU devices have banked memory in the SFR area.
• Switching between these banks requires the RP0 and RP1 bits in the STATUS
register to be configured for the desired bank.
• Some SFRs are initialized by a Power-on Reset and other resets, while other
SFRs are unaffected.

Banking In SFR
• The data memory is partitioned into four banks. Each bank contains General
Purpose Registers and Special Function Registers.
• Switching between these banks requires the RP0 and RP1 bits in the STATUS
register to be configured for the desired bank when using direct addressing.
• The IRP bit in the STATUS register is used for indirect addressing.
Direct and Indirect Addressing of Banks
 • Each Bank extends up to 7Fh (128 bytes).
• The lower locations of each bank are reserved for the
Special Function Registers.
• Above the Special Function Registers are General Purpose Registers.
• All data memory is implemented as static RAM.
• All Banks may contain special function registers.
• Some “high use” special function registers from Bank0 are mirrored in the
other banks for code reduction and quicker access.

Direct Addressing
SFRs IN PIC
• Dedicated to Special Function Like,
– ALU Status
– Timers
– I/O Ports
– ADC
– Etc.
The function of each SFR is fixed because its used to control peripherals.
PIC SFRs are 8 bit registers.
Varies according to series.

GPR(RAM
– It’s a group of RAM locations in file register.
– It is used for data storage and scratch PAD.
– Each location is 8 bit wide.
– Capacity can vary from chip to chip.

THE WREG REGISTER IN THE PIC

• In the CPU, registers are used to store information temporarily.

• The information could be a byte of data to be processed, or an address
pointing to the data to be fetched.
• The vast majority of PIC registers are 8-bit registers.
• In the PIC there is only one data type: 8-bit.

WREG
• The 8-bit WREG register is the most widely used register in the PIC
microcontroller.
• WREG stands for working register, as there is only one.
 •The WREG register is the same as the accumulator in other
microprocessors.
• The WREG register is used for all arithmetic and logic instructions.
MOVLW instruction
• The MOVLW instruction moves 8-bit data into the WREG register.
• Format:
• MOVLW K ;move literal value K into WREG
• K is an 8-bit value that can range from 0-255 in decimal, or 00-FF in hex.
• The L stands for literal, which means, literally, a number must be used.
• MOVLW 25H ;move value 25H into WREG (WREG = 25H)
ADDLW instruction
• The ADDLW instruction has the following format:
• ADDLW K ;ADD literal value K to WREG
• The ADD instruction tells the CPU to add the literal value K to register
WREG and put the result back in the WREG register.
• Notice that in ADDLW, first comes the letter L (literal) and then the letter W
(WREG), which means "add a literal value to WREG," the destination.
• To add two numbers such as 25H and 34H, one can do the following:
• MOVLW 25H ;load 25H into WREG
• ADDLW 34H ;add value 34 to W(W = W + 34H)
• Executing the above lines results in WREG = 59H (25H + 34H = 59H)

PIC WREG and ALU Using Literal Value

• The following program will add values 12H, 16H, 31H, and 43H:
• MOVLW 12H ;load value
12H into WREG (WREG = 12H)
• ADDLW 16H ;add 16 to
WREG (WREG = 28H)
• ADDLW 11H ;add 11 to
WREG (WREG = 39H)
• ADDLW 43H ;add 43 to
WREG (WREG = 7CH)

WREG AND ALU

WREG AND ALU
• PICmicro MCUs contain an 8-bit ALU and an 8-bit working register.
• The ALU is a general purpose arithmetic and logical unit.
• It performs arithmetic and Boolean functions between the data in the working
register and any register file.
File Register
• File register (data RAM) space allocation in PIC
• The file register is read/write memory used by the CPU for data storage,
scratch pad, and registers for internal use and functions.
• As with WREG, we can perform arithmetic and logic operations on many
locations of the file register data RAM.
• The PIC microcontrollers' file register size ranges from 32 bytes to several
thousand bytes depending on the chip.
• Even within the same family, the size of the file register data RAM varies
from chip to chip. Notice that the file register data RAM has a byte-size width,
just like WREG.
• The file register data RAM in PIC is divided into two sections: (a) Special
Function Registers (SFR), and (b) General-Purpose Registers (GPR).
• The general-purpose register section is also referred to as General-Purpose
RAM (GP RAM).
MOVWF instruction
• MOVWF, the F stands for a location in the file register .
• The MOVWF instruction tells the CPU to move (in reality, copy) the source
register of WREG to a destination in the file register (F).
• After this instruction is executed, the location in the file register will have the
same value as register WREG.
• The location in the file register can be one of the SFRs or a location in the
general purpose registers region.
"M
OVWF PORT A"
EXAMPLES TO ACCESS SFR
• MOVLW 55H ;WREG =
55H
• MOVWF PORTB /copy
WREG to Port
B (Port B = 55H)
• MOVWF PORTC ;copy
WREG to Port
C (Port C = 55H)
• MOVWF PORTD ; copy
WREG to Port
D (Port D = 55H)

• PORTB, PORTC, and PORTD are part of the special function registers in the
file register

COMF –Complement instruction

• Syntax : COMF fileReg, d
• The "COMF fileReg, d" instruction complements (inverts) the contents of
fileReg and places the result in WREG or fileReg.
• E.g. Put 55H into WREG and then send it to SFR location of Port B.
• Then the content of Port B is complemented, which becomes AA in hex. The
01010101 (55H) is inverted and becomes 10101010 (AAH).
• MOVLW 55H
;WREG = 55h
• MOVWF PORTB
;Move WREG
to Port B SFR (PB = 55h)
• COMF PORTB ;
complement Port B (PB = AAh)
• DECF –Decrement instruction
• Syntax : DECF fileReg, d
• The "DECF fileReg, d" instruction decrements (subtracts one from) the
contents of fileReg and places the result in WREG or fileReg.
• E.g. Put the value 3 into fileReg location 0x20. Then the value in location
0x20 is decremented and placed in fileReg.
• MOVLW 3 ;WREG = 3
• MOVWF 2OH ;move WREG
to loc 2OH (loc 2OH = 3)
• DECF 0x20, F ;loc 20H
has 2
• DECF 0x20, F ;loc 20H
has 1
• DECF 0x20, F ; loc 20H
has 0 and WREG = 3
• Now, contrast the above code with the following:
• MOVLW 3 ;WREG =
3
 • MOVWF 2OH
;move WREG
to loc 2OH (loc 2OH = 3)
• DECF 0x20, W
;loc 2OH has 3 (WREG = 2)
• DECF 0x20, W
;loc 20H has 3 (WREG =1)
• DECF 0x20, W
;loc 20H has 3 (WREG = 0)
• MOVF Instruction
• Syntax : MOVF filereg,D
• It brings the data into working register from I/O pins
• Used to move the data from I/O port such as Port B into CPU.
• It is also used to move the data into WREG from any SFRs or from any
location in the GP RAM to perform ALU operations.
• MOVF
• Example: Write a program to get data from the SFRs of Port B to Port C again
add 04 to it and send to PORT C continuously.
• AGAIN MOVF
PORTB, W
•
MOVWF
PORTC
•
ADDLW 04H
•
MOVWF
PORTC
•
GOTO
AGAIN
•
MOVFF Instruction
• Copies data from one location in file register to another location in file
register.
• File register location may be any location in the DATA RAM space.
• It moves the RAM data without going through WREG register.
Syntax: MOVFF Source, Destination
Ex. MOVFF PORTB,PORTC ;copy data from portb to portc
• MOVFF PORTB, W ;copy data from portb to WREG

CPU Registers
• STATUS
• PC
• W
• PCL
• PCLATH
STATUS REGISTER
• The STATUS register, shown below, contains the arithmetic status of the
ALU, the RESET status and the bank select bits for data memory.
 • Since the selection of the Data Memory banks is controlled by this register, it
is required to be present in every bank.
• This register is also called as Flag Register.

PIC DATA FORMAT

• PIC has 8 bit data format.
• Byte of data can represented by four ways,
1) Hex e.g.
MOVLW 25

ADDLW 0x11

ADDLW 12H

ADDLW
H’2A’

MOVLW
0E5H – Take care

PIC DATA FORMAT

Binary Numbers:
e.g. MOVLW B’10101010’;WREG=AAH or 10101010
3) Decimal Numbers
e.g.
MOVLW D’12’;WREG=0CH or 00001100

MOVLW .12
4) ASCII Characters
e.g.
MOVLW A’2’ ;WREG= 00110010 or 32H Hex no. for ASCII ‘2’;
ASSEMBLER DIRECTIVES
• Directives give directions to the assembler.
• E.G. EQU,ORG,LIST and END.
• EQU- Equate –Defines a constant value or fixed address.
• E.g. COUNT EQU 0x25
• MOVLW COUNT ;WREG=25H
ORG(origin)
• Used to indicate beginning of the address.
• Can be used for both code and data memory.
• The number after org must be in HEX.
END Directive
• Indicates to the assembler end of the source file.
• Anything after END will be ignored by the assembler.
LIST Directive
• Its unique for PIC assembler informs to the assembler about specific PIC chip
for which the program should be assembled.
– E.g. LIST P = 16F877
#include directive
• Tells assembler to use libraries associated with the specific device.
• Compiler will compile accordingly.
_config directive
• Gives information to assembler about configuration bits for the targeted chip.
• These bits are read during power up.
radix directive
• Used to indicate the numbering system is decimal or hex.
• Default is HEX if we don’t use radix.
• If you want to use ,use “radix dec”.
Assembler
• The assembler converts source code to object code, and then list file.
• Linker converts –OTH file.
• Both are integrated in MPLAB sodtware.
• MPLAB IDE has =>
Editor
,assembler,linker,simulator and all development environment required.

 The assembler converts the instructions into machine code.

 The assembler will produce an object file and a list file
 The extension for the object file is “obj” while the extension for
the list file is “lst”
 The linker program takes object code files and produce an
absolute object file with the extension “abs”.
 The “abs” file is fed into a program called “OH” (object to
hex converter) which creates a file with extension “hex"
that is ready to burn into ROM

Programming the PIC

Directly Downloading Hex files to the PIC Memory
• Used to transfer HEX file to the PIC and begin program execution
• Two methods (HEX file must be generated)
– MPLAB IDE
• Programmer◊Select Programmer◊PICKit2
– PICkit2
• Separate program
• Start◊All Programs◊Microchip◊PICkit 2 v2.11
CALL
BRA (Branch) Instruction
• 2 Byte Instruction(16 bit)
• First 5 bits are opcode and 11 bits relative address.
• Adress range from 0000h to FFFFh ,divided into forward and backword
jumps.
• Forward jump address is positive and for reverse jump address is negative i.e.
+1023 to -1024.
• E.g. HERE BRA HERE
• OR
BRA $
STACK POINTER IN PIC16F877
• Stack is RAM used by CPU to store some very critical information
temporarily.
• This information is address but not data.
• CPU needs it because of limited no. of registers.
• PIC 16F877 have an 8-level deep x 13-bit wide hardware stack.
• The stack space is not part of either program or data space .
STACK POINTER WORKING
• The PC is PUSHed onto the stack when a CALL instruction is executed or an
interrupt causes a branch.
• The stack is POPed in the event of a RETURN, RETLW or a RETFIE
instruction execution.
• So Stack is LIFO type of memory.
• After the stack has been PUSHed eight times, the ninth push overwrites the
value that was stored from the first push.
• The tenth push overwrites the second push (and so on).
PROGRAM COUNTER-PC
• It is used by CPU to point to the address of next instruction be executed.
• The fetches opcode from program memory, the PC is incremented
automatically to point to the next memory location instruction).
• The PC is 13-bits wide. Maximum memory = 8K
• The low byte is called the PCL register which is readable and writable.
• The high byte is called the PCH register.
• This register contains the PC<12:8> bits and is not directly readable or
writable.
 • All updates to the PCH register go through the PCLATH register.
• PCLATH is never updated with the contents of PCH.

Program Memory Paging

• Some devices have program memory sizes greater then 2K words, but the
CALL and GOTO instructions only have a 11-bit address range. This 11-bit
address range allows a branch within a 2K program memory page size.
• To allow CALL and GOTO instructions to address the entire 1K program
memory address range, there must be another two bits to specify the program
memory page.
• These paging bits come from the PCLATH<4:3> bits .
• When doing a CALL or GOTO instruction, the user must ensure that page
bits (PCLATH<4:3>) are programmed so that the desired program memory
page is addressed .
• When one of the return instructions is executed, the entire 13-bit PC is POPed
from the stack.
• Therefore, manipulation of the PCLATH<4:3> is not required for the return
instructions.
Instruction with PCL as destination

Register Addressing Modes

• There are 3 types of addressing modes in PIC
 Immediate Addressing
 Direct Addressing
 Register Indirect Addressing
Immediate Addressing Mode
• Operand comes immediate after opcode when instruction is assembled.
• This mode can be used to information into working register and selected
register .
• It is not used to load information immediately into file register.
• It is also used for arithmetic and logical instructions.
• E.g. MOVLW 0x20
SUBLW
D’62’
ANDLW
B’10101010’

Immediate Addressing
 • Uses 7 bits of 14 bit instruction to identify a register file address
• 8th and 9th bit comes from RP0 and RP1 bits of STATUS register.
• We can use EQU directive to access immediate data.
• Exp: COUNT EQU 0x20
…….
…….
MOVLW COUNT

Direct Addressing Mode

• The entire data RAM can be accessed using direct addressing mode.
• In direct addressing mode the operand DATA is in RAM memory location
whose address is known.
• This address is part of the instruction.
• E.g. MOVLW 0x56 ;(IMMEDIATE ADDRESSING MODE)
MOVWF
0X40 ;COPY WREG INTO 40H RAM LOCATION
MOVFF
0X40,0X50 ;COPY THE DATA FROM 40H TO 50H

Register Indirect Addressing, INDF, and FSR Registers

• In register Indirect addressing Mode , a register is used as a pointer to the data
RAM location.
• In PIC ,three registers are used i.e. FSR0,FSR1,FSR2.
• File Select Register(FSR) is a 12 bit register used to access the .
• We use LFSR(Load FSR) to load RAM address.
• So FSRx is used as a pointers, they must be loaded first with RAM address.
• E.g.
• LFSR 0,0x30 ;
LOAD FSR0 WITH 0x30
• LFSR 1,0x40 ;
LOAD FSR1 WITH 0x40
• LFSR 2,0x50 ;
LOAD FSR2 WITH 0x50
Advantage of register indirect addressing mode
• Accessing the data dynamic rather than static in direct addressing.
• E.g. Write a program to copy 55H into RAM location 40H to 45H.
ORG 0000H
MOVLW 0x50
LFSR 0,0x40
MOVWF INDF0
INCF FSR0L,F
MOVWF INDF0

LOOK UP TABLE
• DB:Define byte directive is widely used to allocate ROM program.
• The data can be hex,decimal,binary or ASCII.
• E.g.

ORG
500H
DATA1 DBD’28’
DATA2 DB
B’10101010’
DATA3 DB0x38
DATA4 DB
‘Y’,’1’,’2’,’3’
Indirect Addressing