1

The Microprocessor
and The Computer
Input Output
port port

Simplest Computer Architecture

All computer systems consist of basic functional blocks that

include a central processing unit (CPU), memory, and
input/output ports. These functional blocks are connected
together with three internal buses, as shown in the block
diagram of Figure. The three buses are the data bus, the address
bus, and the control bus. Input and output devices are connected
through the input/output ports. A port is a physical interface on a
computer through which data are passed to and from
peripherals.

Memory unit:
RAM, ROM,
Input port Output port
and hard disk

Address bus

CPU Data bus

(Microprocessor)

Control bus

Figure : Basic computer block diagram

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Instructions and data are stored in memory in specific locations

determined by the program, a group of instructions designed to
solve a specific problem. Each location has a unique address
associated with it. Instructions are obtained by the CPU by
placing an dress on the address bus. Instructions are transferred
via the data bus as they are requested by the CPU. The CPU
executes the instructions sequentially; frequently, the
instructions modify data stored in memory or obtained from an
input device. Processed may be stored back in memory or sent
to an output device via the data bus. Signals the control bus are
generated by the CPU to coordinate all of these operations.

Microprocessors

A microprocessor is a very large-scale integrated circuit that

contained the entire CPU of a computer on a single integrated
circuit chip. As microprocessor based computers evolved, they
have become much more powerful and have widely replaced
traditional mainframe computers in business and industry.

Within a given microprocessor are several units, each designed

for a specific job, The specific units, their design and
organization, are called the microprocessor's architecture. The
architecture determines the instruction set and the process for
executing those instructions. Three of the most basic units,
common to all microprocessors, are the arithmetic logic unit
(ALU), the register array, and a control unit, as shown in Figure.
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Other units work in conjunction with these three basic units to

form a specific microprocessor.

Arithmetic
Logic Register
Unit Array
(ALU)

Control
Unit

Figure: Basic units of microprocessors

Table : Intel Microprocessors

One interesting form of microprocessor is called a coprocessor,

A coprocessor is actually a microprocessor designed with a
limited instruction set optimized to perform arithmetic
operations very quickly. As microprocessors changed, one of the
changes has been to incorporate the coprocessor inside what was
originally just the microprocessor. Thus, the coprocessor for the
Pentium is actually included inside the Pentium.

Arithmetic Logic Unit : The ALU is the key processing

element of the microprocessor. It is directed by the control unit
to perform arithmetic operations such as addition and
subtraction and logic operations such as NOT, AND, OR, and
exclusive-OR, Data for the ALU are obtained from the register
array.
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Register Array : The register array is the collection of registers

that are contained within the microprocessor. During the
execution of a program, data and addresses are temporarily
stored in registers that make up this array. The ALU can access
the registers very quickly, making the program run more
efficiently. Some registers are classed as general-purpose
registers, meaning they can be used for any purpose dictated by
the program. Other registers have specific capabilities and
functions and cannot be used as general-purpose registers. Still
others are called program invisible registers, used only by the
processor and not available to the programmer.

Control Unit : The control unit is "in charge" of the processing

of instructions. It provides the timing and control signals for
getting data into and out of the microprocessor and for
synchronizing the execution of instructions.

Microprocessor Buses

The three buses mentioned earlier are part of the internal and
external connections for microprocessors to allow data,
addresses, and control signals to be moved.

The Address Bus : The address bus is a "one-way street" over

which the microprocessor sends an address code to a memory or
other external device. The size or width of the address bus is
specified by the number of conductive paths. The first
microprocessor used in computers had 16 address lines, which
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could address 65,536 (216) unique locations (this is called 64k).

The more bits there are in the address bus, the more memory
locations a given microprocessor can access. The number of
address lines increased to 20,24, 32, and 36 bits as
microprocessor technology advanced. The Pentium IV with 36-
bit address lines, can address over 68,719,476,736 (68G)
memory locations!

The Data Bus : The data bus is a "two-way street" on which

data or instruction codes are transferred into the microprocessor
or on which the result of an operation or computation is sent out
from the microprocessor. The original microprocessors had data
buses that were eight bits wide. Depending on the particular
microprocessor, the data bus size is 8 bits, 16 bits, 32 bits, or 64
bits wide.

The Control Bus : The control bus is used by the

microprocessor to coordinate its operations and to communicate
with external devices. The control bus has signals that enable
either the memory or an input/output port at the proper time to
read or write data. Control lines are also used to insert special
wait states for slower devices and prevent bus contention, a
condition that could occur if two or more devices try to
communicate at the same time.

Now according to syllabus, I would like to discuss separately

the 8085 and 8086 Architecture, Registers and ALU, Instruction
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set Addressing mode, Timing diagram, Fetch, Decode and

Execute cycle, Interrupt Mechanism, DMA in detail.

The 8085 Microprocessor

The 8085A (commonly known as the 8085) is an 8-bit general-

purpose microprocessor capable of addressing 64K of memory.
It has forty pins, requires a +5 V single power supply, and can
operate with a 3-MHz single-phase clock. The 8085A-2 version
can operate at the maximum frequency of 5 MHz. The 8085 is
an enhanced version of the 8080A; its instruction set is upward-
compatible with that of the 8080A, meaning that the 8085
instruction set includes all the features of 8080A instructions
plus some additional ones.

Signals of 8085 are classified into six groups:

1) address bus,
2) data bus,
3) control and status signals,
4) power supply and frequency signals,
5) externally initiated signals, and
6) serial I/O ports.
8085 Architecture
Figure below shows the internal architecture of the 8085. It
includes the following:

ALU(Arithmetic/Logic Unit),
Timing and Control Unit,
Instruction Register and Decoder,
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Register Array,
Interrupt Control, and
Serial I/O Control.
THE ALU
The arithmetic/logic unit performs the arithmetical and logical
functions on 8-bit internal data path. The arithmetic unit is
responsible for fundamental arithmetic operations such as
addition and subtraction, while the logical unit performs logical
operations such as NOT, AND, OR, XOR, Rotate and clear
operation. The ALU consist of the accumulator, the temporary
register, the arithmetic and logic circuits, and five flags. The
temporary register is used to hold data during an
arithmetic/logic operation. The result is stored in the
accumulator, and the flags (flip-flops) are set or reset according
to the result of the operation.

The flags are affected by the arithmetic and logic operations in

the ALU. In most of these operations, the result is stored in the
accumulator. Therefore, the flags generally reflect data
conditions in the accumulator-with some exceptions.

REGISTERS

The 8085 include six register, one accumulator, and one flag
register, In addition it has 16-bit register: The stack pointer and
the program counter. They are described briefly as follows.

1. General purpose Registers: B, C, D, E, H, and L are 8-bit

general purpose registers or scratchpad registers, and can be
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accessed by the programmers. Also, we can use it as register

pairs like BC, DE, and HL, as 16-bit. In 16-bit register the
higher order byte reside in the first register and lower order byte
resides in second register. Also, the HL register pairs functions
as a data pointer or memory pointer.
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Figure : The 8085A Microprocessor:

INTA RST 6.5 TRAP
SID SOD
Functional Block INTER RST 5.5 RST 7.5 Diagram
Interrupt Control Serial I/O Control

8-Bit Internal Data Bus

Temp. Reg. Instruction

Accumulator Multiplexer (8)
(8) Register (8)
(8) W
Temp. Reg.(8)
Z
R
(5) Temp. Reg.(8)
e
Flag B
g Reg.(8)
Flip-Flops
Instruction . C
Decoder and Reg.(8)
Machine S D
Arithmetic
Cycle e Reg.(8) Register
Logic l E.
Unit Encoding Array
e Reg.(8)
(ALU) c H
(8) Reg.(8)
t
L
Reg.(16)
Stack Pointer(16)
+5 V Program
Power Supply
GND CounterIncrementer/Decrement
er Address Latch
Timing and Control (16)

CLK Reset (8) (8)

GEN Control Status DMA Address Buffer Data/Address Buffer

CLK OUT HLDA

RD WR ALE S0 S1 IO/M RESET OUT A15 -A8 AD7-AD0
READY HOLD RESET IN
Address Bus Address/Data Bus
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2. Temporary Registers (internal registers): These are 8-bit

registers and it is used internally not by the programmers.

Temporary data register: The ALU has two inputs, one input is
supplied by the accumulator and other from this temporary
register.

W and Z Registers: These are temporary registers and used to

hold 8-bit data during execution of some instructions. For
instance, the CALL instruction is used to transfer the program
control to a subprogram or subroutine. This instruction pushes
the contents of PC onto the stack and loads the given address
into the PC. This given, address is temporarily stored in the
Wand Z registers and placed on the bus for the fetch cycle.
Thus, the program control is transferred to the address given in
the instruction. Also, during execution of XCHG instruction for
swapping HL with DE contents, as temporary storage of data.

3. Special Purpose Registers

Accumulators (Register A): Accumulator is a 8-bit tri-state

register. It is extensively used in arithmetic, logic, load, and
store operations, as well as in I/O operations. In 8085, most of
the arithmetic and logical operations are stored in accumulator
(register A). Hence, it is known as accumulators.

Flag Register: This is an 8-bit register, out of which 5 bit

contains the significant information in the form of flags. These
flags are affected by the arithmetic and logic operations in the
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ALU and generally it reflects data conditions in the

accumulator, with some exceptions.

The descriptions and conditions of the flags are as follows:

 S-Sign flag: After the execution of an arithmetic or

logic operation, if bit D7 of the result (usually in the
accumulator) is 1, the Sign flag is set. This flag is used
with signed numbers. In a given byte, if D7 is 1, the
number will be viewed as a negative number; if it is 0, the
number will be considered positive. In arithmetic
operations with signed numbers, bit D7 is reserved for
indicating the sign, and the remaining seven bits are used
to represent the magnitude of a number.

 Z-Zero flag: The Zero flag is set if the ALU

operation results in 0, and the flag is reset if the result is
not 0. This flag is modified by the results in the
accumulator as well as in the other registers.

 AC-Auxiliary Carry flag: In an arithmetic

operation, when a carry is generated by digit D3 and
passed on to digit D4, the AC flag is set. The flag is used
only internally for BCD (binary-coded decimal) operations
and is not available for the programmer to change the
sequence of a program with a jump instruction.

 P-Parity flag: In an arithmetic or logical operation,

if the result has an even number of 1’s, the flag is set. If it
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has an odd number of 1’s, the flag is reset. (For example,

the data byte 0000 0101 has even parity even if the
magnitude of the number is odd.)

 CY-Carry flag: If an arithmetic operation results in

a carry, the Carry flag is set; otherwise it is reset. The
Carry flag also serves as a borrow flag for subtraction.

The bit positions reserved for these flags in the flag

D7 D6 D5 D4 D3 D2 D1 D0

S Z AC P CY

Figure : Conditional Flag Register in 8085

register are as follows:

Out of the five flags, the AC flag is used internally for BCD
arithmetic; the instruction set does not include any conditional
jump instructions based on the AC flag. Of the remaining four
flags, the Z and CY flags are those most commonly used.

Instruction Register (IR): This is part of ALU, while executing a

processor operations, the processor first fetches the opcode of
the instruction from the memory (i.e., it places an address on the
address bus and memory responds by placing the data stored at
the specified address on the data bus). The CPU stores this
opcode in a register called the instruction register. Further, this
opcode is used by the instruction decoder to select one of the
256 alternatives, i.e. the decoder decodes the instruction and
establishes the sequence of events to follow. This instruction
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register is not programmable and cannot be accessed through

any instruction.

4. 16-bit Registers:

Program Counter (PC): A set of instructions is known as

program. Microprocessor fetches these instructions from
memory and executes them sequentially. At any time, the
program counter (PC) is a special purpose register to store the
address of the next instruction to be fetched. The PC acts as a
pointer to the next instruction. This PC increment always
depends on the nature of the instruction in execution. For
instances, one byte instruction will increment the PC by one,
two byte instruction will increment by two, three byte
instruction will increment by three, such that PC always points
to the address of the next instruction.

During JUMP or CALL instruction, address followed by JUMP

and CALL instructions is placed in the PC. Then, the processor
fetches the next instruction from the new address specified by
JUMP or CALL instructions.

In case of conditional JUMP or CALL instruction, if the

condition is not satisfied, the processor increments PC by three
otherwise, processor fetches the next instruction from the new
address specified by JUMP or CALL instruction.
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Stack Pointer (SP). The stack is a reserved area of the memory

(RAM) where temporary information are stored. A 16-bit stack
pointer is used to hold the address of the most recent stack entry.

Timing and Control Unit

The control circuitry in the processor 8085 is responsible for all

the control operations. This unit synchronizes all the
microprocessor operations with the clock signal. Along with the
control of fetching and decoding operations and generating
appropriate signals for instruction execution, control circuitry
generate signal required to interface with external
devices(peripherals) to the processor. The control signals are
similar to a sync pulse in an oscilloscope. The RD and WR
signals are sync pulses indicating the availability of data on the
data bus.

Instruction Register and Decoder

The instruction register and the decoder are major part of the
ALU. When any instruction is fetched from memory, it is first
loaded in the instruction register. The decoder decodes the
instruction and establishes the sequence of events to follow. The
instruction register is not programmable and cannot be accessed
through any instruction.

Decoding and Executing an Instruction

Decoding and executing an instruction after it has been fetched

can be illustrated with the example:
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Question : Assume that the accumulator contains data byte

82H, and the instruction MOV C,A (4FH) is fetched. List the
steps in decoding and executing the instruction.

Answer. The contents of the accumulator are specified. To

decode and execute the instruction, the following steps are
performed.

1. The contents of the data bus (4F) are placed in the instruction
register and decoded.

2. The contents of the accumulator (80H) are transferred to the

temporary register in the ALU.

3. The contents of the temporary register are transferred to

register C.

8085 Instruction Set

Instruction: Instruction as the name suggest a binary pattern

designed inside a microprocessor that is used to perform some
specific function. And the whole group of instruction is called
the instruction set. The instruction set determines that what
function a microprocessor can perform. The instruction set of
8085 includes all the instruction of 8080A plus two additional
instructions.

The 8085 instruction are classified into the following five

functional categories:

 Data transfer (copy) instructions

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 Arithmetic instructions
 Logical instructions
 Branching instructions
 Machine control instructions

Data Transfer (Copy) Instruction

Data transfer instructions copies data from source to another

location, called a destination, without modifying the contents of
the source. Actually data transfer term is used for this copying
function. However, the term transfer is misleading, since it
creates the impression that the contents of a source are destroyed
when, in fact, the contents are retained without any
modification. Following types of data transfer (copy) are listed
below together with examples of each type:

Types Examples
Between registers Copy the contents of register C
into register E
Specific data byte to a register Load register C with the data byte
or a memory location 45H
Between a memory location and From the memory location 1500H
a register to register B.
Between an I/O device and the From an input keyboard to the
accumulator accumulator
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Arithmetic Instruction

Arithmetic instructions include addition, subtraction, increment,

and decrement.

Addition:- Any 8-bit number, or the contents of a register, or

the contents of a memory location can be added to the contents
of the accumulator and the sum is stored in the accumulator. No
two other 8-bit registers can be added directly (e.g., the contents
of register C cannot be added directly to the contents of register
E). The instruction DAD is an exception and it adds 16-bit data
directly in register pairs.

Subtraction:- Any 8-bit number, or the contents of a register, or

the contents of a memory location can be subtracted from the
contents of the accumulator and the results stored in the
accumulator. The subtraction is performed in 2's complement,
and if the results in negative, are expressed in 2's complement.
No two other registers can be subtracted directly.

Increment/Decrement :- The 8-bit contents of a register or the

16-bit of a register pair or a memory location can be
incremented or decremented by 1. These increment and
decrement operations differ from addition and subtraction in an
important way; i.e., they can be performed in anyone of the
registers or in a memory location.
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Logical Operations

These instructions perform following logical operations with the

contents of the accumulator.

AND, OR, Exclusive-OR:-Any 8-bit number, or the contents of

a register, or of a memory location can be logically ANDed,
ORed, or Exclusive-ORed with the contents of the accumulator.
The results are stored in the accumulator.

Rotate:- Each bit in the accumulator can be shifted either left or

right to the next position.

Compare:- Any 8-bit number, or the contents of a register, or a

memory location can be compared for equality, greater than, or
less than, with the contents of the accumulator.

Complement:- The contents of the accumulator can be

complemented; all 0s are replaced by 1’s and all 1’s are replaced
by 0’s.

BRANCHING OPERATIONS

The branching instructions alters the sequence of program

execution either conditionally or unconditionally.

Jump-conditional jumps are an important aspect of the decision-

making process in programming. These instructions test for a
certain condition (e.g., Zero or Carry flag) and alter the program
sequence when the condition is met. As well as, the instruction
set includes an instruction called unconditional jump.
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Call, Return, and Restart-These instructions change the

sequence of a program either by calling a subroutine or
returning from a subroutine. As well as the conditional Call and
Return instructions can test condition flags.

Machine Control Operations

As the name suggest these instructions control machine

functions such as Halt, Interrupt, or do nothing.

Addressing modes

Many different methods may specify the memory or register

addresses that an instruction uses. Among the most widely used
addressing techniques are

 Direct
 Indirect
 Immediate
 Indexed
 Relative
 Register Direct
 Register Indirect
 Autoincrement Mode
 Autodecrement Mode
 Stack
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8086 Internal Architecture

The 8086 central processing unit is divided into two
independent functional units as shown in the figure.
They are,
Bus Interface Unit (BIU)
Execution Unit (EU)
Bus Interface Unit
The Bus Interface unit (BIU) is responsible for transfer of
instructions, addresses, and data on the system bus to the
execution unit. It handles the transfer of data between the
processor, memory and I/O devices. It includes instruction fetch,
address transfer, an computation of effective address of the
memory.
The functional part of Bus Interface Unit are,
Instruction Queue (IQ)
Segment Registers
Instruction Pointer (IP)
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BIU C-BUS

Σ
6
5
Instruction
B-BUS 4 Stream
ES
CS
3 Byte
2 Queue
SS 1
DS
IP

CONTROL SYSTEM
EU
A-BUS

ES AL
BH BL
CH CL
DH DL ARITHMETIC
SP LOGIC UNIT
BP
SI
DI

OPERANDS
FLAGS

Figure: 8086 Microprocessor Internal Block Diagram

Instruction Queue (lQ)

The instruction queue is of six bytes in length and is used to
speed up the execution of programs, by prefetching six
instruction bytes in advance from the memory. The pre fetched
instructions are stored in a group of high-speed registers known
as the instruction queue: The BIU works in parallel with the EU.
The BIU fetches the instruction bytes while the EU is executing
an instruction. The simultaneous operations of BIU and EU are
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possible only when the EU does not require the system bus. The
process of fetching the next instruction in advance while the EU
is executing the current instruction, is known as pipelining.

Segment Registers
The Bus Interface Unit contains four 16-bit segment registers.
They are,
1. Code Segment (CS) register
2. Data Segment (DS) register
3. Stack Segment (SS) register
4. Extra Segment (ES) register
These registers are used to store the 16-bit starting address of
the four memory segments. The BIU generates a 20-bit address
using the segment and the offset components of an address. BIU
can address the memory locations starting from 00000H to
FFFFFH (0 to 1Mb).

Instruction Pointer (IP)

The instruction pointer is designated as register IP. It always
holds the address of memory location (offset) of the next
instruction to be executed. As the instruction is executed, the IP
is advanced to point to the next instruction in the memory.
Instruction pointer is also called as the program counter in other
microprocessors.
Execution Unit (EU)
The Execution Unit (EU) works in parallel with the BIU. It
informs the BIU the location at which the next instruction or
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data is to be fetched. The phases of execution of the instruction

are Fetch, Decode, Execute, and Write. The fetch phase
performs fetching of the instruction from the instruction queue.
The decode phase performs the decoding of the instruction. The
execute phase performs real (actual) operations on the data. The
write phase performs the operation of storing the computed
result at the destination.
The functional parts of the Execution Unit are,
Control System and Instruction Decode
1. Arithmetic and Logic Unit (ALU)
2. Flag Register
3. General Purpose Registers
4. Stack Pointer Register
5. Pointer and Index Registers
Control Circuitary and Instruction Decoder
The control circuit of the EU directs all the internal operations
of the processor. The instruction in the EU translates the
instruction fetched from the memory into a series of actions
carried out by the execution unit.

Arithmetic and Logic Unit (ALU)

The arithmetic and logic unit is one of the component of the
execution unit. It performs 8-bit or 16-bit mathematical
operations such as addition, subtraction, multiplication, division,
data conversion and logical operations like logical NOT, OR, or
AND. It also performs register increment, decrement, and shift
operations.
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Registers
The 8086 processor provides a few fast, on-chip (within the
processor) storage elements known as registers. The registers
are 16-bit wide. Registers are grouped on the basis of the
meaning assigned to them. The 8086 processor registers are
shown in Figure.
Fourteen, 16-bit hardware registers are divided into five groups
are listed below.
♦ General Purpose Registers AX, BX, CX, and
DX
♦ Pointer and Index Registers SP, BP, SI,
and DI
♦ Segment Registers CS, DS, ES, and
SS
♦ Instruction Pointer Register IP
♦ Flag Register FR (no specific
name)
AX, BX, CX, and DX are general-purpose 16-bit registers. Each
of these 16-bit registers can also be considered as two 8-bit
registers distinguished as high and low order bytes of the
respective 16-bit registers and referenced as AH, AL, BH, BL,
CH, CL, and DH, DL. The register SP points to the current top
of the stack, while BP register is used as a stack pointer. The SI
and DI are the source and destination index registers primarily
used for manipulating strings. The code segment (CS), the data
 25

segment (DS), the extra segment (ES) and the stack segment
(SS) registers hold the starting addresses of their respective
segments. The instruction pointer-(IP) register points to the
location of the next instruction to be executed. It is used with the
CS register to fetch the next instruction from memory. The 8086
processor has nine, I-bit flags for recording the status of CPU
after the execution of each instruction.

Flag Register
The 16-bit flag register of the 8086 processor stores information
about the status of the processor and the status of the instruction
executed most recently. The format of the flag register is shown
in Figure (a). It consists of two parts, status flags and control
flags. The flag register is modified or read directly through
special instructions known as the processor control instructions
such as CLD, STI, CLC, STD, etc., and through arithmetic
instructions. The Flag Register contains the following flags.
• C -Carry flag • Z -Zero flag • I - Interrupt
flag
• P -Parity flag • S -Sign flag • D -
Direction flag
• A -Auxiliary flag • T -Trap flag • O -
Overflow flag
Carry Flag: The carry flag is designated as CF. The carry flag
is set (CF= 1) if an addition produces a carry or if a subtraction
needs a borrow. Certain instructions like the processor control
 26

instructions can modify the carry flag. For example, the

instruction STC sets the carry flag to 1 (CF=1) and CLC resets
the carry flag to zero (CF = 0). Certain conditional jump
instructions can transfer control to the target location based on
the status of the carry flag.
Parity Flag: The parity flag is designated as PF. Parity flag is
set (PF=1) if the lower-order 8-bits of the result contains the
even number of 1’s; otherwise, it is cleared. It is useful in
checking the errors that occur in data transmission. Certain
conditional jump instructions can transfer control to the target
location based on the status of the parity flag.

Control flags CPU status flags

15 8 7
0
U U U U O D IF T S Z U A U P U C
F F F F F F F F

8085 Compatible
flags
OF – Overflow Flag TF – Trap Flag AF – Auxiliary
Flag
DF – Direction Flag SF – Sign Flag PF – Parity
Flag
IF – Interrupt Flag ZF – Zero Flag CF – Carry Flag
 27

U – Undefined
(a) 8086 flag register format
15 0 Flag
Register

15 8 7 0
A AH Accumulat

General Purpose Registers

X AL or
B BH Base
X BL
C CH Count
X CL
D DH Data
X DL

SI Source

Index Registers
Index
DI Destinatio
n Index

S Stack
Pointer Registers

P Pointer
B Base
P Pointer

C
Code
S
D Data
S
 28

Segment Registers
Extra
S
S
S Stack

IP Instruction
Pointer

Figure: (b) 8086 CPU registers

Auxiliary Flag: The auxiliary flag is designated as AF.

Auxiliary flag is set (AF=1) if there is a carry out of the third bit
during an addition process or a borrow by the third bit during a
subtraction. The conditional jump instructions do not use this
flag.

Zero Flag: The zero flag is designated as ZF. Zero flag is set
(ZF= 1) if an addition or a subtraction produces a zero result.
Certain conditional jump instructions can transfer control to the
target location based on the status of the zero flag.

Sign Flag: The sign flag is designated as SF. It is equal to the

MSB of the result. It is set (SF=1) if MSB is one; otherwise SF
is reset. If the MSB of a signed number is one, it indicates a
negative number, hence, the MSB of a negative number is one
and a nonnegative number is zero in 2’s complement form. The
sign flag indicates whether the previous result was negative or
 29

nonnegative. Certain conditional jump instructions can transfer

control to the target location based on the status of the sign flag,

Trap Flag: The trap flag is designated as TF. If TF is set

(TF=1), a trap (interrupt type 1) is executed after each
instruction, The CPU resets this flag while transferring control
to the interrupt handler, if the interrupt is recognized. There is
no direct instruction in the 8086 processor for modifying this
flag. This feature is useful in implementing the program
debugging utilities.

Interrupt Flag: The interrupt flag is designated as IF. If the

interrupt enable flag is set, a maskable interrupt type can be
recognized by the CPU; otherwise, these interrupts are ignored.
The CPU resets this flag while transferring control to the
interrupt handler, if the interrupt is recognized.

Direction Flag: The direction flag is designated as DF. Certain

instructions such as, STD, CLD, etc., modify the direction flag.
It is used for the manipulation of the data array in string
instructions. If this flag is cleared, then the string is processed
from the beginning with the first element having the lowest
address and progressing towards the highest address. If DF is
set, the string is processed from the higher address towards the
lower address. It increments or decrements the index pointers
based on the status of the direction flag.
 30

Overflow Flag: The overflow flag is designated as OF. It is set

(OF= 1) if an addition produces a carry out of the MSB. In
subtraction operation, it is set when the MSB needs a borrow
and there is no borrow available from the MSB. This is known
as underflow. Certain conditional jump instructions can transfer
control to the target location based on the status of the overflow
flag

General Purpose Registers

The four general-purpose registers (GPRs) of the 8086 processor
which are 16-bits, can be used as operands in most of the
instructions. The GPRs are used as the source or the destination
register during the transfer of data and computation, as pointers
to memory and as counters. Each of the GPRs can store 16-bit
values, can be loaded with or written to the memory, or used in
arithmetic and logical operations. For example, the following
instructions in the code segment,
..
mov ax, 100 ; ax ←100
mov dx, 200 ; dx ← 200
mov ax, dx ; ax ← ax + dx
loads the value 100 into AX, loads the value 200 into DX, adds
the two values and stores the result, 300, into the register AX.
These GPRs can function as the source and destination for the
manipulation of data instruction. Each one of the general-
purpose registers have their own special meaning.
 31

AX Register
The register AX functions as the Accumulator. The register AX
is always involved in multiplication and division as the default
operand. The usage of AX register is the most efficient in data
movement, arithmetic, and logical operations. The register AX
is divided into two parts. The lower 8-bit of the AX register is
AL register and the higher 8-bit of the AX register is AH
register. The splitting of the AX register into AH and AL
registers is convenient for performing the byte-data operations.

BX Register
The register BX functions as the Base Register. It is used as a
pointer to a memory location. It is suitable for accessing the
elements of an array from the memory. The code for reading a
word from memory location 40 in DS into register AX is as
follows:

..
mov bx, 40 ; BX = address of the memory
location
mov ax, [bx] ; Read memory pointed to by BX
register

The register BX is loaded with the offset of the memory location

in DS. The BX register can be treated as two 8-bit registers BH
and BL, as in the case of AX, CX, and DX registers.
 32

CX Register
The register CX functions as the Count Register. Loop and
Repeat instructions of 80x86 use CX register to hold repeat
count value. For example, to repeat a block of code 100 times,
the outline of the program is as follows:
mov cx, 100 ; CX = loop count
Beginofloop:
.. ; body of theloop
loop Beginofloop ; CX +- CX -1, if CX ≠ 0 then
Beginofloop
The register CX can be treated as two 8-bit registers CH and
CL, as in the case of AX, BX, and DX registers.

DX Register
The register DX functions as the Data Register. The register DX
is the only register used as an I/O address pointer in the IN and
OUT instructions. The following code will read a character
from the port number 100 and stores in AL register,
..
mov dx, 100 ; DX = port address = 100
in al, dx ; read from port pointed to by
register DX
The register DX is also involved in 16-bit multiplication
and division operations as the default operand. The
register DX is most efficiently used in data movement,
 33

arithmetic, and logical instructions. The DX register can

be treated as two 8-bit registers DH and DL, as in the
case of AX, BX, and CX registers.

Pointer and Index Registers

The 8086 processor has two pointer registers, the SP and
BP and two index registers, the SI and DI. The pointer
registers are generally used for storing the offset address
of data elements stored in the stack. The index/registers
are used for Storing index or offset of the array elements.

SI Register
The Source Index register is designated as SI. This is
especially used as a pointer to a memory location as in
die case of BX and D1 registers. It is suitable for
accessing the data array (elements of an array) from the
memory. The code for reading a word from a memory
location 40 in DS into the AX register is as follows:
..
mov si, 40 ; S1 = address of memory
location
mov ax, [si] ; read memory pointed to
by DS : SI register
 34

The register SI is loaded with the offset of the memory

location in DS. The register SI is useful in accessing
contiguous memory locations, such as a text string. In
repeat string instructions, SI is used as a pointer to a
source string element.

DI Register
The Destination Index register is designated as DI. It is
especially used as a pointer to a memory location as in
the case of BX and SI registers. It is suitable for
accessing the data array from the memory. The code for
reading a word from memory location 40 in DS into AX
register is as follows:
..
mov di, 40 ; DI = address of the
memory location
mov ax, [di] ; read memory pointed to
by DS : DI register
The register DI is loaded with the offset of the memory
location in DS. The register DI is useful in accessing
contiguous memory locations, such as a text string. In
repeat string instructions, DI is used as a pointer to a
destination string element.
 35

BP Register
The Base Pointer register is designated as BP. The use of
BP register as a pointer to a memory location is similar
to the use of BX, SI, and DI registers. The registers BX,
SI, and DI normally act as memory pointers relative to
the segment register DS (DI relative to ES in the case of
string instructions). The register BP points relative to the
stack segment register. The BP register is generally used
for accessing the parameters from the stack in the
procedures. The outline of the code for reading the first
parameter from the stack by the C language procedure
call convention is as follows:
..
push bp ; save BP onto the stack
mov bp, sp ; assign SP to BP
mov ax, [bp + 4] ; peek for stack and put the
contents
; into AX register
In short, BP is designed to provide support for passing of
parameters between the procedures, local variables, and
other stack based allocation and operations. The BP
register is mainly used to access any location directly in
the stack.
 36

SP Register
The Stack Pointer register is designated as SP. This
register is dedicated for maintaining an area of memory
used as a stack. The stack is an area of memory into
which data can be stored and retrieved on the basis of
Last- In-First-Out (LIFO), i.e., the data stored last in a
stack is the first one to be retrieved. The stack is useful in
implementing procedure calls, recursions, passing of
parameters, creation of local variables, etc.
The register SP always points to the top of die stack
relative to SS. The process of storing data onto the stack
is known as push operation. It is performed by die PUSH
instruction; first, SP is decremented by 2 and then the
data is placed into a new location pointed to by SP. The
SP is decremented by 2, because, the stack in 80x86
system grows from higher to lower memory locations.
The process of retrieving (reading) the data from the
stack is known as pop operation. It is performed by the
POP instruction. First, the contents of the memory
location pointed to by SP is read and stored in the
destination and then SP is incremented by 2 so that SP
points to the next element in the stack after the pop
 37

operation. The push and pop operations are performed on

16-bit operands.

IP Register
The Instruction Pointer register is designated as IP. It
always holds the memory (offset) address of the next
instruction to be executed. As the instruction is executed,

X – Hexadecimal
digit
Physical Address = segment * 16 + Offset

20-Bit address
Figure: Computation of physical address

IP is advanced to point to the instruction at the next

memory address. However, some instructions, such as
jump and procedure calls, can cause the IP to be loaded
with a new value, thereby branching to the target code
(instruction).

Segment Registers

In 80x86 processors based systems, the memory is

organized into segments of 64Kb size. The 8086
processor is capable of addressing 1 Mb (220) of memory.
However, 8086 processor has 16-bit pointers to the
 38

memory but a 20-bit address is required to address the

main memory of 1 Mb size. In 8086 processor, the
address of memory has two parts, the segment and the
offset. Each I6-bit memory pointer or a memory offset, is
combined with the contents of the 16-bit segment register
to form a 20-bit memory address.

Segment and offset are combined as follows, the segment

is shifted left by 4 bits (equivalent to multiplying by 16)
and then added to the offset as shown in Figure to
compute a 20-bit effective address.
CS Register

The register CS is the Code Segment register. The CS

register points to the start of the 64 Kb memory block
which contains the next instruction to be executed. The
next instruction to be executed in the code segment is
pointed to by the offset in the register IP; i.e., the
segment:offset combination is indicated by CS:IP. The
8086 processor never fetches instruction from the
segment other than that is defined by CS and IP. The
register CS can be changed by different instructions,
including certain jumps, and calls and returns (far jump,
far call, or far return). The register CS cannot be loaded
 39

directly. The register IP operates only relative to the

register CS and no other registers operate relative to it.
DS Register
The register DS is the Data Segment register. The DS
register points to the start of the data segment, a memory
block of size 64Kb, where most of the operands are
stored. Normally, the memory offset stored in the
registers BX, SI, and DI operate relative to DS, however,
the register DI operates relative to ES in the case of
string instructions. As the name implies, the DS is used
to store the data set. The DS register is not set to the data
segment, hence it should be set by the user to point to the
appropriate segment.
ES Register
The register ES is the Extra Segment register. The ES
register points to the start of a memory block of size
64Kb. As the name implies, the ES is not dedicated for
any definite purpose. The extra segment is generally used
to make an additional block of memory of size 64Kb
available for data storage. The memory access in ES is
less efficient than the memory access in DS.
 40

The ES is extensively used in string instructions. It is

used as the destination segment, addressed by the
combination of register ES:DI. It is useful in block copy,
string comparison, memory scanning, and clearing block
of memory locations. The register ES can point to the
data segment if an extra block of memory (64 Kb) is not
required.
SS Register
The register SS is the Stack Segment register. The SS
register points to the start of the memory block (64 Kb)
known as the stack memory. The instructions which use
SP to store memory offset referring to the stack segment
are push, pop, call, and return. The offset stored in SP is
capable of addressing only through the SS register. The
register BP also operates relative to SS. The register SS
allows the register BP to be used for accessing the
parameters (parameters passed through stack) and the
local variables that are created on the stack.

Instruction Set of 80×86

The processor 80×86 supports a wide array of
instructions to perform the movement of data (between
memory, CPU, I/O devices), arithmetic and logical
 41

operations (addition, subtraction, multiplication, division,

data conversion, logical instructions), branch (jump
instructions) and control of processor operations (enable
interrupt, set direction flag), string operations, and
protection control.
The 80×86 instructions are classified into the following
categories.
 Data Transfer Instructions
 Arithmetic and Logical Instructions
 Branch Instructions
 Processor Control Instructions
 String Operation Instructions
 Protection Control Instructions
The instruction set of 8086 is upward compatible, i.e.,
programs written for lower version processors can also
be run on higher version processors without any
modification. The higher version of 8086 such as 80286,
80386, 80486, Pentium, P6, etc., are binary compatibles
with lower versions. Hence the discussion on 8086
programming also applies to ×86 family of processors.

Instruction Types
The 80×86 processor instructions are classified into four
groups depending on the number of operands explicitly
 42

specified in the instructions. They are, zero, single,

double, and three operand instructions.

Zero Operand Instructions

The instructions in which the operands are not explicitly
specified are known as zero operand or a instructions.
The implicit operands are assumed to be in the registers.
Examples :
CMC ; complement carry
STC ; set carry
CLD ; clear direction flag
The above instructions operate on an implicitly assumed
8086 flag register.

One Operand Instructions

The instructions in which a single operand is explicitly
specified are known as one operand or address
instructions.
Examples:
INC AX, ; AX ← AX + 1
DEC CX ; CX ← CX - l, decrement CX
content by 1
POP BX ; pop BX from the stack
The above instructions operate on the single operand
specified in the instruction.
 43

Two Operands Instructions

The instructions in which two operands are explicitly
specified are known as two operands or address
instructions.
Examples:
MOV AX, 100 ; AX ← 100
ADD AX, BX ; AX ← AX + BX
SUB CX, 1 ; CX ← CX-l
The above instructions operate on the two operands
specified in the instruction.

Three Operands Instructions

The instructions in which three operands are explicitly
specified are known as three operands or address
instructions. The three operands instruction (MOL is
supported by the 80186 processor only.
Examples:
IMUL BX, CX, 10 ; BX ← CX * 10
IMUL AX, BX, 1024 ; AX ← BX *
1024
The above instructions operate on the three operands
specified in the instruction.
 44

Addressing Modes
Addressing mode is defined as a method of specifying
the effective address of the operands in memory. The
addressing mode increases the flexibility of the
programming language and is useful in implementing the
constructs and data structures of the powerful high level
programming language.

The registers of 8086 involved in computation of the

address of the operand are,
Base Registers : BX and BP
Index Registers: SI and DI
The general form of an operand is,
[base register + index + register + displacement]
OR
[base register + index] [register + displacement]
where BX or BP are base registers,
SI or DI are index registers,
displacement is any 16-bit constant value or
expression or label.
The convention [address] refers to the contents of the
memory location pointed to by the address. The three
components used in accessing the memory operands are,
1. Base Registers: BX and BP
 45

2. Index Registers: SI and DI

3. Displacement: 8-bit sign extended or 16-bit value
The base, index, and displacement can be combined
as,
BX SI
or + or + Displacement (disp) = memory address
of the operand
BP DI
(Base) (Index)
These three components are added together in 8086 each
time an instruction referring to a memory operand is
executed. Each of these three parts are optional, but at
least one of the three must be used depending on the
addressing modes. Using these three address
components, the user can specify the address of the
memory in 16 different ways as listed below.
Direct
1. [disp]
Register Indirect
2. [BX]
3. [9I]
4. [DI]
 46

Based Indexed
5. [BX + SI]
6. [BX + DI]
7. [BP + SI]
8. [BP + DI]
Register Relative
9. [BX + disp]
10. [BP + disp]
11. [SI + disp]
12. [DI + disp]
Relative Based Indexed
13. [BX + SI + disp]
14. [BX + DI + disp]
15. [BP + SI + disp]
16. [BP + DI + disp]
Note that, the 8086 processor does not allow the use of
the BP register independently in the addressing mode,
however, it can be used along with the index registers
and/or displacement.
The 24 types of addressing modes in the 8086
processor can be grouped into the following categories.
1. Immediate Addressing Mode
2. Implicit Addressing Mode
3. Direct Addressing Mode
4. Indirect Addressing Mode
5. Register Addressing Mode
6. Register Indirect
 47

7. Based Indexed
8. Register Relative
9. Relative Based .Indexed
Phase of Execution
The phases of execution of the instruction are fetch,
decode, execute and write.
♦ The fetch phase performs fetching of the
instruction queue.
♦ The decode phase performs the decoding of the
instruction.
♦ The execute phase performs real (actual)
operations on the data.
♦ The write phase performs the operation of
storing and computed result at the destination.
Interrupt
Introduction
An interrupt refers to the change in state of the central
processing unit (CPU) as a result of a condition which is
external to the system or within the system. The terms
exception, trap, supervisor call, system call are the
synonyms of the term interrupt.
Intel defines interrupt as follows: -
 48

“Interrupts and exceptions are special kinds of control

transfer; they work somewhat like unprogrammed
CALLs. They after the normal program flow to handle an
external event or to report error or exceptional condition.
The difference between interrupts and exceptions is that
interrupts are used to handle asynchronous events
(processor does not wait for an event to occur) external
to the processor and exceptions handle conditions
detected by the processor itself in the course of executing
instructions”.

An interrupt is a hardware signal that informs the CPU to

temporarily halt its current activities and transfer control
to a program called interrupt handler or Interrupt Service
Routine (ISR). The CPU would have to constantly check
for external events in the absence of interrupts, which is
called as polling; with interrupts, the CPU can perform
some other operation and still respond to an event as
soon as it occurs.

Interrupts can be broadly categorized into three groups.

1. External Hardware Interrupts
2. Internal Hardware Interrupts
3. Software Interrupts
 49

External interrupts are requests from the peripheral

devices for processor action or attention. The external
interrupt is due to the activity external to the processor.
The internal interrupts are the exceptions, generated
internally due to the illegal or invalid operation inside the
processor, such as illegal opcode, address error (illegal
memory reference), arithmetic error (divide by zero,
overflow, etc.). Software interrupts are pseudo interrupts
providing a mechanism to implement the system services
which are accessed using the system calls. The source of
the software interrupt is the program, which accesses the
system service by executing a system call (Eg: INT
instruction in ×86 microprocessor).

Features of 8085 Microprocessors

1. It is 40 pin IC.
2. It has 8 pin for data.
3. It has 16 pin for address.
4. It can access 216 ≅ 64KB (65536 bytes) of
memory.
5. It use 3 MHz (3×106) clock frequency.
 50

6. It uses +5 volt as vcc and ground for proper

functioning.
7. It uses multiplexed address & data line.
8. It uses 8 registers for functioning. They are
A,B,C,D,E,H,L,M.
9. It is compatrible with its previous micro
processor 8080.
10. It is pin based microprocessor.
11. It is made up 6500 transistor.

Features of 8086 Microprocessor

1. It is 40 pin IC.
2. It is 16 bit Microprocessor.
3. It has 20 pin for address.
4. It can access 220 ≅ 1MB (1024 KB) of memory.
5. It is uses 5-10 MHz clock frequency.
6. It is architecture based Microprocessor.
7. Its architecture unit is divided into two parts.
 BIU (Bus Interface unit)
 EU (Execution unit)
8. It works in two modes.
9. Minimum
10. Maximum
11. It is made up of 29,000 transistor.
12. It is parallel pipelined Microprocessor.
13. It is uses one pin for vcc and two pin for
ground.
51