TN-46-05

GENERAL DDR SDRAM FUNCTIONALITY

TECHNICAL GENERAL DDR SDRAM

NOTE
INTRODUCTION
The migration from single data rate synchronous
DRAM (SDR) to double data rate synchronous DRAM
(DDR) memory is upon us. Although there are many
similarities, DDR technology also provides notable
product enhancements.
In general, double data rate memory provides
source-synchronous data capture at a rate of twice the
clock frequency. Therefore, a DDR266 device with a
clock frequency of 133 MHz has a peak data transfer
rate of 266 Mb/s or 2.1 GB/s for a x64 DIMM. This is
accomplished by utilizing a 2n-prefetch architecture
where the internal data bus is twice the width of the
external data bus and data capture occurs twice per
clock cycle. To provide high-speed signal integrity, the
DDR SDRAM utilizes a bidirectional data strobe,
SSTL_2 interface with differential inputs and clocks.
The objective of this technical note is to provide an
overview of the 2n-prefetch architecture, a strobe-based
data bus, and the SSTL_2 interface used with DDR
SDRAM. It will also highlight the functional differences
between SDR and the improved DDR memory technol-
ogy. For detailed design and timing criteria for DDR
SDRAM-based systems, see Micron's DDR SDRAM data
sheets.(http://www.micron.com/ddrsdram.)
FUNCTIONALITY
Table of Contents
DDR vs. SDR Functionality ............................... 2
Table 1: SDR to DDR Quick Reference ................. 1
Figure 1: Functional Block Diagram .................... 2
Figure 4: Example of DDR Command Bus .......... 3
2n-Prefetch Architecture ................................. 3
Figure 2: Block Diagram 2n-Prefetch READ ........ 3
Figure 3: Block Diagram 2n-Prefetch WRITE ....... 3
Minimum Time Slots ........................................ 3
Figure 5: 2n-Prefetch READ Slot Timing ............. 4
Figure 6: 2n-Prefetch WRITE Slot Timing ............ 5
Figure 7: READ Command Slots ........................... 6
Strobe-Based Data Bus ..................................... 4
Preamble and Postamble ................................. 7
Figure 8: DQS READ Postamble and Preamble ... 7
Figure 9: DQS WRITE Postamble and Preamble . 8
SSTL_2 Interface ............................................... 9
Drivers and Receivers ...................................... 9
Figure 10: Typical LVCMOS Receiver ................... 9
Figure 11: Typical SSTL_2 Receiver ...................... 9
I/O Signaling .................................................... 10
Figure 12: Typical SSTL_2 Interface and
Input Levels ....................................... 10
Clock Inputs ..................................................... 11
Figure 13: SSTL_2 Clocks ..................................... 11
Summary ......................................................... 11

Table 1
SDR to DDR Quick Reference
PARAMETER SDR DDR NOTES
DQM Yes No Used for write data mask and read OE
DM (Data Mask) No Yes Replaces DQM, used to mask write data only
DQS (Data Strobe) No Yes New, used to capture data
CK# (System Clock) No Yes New, DDR utilizes differential clocks
VREF No Yes Reference voltage for differential inputs (1/2 VDD)
VDD and VDDQ 3.3 Volts 2.5 Volts Reduced supply and power for DDR
Signal Interface LVTTL SSTL_2 DDR utilizes differential I/O
Output Drive Fixed Variable x16 DDR devices offer a reduced drive option
Data Rate 1x Clock 2x Clock Data transfer is twice the clock rate for DDR
Architecture Synchronous Source-Synchronous DDR utilizes a bidirectional data strobe

General DDR SDRAM Functionality

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©2001, Micron Technology, Inc.
 TN-46-05
GENERAL DDR SDRAM FUNCTIONALITY

Figure 1
Functional Block Diagram
2 Meg x 4 Memory Array with SDR and DDR Interface

CKE
CK# 1 1
DQM
CK
SDR I/O Interface

CS# CONTROL
COMMAND

LOGIC
DECODE

WE# DATA
Generic Memory Array 4 OUTPUT
BANK3
CAS# BANK2 DQM REGISTER
RAS# BANK1 Not Used for DDR DQM

(SDR) DQ0-
Internal Data Bus 4 4 DQ3

REFRESH DATA
12
MODE REGISTERS COUNTER INPUT
ROW- 12 BANK0
ROW- REGISTER
ADDRESS BANK0
MUX ADDRESS MEMORY 4
12 4,096
LATCH ARRAY
12 AND (4,096 x 1,024 x 8)
DECODER

SENSE AMPLIFIERS
CK
4,096 DDR I/O Interface

DATA DLL
Internal Data Bus
4
2
I/O GATING x4 for SDR 8 4
READ
x8 for DDR MUX
A0-A11, ADDRESS BANK LATCH 4 DRVRS
BA0, BA1 14
REGISTER CONTROL DQS 1
2 LOGIC GENERATOR
1,024 DQ0-
(x8) DQ3, DM
Internal Data Bus COL0
DQS
(DDR) INPUT
8 REGISTERS
COLUMN DQS
DECODER 1 1
MASK
COLUMN- 1
ADDRESS WRITE 1 1
11 8 FIFO 2
COUNTER/
LATCH AND RCVRS
COL0 4 4
DRIVERS
8 4
1 Not Used for SDR 4 4
ck ck
out in DATA

COL0
CK
1

DDR VS. SDR FUNCTIONALITY

SDR SDRAM is well established and generally un- employs a 2n-prefetch architecture, where the inter-
derstood, so questions tend to focus where DDR dif- nal data bus is twice the width of the external bus. This
fers from SDR. allows the internal memory cell to pass data to the I/O
An examination of the 32 Meg x 4 SDR and DDR buffers in pairs. With DDR, there is no output enable
functional block diagrams reveals that the memory core for READ operations, but DDR does support a BURST
is essentially the same (see Figure 1). Both have an TERMINATE command to quickly end a READ in pro-
identical addressing and command control interface; cess. During a WRITE operation, the DM signal is avail-
both have a four-bank memory array; and both incor- able to allow the masking of nonvalid write data.
porate the same refresh requirements. The fundamen- The DDR command bus consists of a clock enable,
tal differences are found in the data interface. chip select, row and column addresses, bank address,
The SDR memory data interface is a fully synchro- and a write enable as shown in Figure 4. Commands are
nous design where the data is only captured on the entered on the positive edges of clock, and data occurs
positive clock edge. The internal bus is the same width on both positive and negative edges of the clock.
as the external data bus and data latches into the inter- The double data rate memory utilizes a differential
nal memory array sequentially as it passes through the pair for the system clock and therefore will have both a
I/O buffers. SDR memory also supports a DQM signal true clock (CK) and complementary clock (CK#) signal.
that acts as a data mask during a WRITE operation or The positive clock edge for DDR refers to the point
an output enable for a READ. where the rising clock signal crosses with the falling
The DDR memory data is a true source-synchro- complementary clock signal, and the term negative
nous design, where the data is captured twice per clock clock edge indicates the transition of the falling clock
cycle with a bidirectional data strobe. This architecture and rising complementary clock signals.

General DDR SDRAM Functionality

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©2001, Micron Technology, Inc.
 TN-46-05
GENERAL DDR SDRAM FUNCTIONALITY
2n-Prefetch Architecture Figure 4
The term DDR (or DDRI) should be specifically as- Example of the DDR Command Bus
sociated with the 2n-prefetch device, as future memory
designs (DDRII) will use the 4n-prefetch architecture. for a WRITE Cycle
To the DRAM vendor, 2n-prefetch means that the
internal data bus can be twice the width of the external CK#
data bus, and therefore the internal column access CK
frequency can be half of the external data transfer rate.
That is, for each single read access cycle internal to the CKE HIGH
device, two external data words are provided (as shown
in Figure 2). Similarly, two external data words written CS#
to the device are internally combined and written in
one internal access (as shown in Figure 3).
RAS#

Figure 2
CAS#
Simplified Block Diagram
of 2n-Prefetch READ
WE#
n-bit
data DQS
n-bit
Data
Register
2n-bit n-bit data
From data D0 plus DQS All DQ
A0–Ai CA
DRAM MUX Q and DQS
Core D1 C Outputs

n-bit
Data CLKD
A0–Ai RA
Register
n-bit DQS
data
EN AP
A10
To the user, from a high-level view, 2n-prefetch DIS AP
means that data accesses occur in pairs; i.e., a single
read access fetches two data words; and for a single
BA0, 1 BA
write access, two data words (and/or data mask bits)
must be provided. This affects both the minimum burst
size and nonminimum burst interruptions. The mini- CA = Column Address
mum burst size of a 2n-prefetch architecture is two RA = Row Address
external data transfers. Ai = Most Significant Address
BA = Bank Address
EN AP = Enable Auto Precharge
Figure 3 DIS AP = Disable Auto Precharge
Simplified Block Diagram of
2n-Prefetch WRITE DON’T CARE

n-bit
data Minimum Time Slots
DQ0-DQi D Q
For READs, the controller can choose to ignore ei-
n-bit
Data ther of the two words, but the time slots for both will be
Register
occupied (see Figure 5). Similarly, for WRITEs, the con-
troller can mask either of the two words, but again, the
2n-bit time slots are occupied (see Figure 6). For each READ or
data
To
D Q D Q DRAM
WRITE command (and column address) applied, two
n-bit
Data
n-bit 2n-bit
Data
Core
data words are provided. Because the device is double
data
Register Register data rate as well as 2n-prefetch, a minimum of two data
DQS
words is optimal (since commands cannot be applied
CK more frequently).

General DDR SDRAM Functionality

TN4605.p65 – Rev. A; Pub. 7/01 3 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.

GENERAL DDR SDRAM FUNCTIONALITY
Figure 5
Minimum Data Time Slot for 2n-Prefetch READ
CK#
CK
COMMAND READ READ READ
Bank, Bank, Bank,
ADDRESS Col n Col x Col b
CL = 2
DQS
DO
DQ n n'
NOTES: 1. DO n, etc. = data-out from column n, etc.
2. n', etc. = the next data-out following DO n, etc.,
according to the programmed burst order.
3. Burst length = 2, 4, or 8 in cases shown.
4. READs are to active rows in any banks.
5. Shown with nominal tAC and tDQSQ.
6. The controller wants the first of two words for the first
READ command, both words for the second, and the
second of two words for the third.
For nonminimum READ bursts (four or eight words),
it helps to associate each positive clock edge with a pair
of data words. This way, interruptions of READ com-
mands are easily understood. For example, with a burst
length of eight, a READ command followed by three
uninterrupting commands is needed to access the en-
tire burst. If an interrupting command is applied at the
first positive clock edge following the READ command,
only two words will be accessed; if an interrupting com-
mand is applied at the second positive clock edge fol-
lowing the READ command, only four words will be
accessed, etc., (see Figure 7).
The concept of associating pairs of data with posi-
tive clock edges applies for WRITEs as well. However, to
fully understand the masking and interrupting of write
data, WRITE latency and strobe-based data bus tim-
ing must be considered. For now it should be noted
that the positive clock edges of interest for WRITEs are
different than those for READs. This is because of dif-
ferences in latencies and because the array access oc-
curs at the beginning of a READ operation but at the
end of a WRITE operation. In fact, the relevant edges
depend on what the interrupting command is, as we
will be shown later.
General DDR SDRAM Functionality
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TN-46-05
READ NOP NOP
Bank,
Col g
DO DO DO DO DO DO
x x' b b' g
DON’T CARE (to DRAM)
DON'T CARE (to controller)
Strobe-Based Data Bus
In a purely synchronous system, data output and
capture are referenced to a common, free-running sys-
tem clock. However, the maximum data rate for such a
system is reached when the sum of output access time
and flight time approaches the bit time (the reciprocal
of the data rate). Although generating delayed clocks
for early data launch and/or late data capture will allow
for increased data rate, these techniques do not ac-
count for the fact that the data valid window (or data
eye) moves relative to any fixed clock signal, due to
changes in temperature, voltage, or loading. So, to al-
low for even higher data rates, data strobe signals were
added to DDR devices. The data strobes are nonfree-
running signals driven by the device, which is driving
the data signals (the controller for WRITEs, the DRAMs
for READs). At the DRAM device level, for READs, the
data strobe (DQS) signals are effectively additional
data outputs (DQ) with a predetermined pattern; for
WRITEs, the strobe signals are used as clocks to cap-
ture the corresponding input data. At the board level,
the strobe signals have identical loading to data sig-
nals and should be routed similarly.
©2001, Micron Technology, Inc.
 TN-46-05
GENERAL DDR SDRAM FUNCTIONALITY

Figure 6
Minimum Data Time Slot for 2n-Prefetch WRITE

CK#
CK

COMMAND WRITE WRITE WRITE WRITE WRITE

ADDRESS Bank, Bank, Bank, Bank, Bank,

Col b Col x Col n Col a Col g

tDQSS (NOM)

DQS

DI DI DI DI DI DI
DQ b x x' n' a a'

DM

DON’T CARE (to DRAM)

NOTE: 1. DI b, etc. = data-in for column b, etc.

2. b', etc. = the next data-in following DI b, etc., according to the programmed burst order.
3. Programmed burst length = 2, 4, or 8 in cases shown.
4. Each WRITE command may be to any bank.
5. The controller wants to write the first of two words for the first WRITE command,
both words for the second, and the second of two words for the third.

At this point, it may be helpful to digress for a mo-
ment to cover the ratio of strobe-to-data signals. This
technical note focuses on typical desktop PC main
memory applications, which use x64 DIMMs con-
structed with x8 or x16 DRAM devices. Controllers for
these applications will be designed with one strobe per
byte; i.e., there is one strobe on each x8 DRAM device
and two strobes on each x16 device.
Other types of applications may use different strobe-
to-data ratios. For example, servers using x72 DIMMs
based on x4 components require controllers with one
strobe per four bits, and controllers for graphics or com-
munications applications might use one to four strobes
per 32 bits. Creative techniques can be utilized to mix
and match different strobe-to-data ratios in a system,
but those will not be covered here. Because of the focus
of this technical note, a strobe-to-data ratio of one per
byte is used. The timing and calculations described
apply independently to each group of signals.
For READs, the data strobe signals are edge-aligned
with the data signals, meaning that all data and data
strobes are clocked out of the device by the same inter-
nal clock signal, and all will transition at the outputs at
nominally the same time. The controller will internally
delay the received strobe to the center of the received
data eye.
For WRITEs, the controller must provide the data
strobes center-aligned relative to data. That is, strobe
transitions occur nominally 90 degrees (relative to the
clock frequency) out of phase with data transitions.
The DRAM device uses internally matched routing for
the strobes and data such that the strobes can be used
directly to capture input data. Note that the reason
READs and WRITEs use a different alignment scheme
is so that the delay circuitry can be centralized in one
place (the controller) and does not have to be repli-
cated in every DRAM device in the system. This ap-
proach is expected to be carried forward to future gen-
erations of DDR to leverage the infrastructure now be-
ing established.

General DDR SDRAM Functionality

TN4605.p65 – Rev. A; Pub. 7/01 5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
 TN-46-05
GENERAL DDR SDRAM FUNCTIONALITY

Figure 7
Relating Command Slots to Read Data

(Pair 1) Pair 2 Pair 3 Pair 4

CK#
CK

COMMAND READ n NOP NOP NOP NOP NOP NOP

CL = 2

DO
DQ n

PAIR 1 PAIR 2 PAIR 3 PAIR 4

COMMAND READ n NOP NOP BST NOP NOP

CL = 2

DO
DQ n

COMMAND READ n NOP BST NOP NOP NOP

CL = 2

DO
DQ n

COMMAND READ n BST NOP NOP NOP NOP

CL = 2

DO
DQ n

NOTE: 1. DO n = data-out from column n. DON’T CARE

2. NOP commands represent any valid uninterrupting commands.
3. BST commands represent any valid interrupting commands.
4. Controlling command slots are noted for each pair; if an interrupting command is
applied in the controlling command slot for a given data word pair, that pair will
not be read out.
5. Pair 1 is always read out (i.e., is the minimum burst) when a READ command is applied.

General DDR SDRAM Functionality

TN4605.p65 – Rev. A; Pub. 7/01 6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.

GENERAL DDR SDRAM FUNCTIONALITY
Preamble and Postamble
The data strobe timing pattern consists of a
preamble, toggling, and postamble portion. Figure 8
shows the strobe pattern and alignment to data for
READs, and Figure 9 shows the same for WRITEs. The
preamble portion provides a timing window for the
receiving device to enable its data capture circuitry
while a known/valid level is present on the strobe sig-
nal, thus avoiding false triggers of the capture circuit.
Following the preamble, the strobes will toggle at the
same frequency as the clock signal for the duration of
the data burst. Each high transition and each low tran-
sition is associated with one data transfer. The low time
following the last transition is known as the postamble.
Most controllers have an internal clock running at twice
the memory clock frequency, so generating a strobe
shifted 90 degrees relative to data is fairly straightfor-
ward. Typically, data and strobe are clocked out using
the 2x clock, with data being driven by edges of one
polarity, and the strobe being driven by edges of the
opposite polarity. Delaying the incoming strobe for
READs is more involved and will be covered in detail in
an independent technical note.
TN-46-05
For read-to-read data bus transitions where the
READs are from different physical banks of DRAMs, or
read-to-write data bus transitions (i.e., transitions from
one device driving the data bus to another device driv-
ing the data bus), there is a hand-off of strobe signals,
and the full strobe pattern (including preambles and
postambles) is needed from each source. The conser-
vative approach is to space requests such that the
postamble from the first source completes before the
preamble from the second source begins. Consecutive
READ bursts from the same bank of DRAMs are
achieved by extending the toggling portion of the data
strobe pattern. (A postamble and preamble are not
needed between consecutive READ bursts from the
same source.) Consecutive WRITE bursts are also pos-
sible, even if to different physical banks of DRAMs.
This is a little less intuitive because, unlike the case of
consecutive READs from the same source, the destina-
tion DRAMs for the second consecutive WRITE burst
have no way of knowing that a first WRITE burst to
another bank of DRAMs occurred. This means that the
DRAMs must be capable of accepting different pre-
amble timing, depending on whether there was prior
write activity on the bus.

Figure 8
DQS Pattern for READ Showing Preamble and Postamble

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK

COMMAND READ n NOP NOP NOP NOP NOP

Preamble Postamble

DQS

DO
DQ n

NOTE: 1. DO n = data-out from column n.

DON’T CARE
2. Burst length = 4, CAS latency = 2.
3. Three subsequent elements of data-out appear in the programmed order following DO n.
4. Shown with tAC and tDQSQ = 0 for illustration.

General DDR SDRAM Functionality

TN4605.p65 – Rev. A; Pub. 7/01 7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
 TN-46-05
GENERAL DDR SDRAM FUNCTIONALITY

Figure 9
DQS Pattern for WRITE Showing Preamble and Postamble

T0 T1 T2 T3 T4 T5 T6
CK#
CK

COMMAND WRITE b NOP NOP NOP

Preamble Postamble

DQS

DQ DI
b

DON’T CARE
NOTE: 1. DI b = data-in for column b.
2. Three subsequent elements of data-in
are applied in the programmed order following DI b.
3. A burst of four is shown.
4. Shown with nominal tDQSS and without DM bits
for illustration.

General DDR SDRAM Functionality

TN4605.p65 – Rev. A; Pub. 7/01 8 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.

GENERAL DDR SDRAM FUNCTIONALITY
SSTL_2 Interface
Previous SDR memory technology used LVTTL and
a fixed voltage level for signal interface. DDR SDRAM
utilizes differential inputs and a reference voltage for
all interface signals. This interface is called SSTL_2,
which stands for stub series terminated logic for 2.5
volts. SSTL_2 is an industry standard defined by JEDEC
document #EIA/JESD8-9. Although some DRAMs will
support a reduced drive output, most will comply with
the SSTL_2 Class II drive levels.
Benefits to the SSTL_2 interface include symmetri-
cal low and high logic levels, improved signal integrity,
and better noise immunity, as the input levels track
minor variations in the supply voltage.
TN-46-05
Driver and Receivers
The output buffer and input receivers have changed
from LVTTL to SSTL_2. The output buffer logic has not
changed, but the VDDQ has moved from 3.3 volts to 2.5
volts for DDR.
The input receivers have migrated from an n and p
channel stacked gate to a differential pair common
source amp. The more complex receiver used in DDR
provides greater bandwidth and a smaller variation
over temperature to increase margin to the tighter in-
put signaling. VREF has been added to improve VDD
margin over temperature.

Figure 10 Figure 11
Typical LVCMOS Receiver Typical SSTL_2 Receiver

VDDQ = 2.5V

VDDQ = 3.3V

VOUT

In Out VREF In

VSS

VSS

General DDR SDRAM Functionality

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©2001, Micron Technology, Inc.

GENERAL DDR SDRAM FUNCTIONALITY
I/O Signaling
The typical SSTL_2 interface includes series termi-
nation and a pull-up to the termination voltage (refer
to Figure 12). The SSTL_2 interface uses a reference
voltage and differential input to determine the logic
levels. The reference voltage is defined to be half of the
supply voltage and the termination voltage equals
the reference voltage. (VDD = 2.5 volts, VREF = VTT = 1.25
volts).
TN-46-05
There are both DC and AC input logic levels for the
SSTL_2 interface. In general, the DRAM will start to
switch to the new logic level when the input signal
transitions through the target DC level and it will latch
when the input signal crosses through the final AC
input level. Once the logic level has been latched, it will
remain latched until the input signal transitions back
through the DC level. Refer to Figure 12 for a typical
SSTL_2 input signal.

Figure 12
Typical SSTL_2 Interface and Input Levels

VIH(AC)

VTT

RT VIH(DC)
RS

VIN
+
VOUT VREF
-
VREF
Driver Receiver

VIL(DC)

VIL(AC)

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(0°C ≤ TA ≤ +70°C; VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V)

PARAMETER/CONDITION SYMBOL MIN MAX UNITS

I/O Reference Voltage VREF 0.49 x VDDQ 0.51 x VDDQ V
I/O Termination Voltage (system) VTT VREF - 0.04 VREF + 0.04 V
Input High (Logic 1) Voltage VIH(DC) VREF + 0.15 VDD + 0.3 V
Input Low (Logic 0) Voltage VIL(DC) -0.3 VREF - 0.15 V
Input High (Logic 1) AC Voltage VIH(AC) VREF + 0.310 – V
Input Low (Logic 0) AC Voltage VIL(AC) – VREF - 0.310 V

General DDR SDRAM Functionality

TN4605.p65 – Rev. A; Pub. 7/01 10 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.

GENERAL DDR SDRAM FUNCTIONALITY
Clock Inputs
To increase accuracy caused by clock jitter, a differ-
ential clock was added to DDR. SDR devices use the
midpoint of the rising clock edge to latch data and thus
are exposed to drift. DDR uses the crossing point of
CK and CK#. Using the crossing point instead of the
midpoint helps negate the affects of jitter and increase
margins. The clocks used for DDR also operate within a
set of parameters, which are defined by JEDEC (see
Figure 13).
TN-46-05
SUMMARY
The similarities between SDR and DDR SDRAM pro-
vide the DRAM manufacturer cost advantages and as-
sure high production yields. These similarities also help
the designer to better understand DDR and allow the
most optimal design techniques from previous designs
to be incorporated into the new DDR platforms. Al-
though the addressing schemes, layout requirements,
and device configurations are much the same for DDR,
the performance gains are remarkable. For example,
the power consumption for DDR is significantly less
than for a comparable SDR device, yet peak transfer
rates can exceed 2.1 GB/s for a standard x64 DDR DIMM.

Figure 13
Typical SSTL_2 Clocks

2.80V Maximum Clock Level

CK

1.45V X
1.25V VMP(DC) VID(DC)
VIX(DC) VID(AC)
1.05V X

CK#

- 0.30V Minimum Clock Level

Reference: Micron DesignLine, Volume 8, Issue 3 (3Q99)

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General DDR SDRAM Functionality

TN4605.p65 – Rev. A; Pub. 7/01 11 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.