JIET GROUP OF INSTITUTIONS

(Department of Electronics & Communication Engineering)

II B. TECH. (III SEM ECE) 3EC2: Electronics Devices & Circuits
UNIT1: SEMICONDUCTOR PHYSICS
TUTORIAL SHEET: 1
___________________________________________________
Q.1 Explain Hall Effect and its applications. (R.U. 2004)

Q.2 Explain why a contact potential is developed across an open circuited pn junction.
Also specify the parameters on which the contact potential is dependent. (R.U. 2003)

Q.3 By what percentage does the conductivity of intrinsic Ge at room temperature

(3000K) increase per degree rise in temperature ? EGO = 0.785 EV at T= 3000K.
(RTU 2009)

Q.4 Explain diffusion in semiconductors with suitable diagram and mathematical

relation. (R.U. 2004)

Q.5 Differentiate between metals, insulators and semiconductors using energy band
diagram. (R.U. 2004)

Q.6 What do you understand by intrinsic and extrinsic semiconductors. (R.U. 2004)

Q.7 Explain Energy band diagram and Fermi Dirac distributions. (R.U. 2003)

Q.8 Explain carrier lifetime and continuity equation with suitable diagram and
mathematical relation. (RTU 2010,2009,R.U.2006)

Q.9 In n-type semiconductor, the Fermi level lies 0.30eV below the conduction band at
3000K. If the temperature is increased to 330 0 K. find the new position of Fermi level.

Q10.Derive the expressions for number of holes in valence band and Fermi level in an
intrinsic (RTU 2009)

Q11.Write the main properties of semiconductors. Draw and explain energy band
diagrams for intrinsic P type and N type semiconductor. (RTU 2010)

Q12. A rectangular semiconductor specimen , 2mm wide and 1mm thick, gives a Hall
voltage of 1mV is developed . Find the magnetic field and Hall field. (RTU 2010)

Q13. In n-type semiconductor, the Fermi level lies 0.2eV below the conduction band . If
the concentration of donor atoms is increased by a factor 4 times. find the new position of
Fermi level. Assume KT=0.025eV. (RTU 2010)
 TUTORIAL SHEET - II
UNIT II: JUNCTION DIODES

Q1. What are Voltage Multipliers? Expain with required circuits. (RTU 2010)
Q2. Explain the working principle of a voltage quadrupler with neat diagram
(RTU 2009)
Q3. Explain the usefulness of DC Load line. What are its intercepts on x- axis & y-axis.
Q4. What is a comparator circuit? How does such a circuit differ from a clipping
circuit.
Q5. Determine the output waveform for circuit given in figure a:
a. When input is (i) Sine wave of peak amplitude of 15V & (ii)a square wav e as
shown in fig b
b. Assume D to be an ideal Si diode.

Q6. What is clipping and clamping ? Describe their application. (RTU 2009)
Q7. Consider a circuit consisting of a diode D, a resistance R, and a signal source vi in
series. Define:
a. Static characteristics
b. Dynamic characteristics
c. Transfer characteristics
a. Correlation between b & c

Q7. Differentiate between zener breakdown and avalanche breakdown. (RTU 2009)

Q8. With the help of a suitable circuit diagram explain the operation of full wave voltage
 doubler. (R.U. 2005)

Q9. Is it possible to construct a transistor by simply connecting two separate(isolate)

diodes in series opposing? Comment (R.U. 2004)

Q10. Draw the output waveforms of the following circuits and explain the working also:

Q11. Explain construction , characteristics and working principle of UJT . Explain the
application of UJT as a relaxation oscillator. (RTU 2010,2009)

Q12. Find minimum and maximum load currents for the given zener diode circuit (i) to
maintain lad regulation . what is the minimum value of RL that can be used ? Here Vz =
12V , Zener impedance = 0 , IZ min = 1mA, IZ max=50mA. (RTU 2010)

TUTORIAL SHEET - III

 UNIT III: BIPOLAR JUNCTION TRANSISTOR

Q1.Explain the h-parameter model of a transistor at low frequencies and derive the
formulae

a. Current gain

b. Voltage gain

c. Input impedance

Q2. Draw and explain self bias circuit and why such a circuit is improvement over
fixed bias circuit.

Q3. Define stability factor and obtain an expression for fixed bias circuit.

Q4.Write short notes on

a. compensation techniques (RTU 2009)

b. stabilization techniques

Q5. Explain the Ebbers-Moll Model for a pnp BJT. (RTU 2009,RU. 2001)
Q6. Explain thermal resistance and thermal stability of a power transistor circuit.
What is the power dissipation condition to prevent thermal runaway
(RTU 2010,2009,R.U. 2002)
Q7. Explain why self bias circuit is not suitable for biasing the integrated circuits.
Suggest and describe a two transistor technique to bias linear integrated circuits.
(R.U. 2002)
Q8. Describe an emitter coupled differential amplifier by giving suitable circuit diagram.
(R.U.
2001,2002)
Q9. Describe the construction and working of a Bipolar Junction Transistor. Explain the
concept of Early Effect with the aid of plots of potential and minority concentration
throughout the base region.
Q10. Plot the input and output characteristics of Common Collector configuration for a
Bipolar Junction Transistor.
 TUTORIAL SHEET - IV
UNIT IV: JFET & MOSFET

Q1.Draw the circuit of JFET CS amplifier using fixed bias and describe the working
of biasing circuit.

Q2. A voltage source Vs of internal resistance Rs =500Ω drives a CE amplifier

stage using a load resistance RL =2000Ω . The h parameters are
hie =1100Ω, hoe =25µA/V,
hfe =50, hre =2.5x10-4
Compute current gain Ai, input resistance Ri,
voltage gain Av, output resistance Ro using exact analysis. Repeat the calculation
using approximate analysis and compute the percentage error in Ai, Ri, Av, Ro.

Q3.Explain how FET can be used as VVR in detail. (RTU 2010)

Q4.What does thermal stability mean? Derive the condition for thermal stability.

Q5.Draw a family of CS drain characteristics of an n-channel JFET. Explain the

shape of these curves qualitatively. Define the pinch off voltage Vp.

Q6.By deducing the expression for a voltage gain, show the effect of source bypass
capacitance in a common source FET amplifier stage. (R.U. 2002)

Q7.Describe the carrier transportation in a n-channel depletion type MOSFET using

suitable diagram and also explain qualitatively its drain characteristics.

Q8.Explain Biasing techniques of MOSFET. (R.U. 2002)

Q10. Derive the low frequency voltage gain of common source amplifier with
unbypassed source resistance. (R.U 2002)
 TUTORIAL SHEET - V
UNIT V: SMALL SIGNAL AMPLIFIERS AT LOW FREQUENCY

Q1. Draw and explain the circuit of Darlington Emitter Follower.

(RU. 2007)

Q2. Draw the equivalent circuit of a two-stage RC –coupled amplifier and

analyze it to obtain the expression for gain-bandwidth product. (RTU 2010,R.U.
2005,2003)

Q3. What is significance of “Piece to Piece Variation”? Which characteristic

of JFET shows Piece to Piece Variation ?

Q4. What are important small signal parameters of JFET. Can JFET be
modeled with h-parameter like BJT. Justify. ( RTU
2009,R.U. 2001)

Q5.Draw equivalent circuit of a CS amplifier and derive the expression voltage gain

(RTU 2010)

Q6.State Miller’s Theorem and its dual with an aid of circuit diagram.

(RTU 2009,2010,RU 2001)

Q7. Draw a CE (first ) stage cascaded with CC (second ) stage .In terms of A v1,
Av2, Ai1, Ai2 determine the expression for
 a. the resultant voltage gain Av

b. the resultant current gain Ai.

Q8. Explain why Darlington emitter follower has higher input impedance than
a single stage emitter follower.

Q9. In the CE amplifier shown in figure IE=1mA, RE=1k ,β=49.Find the values
of R1 and R2 such that the stability factor does not exceed 5.Assume VCC=5V and
VBE= 0V .

Q10.Discuss biasing problem in Darlington pair. How is it solved? Explain

bootstrapping principle and how effectively it can be used in Darlington? (RTU 2010)

Q11. Give the ac analysis of a dual in balanced output differential amplifier.

(RTU 2009)

Q12.Differentiate between BJT and FET. (RTU 2009)