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com

email : support@gateforum.com Phone : 080 - 41310203

Disclaimer:

The accuracy of the question paper is not guaranteed, nor can you expect

the same type of question paper in 2006. As a matter of fact, the year before, they

had asked to draw the first angle projection of an object. This question paper is

just to give you a feel of the topics that are important for the test – Electronic

circuits(Op- amps), Digital, Electrical Machines(motors), communication,

switching, may be u can include power electronics ,…

Note: You should take with you the call letter or your gate score card as a proof of

identity to appear for the test. The last date for buying iisc application ends in a few

days after the gate results are out. Please check the iisc website periodically after

writing the gate exam.

Test – 2005

April 18

Questions from 1-20 carry 1 mark (-0.5 marks for wrong answer)

a. input current and output current

b. power dissipation

c.

d.

100 micro watts. The maximum dissipation in the first stage can be:

a. 50 micro watt

b. 25 micro watt

c. 10 micro wa tt

d. 75 micro watt

gravity as 10m/s2. Efficiency of motor is 80%. The terminal voltage of the motor

is 10V. Find the armature current.

a.

b.

c.

d.

a. Induction motor

b. Stepper motor

c. DC motor with cam and lever

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email : support@gateforum.com Phone : 080 - 41310203

d. Synchronous motor

a. b. c. d.

6. This question was from 8086 which I least understood. Info regarding the

question is:

Instructions – MOV, JUMP, JC, ADD

Registers – AX, BX, ES, DS

The question was to find where a particular data will be stored at the end of the

execution of the program.

a. b. c. d.

need to calculate the effective output capacitance.

a. b. c. d.

transmits at 1Mbps and when ‘off’ at 0Mbps. Source ‘on’ time to ‘off’ is 1:9.

Number sources that share the transmission medium for ckt switching and packet

switching, respectively is:

a. 1, 10

b. 10,1

c. 10,10

d. 10,100

a. OR

b. NOR

c. AND

d. NAND

a. N

b. 2N

c. log2N

d. 2N

a. power and time

b. armature current.

c.

d.

12. The duty cycle of a transmitter is 10%. The average power is 1KW. The peak

power is

a. b. c. d.

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email : support@gateforum.com Phone : 080 - 41310203

13. In Freq. mod. when the modulating frequency is doubled the phase deviation

is

a. doubled

b. unchanged

c.

d.

14. A 4 bit full adder has a delay of 4ns. 2 synchronous counters feed the full

adder. The maximum clock frequency of the counter is:

a. 125 MHz

b. 250 MHz

c. 500 MHz

d. the highest frequency the counter can work.

15. There is a rod between two movable surfaces. The rod can slide over the

surface. Find the angle at which H is twice V.

21. What is the input offset voltage drift if the output voltage is 1V at 25 deg

celcius and 1.01V at 50 deg celcius.

22. Draw a simple circuit to light the led when 5 occurs. I4 is the MSB.

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email : support@gateforum.com Phone : 080 - 41310203

23. There is a triangular wave generator. Draw the voltage waveforms at nodes A,

B, C.

24. Find the currents I1 and I2 when V0 is short circuited to ground. The circuit

was a series voltage regulator using an op amp and transistors, with short circuit

protection. I1 was op amp output current and I2 was the current through the short.

1. Aluminium – Reinforcement

2. Glass epoxy – corrosion protection

3. cyano acrilate – printed circuit board

4. poly acril…. - …

5. silver - ….

6. gold - Heat sink

7. glass fiber - electrical conductor

27. In the following circuit diagram d1,d2 and d3 are delay elements. The AND

gate has no propagation delay. State the condition under which glitch occurs at the

output(static zero hazard), for the inputs given below.

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email : support@gateforum.com Phone : 080 - 41310203

28. A number of users share a channel. Each user transmits with a probability of

‘p’.

1. What is the probability of successful transmission is there are 10 users.

2. To maximize the above (for 10 users) what should be ‘p’.

3. What is the expected number of users transmitting at a time for this ‘p’.

voltage sources. Find d1 and d2 in terms of V1 and V2 for V0 to be zero.

30. The last question involved calculation of the following for a class A amplifier.

1. conversion efficiency for a given Q – point.

2. power dissipation.

3. bla bla bla

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email : support@gateforum.com Phone : 080 - 41310203

2. The power dissipation of a CMOS gate is proportional to frequency of

operation. In a ripple counter the frequency gets progressively halved.

Hence total power dissipation

P = 100 = const. * ( 1 + 0.5 + 0.52 + 0.53 + 0.54 + 0.55 + ………)

Const. = 50

Thus power dissipation in the first stage is 50 micro watt, second 25, third 12.5

and so on.

Power= mgh/t = mgv = 8W

Efficiency = 0.8

Required power = mgv/0.8 = 10W

Armature current = required power/ voltage = 10/10=1A

22. this question is a googly. You should not design a circuit to produce a 1 when

five occurs. Rather you should design the circuit to produce a 0 when 5 occurs. It

might also be safe to include a current limiting resistor.

29. capacitance = A / d.

Current through a capacitor = c dv/dt

Current thro the two capacitors should cancel each other(they should be equal)

Interview

In the interview the questions asked were from the project, digital electronics, op

amps, computer networks osi layers and their functions, basic math. The selection

will be based on the combined performance in the test and interview. You are

required bring with you the gate score card, college and school marksheets.

Selected for interview – 156

Selected for the course – 29

Request: Those who attend the edt test in 2006, please try to make a soft copy of

the question paper and pass it on to your juniors so that they will have a better

opportunity to get through the test.

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