designideas

Edited By Charles H Small

and Fran Granville

readerS SOLVE DESIGN PROBLEMS

Build a complete industrial-ADC D Is Inside

interface using a microcontroller 66 Circuit guards amplifier outputs
against overvoltage
and a sigma-delta modulator 70 Isolated circuit monitors ac line
Patrick Weber and Craig Windish, 72 I2C interface has galvanic
Siemens Energy and Automation, Pittsburgh, PA isolation, wired-OR capability,


Designers commonly use 0- to
20-mA, 0 to 10V isolated in-
puts for industrial-application-control
signals. A combination of isolated sup-
plies, the built-in isolation of an Analog
Devices (www.analog.com) AD7400
sigma-delta modulator, and a Texas In-
struments (www.ti.com) MSP430 mi-
crocontroller creates a design for in-
dustrial designers requiring complete,
isolated, and robust analog-signal in-
terfaces. A precise signal-condition-
ing circuit generates the small differen-
tial voltage that the AD7400 requires
(Figure 1). The circuit generates the
required 200-mV differential voltage.
For clarity, the figure omits overvolt-
age diodes and protection circuits.
A 0- to 20-mA current loop con-
verts to a voltage through a properly
scaled resistor, R2, and enters a preci-
sion operational amplifier. The signal
level, which connects to the negative
input, gets a positive offset by main-
improved noise margin
EWhat are your design problems
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Design Ideas to edndesignideas@
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taining constant voltage on the posi-
tive input of the amplifier. The 0 to
10V signal, such as that from a poten-
tiometer, also scales to a similar volt-
age to that of the 0- to 20-mA sig-

12V

R1
100
A_IN_O_010V(H)

D1
R3 C3
BZX84C11 0.1 �F
A_IN_O_010V(W) 12.1k

R7
10k
R4
A_IN_O_020MA(+) 10k
5V
R2 D2 5V
C1 R10
20 IN4448W R8
A_IN_O_COM 0.1 �F 22.1
IC1 10k
OP1177 �
2.5V R9 R11 C4
AD8138 47 �F TO AD7400
REFERENCE 10k 22.1
R5 �
8.68k �5V
�5V
R6 C2
1k 0.1 �F

Figure 1 This analog-conditioning circuit filters and level-shifts the input signals, developing the AD7400 ADC’s differen-
tial input.

july 5, 2007 | EDN 63

edn070607di40691 DIANE
designideas
nal and gets summed into the nega-
tive terminal of the Analog Devices
OP1177 amplifier, IC1.
Shifting the signal above 0V re-
sults in a signal that is similar to a
positive, single-ended analog signal.
A differential ADC-driver amplifier,
Analog Devices’ AD8138, drives the
AD7400. The gain scales such that
the resultant signal is within 6200
mV, which the ADC requires. Final-
ly, before connecting to the AD7400,
the signal runs through a lowpass fil-
ter, which R10, R11, and C4 create be-
tween the positive and the negative
terminals. The AD7400 converts this
differential signal and processes it us-
ing a low-cost microcontroller. Sig-
ma-delta-modulator ADCs, such as
the AD7400, commonly interface to
an FPGA or a DSP. However, this ap-
proach comes at a high price in both Figure 2 These oscilloscope traces show MDAT, inverted MCLKOUT, and the
cost and complexity. For cost-sensi- resulting data stream (courtesy LeCroy).
tive applications not requiring ad-
vanced filtering, you can use a simple puts, MCLKOUT and MDAT (Fig- stream, MDAT. The AD7400 inter-
microcontroller. ure 2). MCLKOUT, a 10‑MHz clock, prets MDAT as a percentage of ones
The AD7400 device has two out- synchronizes the modulated data over time. Because MDAT changes

3.3V

38 1
LDO
37 LDI 2
3.3V
36 3
5V 0.1 �F
35 4

1 16 TC7SZ08F 34 5
AD7400
VDD+ GND2
2 15 33 6
� VIN+ NC NC7S14M5X
3 14
� VIN� VDD2 32 7
4 13
NC MCLOCKOUT
5 12 31 8
NC NC
6 MDAT 11 30 9
NC
7 VDD1 10 MSP430F2274
0.1 �F NC 29 10
8 9
GND1 GND2
28 11
27 12
26 13

25 14
CLK
24 15

23 16

22 17
21 18

20 19 10 �F 0.1 �F

Figure 3 The AD7400 serial ADC digitizes the analog input and feeds the simple, low-cost microcontroller.

64 EDN | july 5, 2007

edn070607di40693 DIANE
designideas
only at the rising edge of MCLKOUT,
the circuit must AND together MDAT
and MCLKOUT to create a stream of
pulses that the microcontroller can
count. The microcontroller first in-
verts MCLKOUT to prevent unin-
tentional glitches from being counted
at the transition edges of MDAT. The
figure shows MDAT, inverted MCLK-
OUT, and the resulting data stream.
The pulsed data signal and the in-
verted MCLKOUT each feed into
a separate timer/counter on the mi-
crocontroller (Figure 3). The TI
MSP430F2274 provides two 16-bit
counters and can support operation as
fast as 16 MHz. The circuit measures
the ADC value by sampling the data
counter when the clock counter sig-
nals an overflow interrupt. For this
application, running an average num-
ber of data measurements on a circu-
lar buffer may conveniently filter the
data.EDN

Circuit guards amplifier outputs high-voltage condition on either out-

put. The MOSFETs, Q1A and Q1B, are
against overvoltage
STEVE EDN070621DI4073 FIGURE 1normally on; zener diode D4 and its
bias components drive the MOSFETs’
John Guy, Maxim Integrated Products, Sunnyvale, CA gates to approximately 11V. Dual diode


A universal requirement for au- rior. Though operating from a voltage D3 provides a diode-OR connection to
tomotive electronics is that any of 3.3 or 5V, which is lower than the the dc voltage on each output, thereby
device with direct connections to the battery voltage, the amplifier must be producing a voltage that controls the
wiring harness must be able to with- able to stand off the full battery volt- output of shunt regulator IC2. The cir-
stand shorts to the battery voltage. age. You can also use a protection net- cuitry protects IC1, a 1.4W Class AB
Though brutal, this requirement is nec- work appropriate for these amplifiers amplifier suitable for audible warnings
essary for reliability and for safety. One for other automotive circuits (Figure and indications for the automotive
example of the need for this protection 1). A dual N-channel MOSFET dis- electronics.
is an audio amplifier that produces in- connects the amplifier’s outputs from During normal operation, the am-
dicator noises in the automotive inte- the wiring harness in response to a plifier outputs’ dc components are at

J1
VBAT

J2
VCC

R3
200k
R4
J3 5.1k

J6
C4 OUT�
D4
0.1 �F
CMPZ5241

Q1A
1 SHDN OUT� 8 SI4982
2 BIAS GND 7
C5 3 IC1 6
1 �F IN� VCC J7
MAX9716 OUT�
4 5
IN� OUT�
D3
C1 D1 D2 BAV70LT1
1 �F Q1B K
CMPZ5231 CMPZ5231
C3 R R2 SI4982 R5
1
J4 1 �F 22k 51k 38.3k
IN
1 PGND FB 5
2 GND IC2
J5 MAX8515
3 OUT 4
IN R6
10k
C2
0.1 �F

Figure 1 This output-protection circuit provides continuous protection against overvoltage faults.

66 EDN | july 5, 2007

designideas
one-half of the VCC supply—2.5V in
this case, for which VCC is 5V. The 11V
gate drive fully enhances the MOS-
FETs, and the shunt-regulator output
is off because its feedback input, Pin
5, is below its internal 0.6V threshold.
If either output exceeds 5V, current
flows through D3 into the R5/R6 divid-
er, pulling the feedback terminal above
its threshold. The shunt-regulator out-
put then pulls the MOSFET-gate volt-
age from 11V almost to ground, which
blocks high voltage from the amplifi-
er by turning off the MOSFETs. The
MOSFETs easily withstand the con-
tinuous output voltage, and the circuit
returns to normal operation when you
remove the short. Because the circuit
does not respond instantaneously, zener
diodes D1 and D2 provide protection at
the beginning of a fault condition.
The waveforms of Figure 2 repre- Figure 2 In Figure 1, one of IC1’s two audio outputs (Trace 1) has protection
sent an operating circuit. One of the when its external terminal accidentally contacts an 18V supply voltage (Trace 2).
amplifier’s outputs (Trace 1) is a 1-
kHz sine wave biased at a dc voltage of to ground in response to the overvolt- other voltages, you can adjust the R5/
2.5V. Trace 2 is the signal on the wire age condition. Trace 4 is current in the R6 resistor values. The shunt regulator
harness. It also starts as a 1-kHz sine wire harness. Initially a sine wave, this must be able to function in saturation
wave biased at a 2.5V-dc voltage, but, current drops to zero in response to the and, therefore, requires a separate sup-
at 200 msec, it shorts to an 18V sup- overvoltage condition. ply pin in addition to the shunt output
ply. Trace 3 is the shunt regulator’s out- The components in Figure 1 opti- pin. The circuit repeatedly withstands
put, initially biased at 11V but pulled mize this circuit for 5V operation. For 28V shorts without damage.EDN

zero, the optocoupler circuit is on, and

Isolated circuit monitors ac line the output voltage is low. It continues
to be low until the input voltage moves
David Williams, Millington, MI
below the enable voltage. The follow-


The circuit in Figure 1 provides
a low-cost, isolated ac-line mon-
itor that measures ac-line-voltage level
and has some other unique capabilities.
The analysis of the circuit is straightfor-
ward: When the ac input, VIN, is posi-
tive relative to neutral, you apply it to
the network comprising R1, R2, D1, and
the LED in optocoupler IC1. Current
flows in this network when the volt-
age is high enough to get zener diode
D1 and the diode in the optocoupler to
conduct. This diode pair’s conducting
voltage is the enable voltage, VE. The
zener diode’s reverse-breakdown volt-
age of 47V and the optocoupler’s LED
forward voltage of 1.2V make the en-
able voltage 48.2V. Any voltage below
this level drives the output of the op-
tocoupler high. When the voltage ex-
ceeds the enable voltage, the transistor
in the optocoupler becomes saturated,
pulling the output low. The output con-
tinues to stay low until the input volt-
age drops below the enable voltage.
The resulting output is a square wave
with a fixed time, tTOTAL, based on how
long the input voltage is above the en-
able voltage. If the voltage on the input
varies from 120 to 144V, the resulting
square-wave waveform becomes wid-
er; if the voltage varies downward, the
pulse width decreases. To calculate the
formula for this circuit, consider the in-
put waveform as a cosine function. Be-
cause the input voltage peaks at time
ing equation yields the time when this
crossover happens:
VE5VIN3cos(23p3f3tON).
Because the cosine function is sym-
metrical around zero, time tON is half
the total time that the output pulse is
high. Because a microprocessor’s timer
port usually captures the time, the sim-
plest way to calculate the input volt-
age from the pulse width is to replace
the on-time with the total time and
thenEquation
to solve for
thedi4074
equation for the in-
put voltage, which gives the result as a
function of the measured pulse-width
output from the optocoupler:
VE
VIN = .
cos(π × f × t TOTAL )

70 EDN | july 5, 2007

designideas
You can implement this formula in
software or a look-up table that con-
verts pulse width to input voltage. Take
note that the input voltage is the peak
ac voltage, so you must convert it to
the rms value if necessary. You can also
use this circuit as a clock line because
the output frequency is independent
of the duty cycle. The output is con-
sistently 60 Hz, and you can use it for
timekeeping. You can also potentially
use it for zero-crossing-load driving if
you extrapolate the time back to the
zero crossing based on the input volt-
age, because the duty-cycle edge time-
shifts from the real zero crossing.
Some other design principles in this
circuit require attention. D2 protects
the diode in the optocoupler when the
ac input goes negative. In most cases,
the optocoupler diode is unaffected
because the reverse leakage through
the network ensures that the LED
does not exceed its maximum reverse
voltage. However, bypassing the diode
is the best approach for clamping the
voltage across this optocoupler using
a diode. Adding this diode does more
than double the quiescent current in
I2C interface has galvanic isolation,
wired-OR capability, improved
noise margin
Michele Costantino, Microsaic Systems Ltd, Woking, United Kingdom

This Design Idea describes a sim-
ple and effective way to provide
optoisolation for devices connected on
the I2C bus (Figure 1). It improves on
an earlier version (Reference 1). SDA
and SCL are on the bus master’s side
of the I2C bus; SDA1 and SCL1 are on
the slave device’s side. It is fairly easy
to optoisolate the clock line because
it is unidirectional, from the master to
the slave device. A P-channel MOS-
FET, Q3, provides the current for the
LED of the fast optocoupler, IC2, buff-
ering the clock line.
The data line, however, is bidirec-
tional. This section of the circuit is sym-
metrical. Resistors R6 and R7 are the I2C
72 EDN | july 5, 2007
R1 R2 D1
10k 10k 1N6016B
5V
R4
10k
VIN
120V IC1 VOUT
WPPCD11064CD R3
1k
D2
1N4004
C1
0.001 �F
Figure 1 This simple ac-mains voltage monitor’s output is a square wave
whose width is proportional to the input-voltage level.
the circuit, and, because you apply this ance on the zener voltage. A 5% varia-
current to the ac line, it may be a con- tion on this voltage can result in a sig-
cern for both energy consumption and nificant error in your estimate of the
power dissipation in the resistors in the input-voltage amplitude. Specifying a
input circuit. more precise diode or calibrating each
If you need a more accurate estima- board by applying a known input volt-
tion of input voltage, some options age and storing that value in memory
improve circuit function. The main as a fixed calibration improve the over-
source of this variation is the 5% toler- all accuracy of this circuit.EDN
high—that is, no I2C devices are pull-
ing them down—Q1 is off, no current
flows into the LED of optocoupler IC2,
IC2’s Pin 7 is high, Q2 is off, and the
LED of optocoupler IC1 is also off.
If a device drives the SDA line low,
Q1 and the LED of IC2 turn off, driving
pullup resistors on the slave device’s IC2’s Pin 7 low; diode D2 then starts to
side of the bus, and R3 and R1 are dum- conduct. The result is a low level on
my pullups in parallel with the main the SDA1 line—the low output volt-
I2C pullup resistors on the SDA/SCL age of IC2 plus the threshold voltage of
side. If both SDA and SDA1 lines are Schottky barrier diode D2. In this situ-
ation, it is important to notice that the
the LED of IC1 LED of IC1 does not turn on because
the voltage applied across it is below
does not turn its threshold. This situation means that
on because the circuit does not latch, and it can
recover from this state once you release
the voltage the SDA line.
applied across Q3 and the PNP BJT (bipolar-junc-
tion transistor), Q1, effectively buf-
it is below its fer the two SDA/SCL lines so that
threshold. no extra current flows into the open-
collector and -drain stages of the I2C
designideas VCC1 VCC1 VCC1
VCC
5V 5V 5V
VCC VCC C1 5V
devices that connect to the bus when 5V 5V 100 nF

they hold the lines down. This config- R5 R6 R7

uration allows the optoisolated inter- R1 R2
8 330 330 330

face to repeatedly pull low, providing 10k 330 7 IC1

HCPL0600
wired-OR capability. Using Schott- 2
6
ky barrier diodes for D1 and D2 rath-
D2
er than common diodes reduces the 3
BAT254
low-level voltage on the bus, improv- 5 SDA1
ing the noise margin. Finally, because Q2
MMBT3906LT1
of the low propagation-delay times of VCC1
5V C2
the Fairchild Semiconductor (www.fair 100 nF
childsemi.com) HCPL06XX devices
5
that this design uses, this interface has
no bus-glitch problems and works well D1
7

at speeds of 400 kHz or higher (Refer- BAT254 2

ence 2).EDN 4
SDA 6
Q1 SCL1
R e fe r e nce s MMBT3906LT1
R4
330
1 Nguyen, Minh-Tam, and Martin VCC
3
Baumbach, “Two-wire interface has 5V IC2
HCPL0630
galvanic isolation,” EDN, Nov 11,
1999, pg 174, www.edn.com/article/
R3
CA46286. 10k
Q3
FDV302P
2 Blozis, Steve, “Opto-electrical

isolation of the I2C-Bus,” Embedded SCL

Systems Design, Oct 14, 2004, Figure 1 This circuit provides an isolated, bidirectional, wired-OR connection of
www.embedded.com/showArticle. slave devices to the I2C-bus master.
jhtml?articleID=49901764. edn070621di40771 DIANE

74 EDN | july 5, 2007