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OUM

Ovonic Unified Memory

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Outline

„ Introduction
„ Ovonic Unified Memory technology
„ OUM advantages
„ Risk factors
„ Product/manufacturing technology
„ Conclusion

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„ Ovonic Unified Memory is a new approach to high-speed,

non-volatile memory
„ Reduced cost/bit
„ High endurance, low power, nonvolatile RAM
„ Readily scaled – avoids scaling barriers of DRAM/Flash
„ Merged memory/logic simplified

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Introduction

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„ Ovonic Unified Memory is a new semiconductor

memory technology, originally invented by
Energy Conversion Devices, Inc. (ECD), and
now licensed exclusively to Ovonyx, Inc.

„ OUM uses a reversible structural phase-change --

from the amorphous phase to a crystalline phase --
in a thin-film chalcogenide alloy material as the
data storage mechanism.

„ The small volume of active media in each memory

cell acts as a fast programmable resistor,
switching between high and low resistance with
>40X dynamic range.

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„ Phase-change technology is well established, and is
the basis for the current CD RW, PD, DVD-RAM and
DVD+RW optical disk memory products.

„ OUM offers advantages in cost and performance over

conventional DRAM and Flash memories, and it is
compatible with merged memory/logic.

„ OUM technology uses a conventional CMOS process

with the addition of a few additional layers to form the
thin-film memory element.
„ OUM products are now being commercialized through
a number of licensing agreements and joint
development programs with Ovonyx.

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Technology

Material Science and Device Physics

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„ Many phase-change alloys have been
described in the technical literature

Binary Ternary Quaternary

Ga Sb Ge2Sb2Te5 Ag In Sb Te
In Sb In Sb Te (Ge Sn)Sb Te
In Se Ga Se Te Ge Sb (Se Te)
Sb2 Te3 Sn Sb2 Te4 Te81Ge15Sb2S2
Ge Te In Sb Ge Ge2Sb2Te5:O
Ge Sb Ga Sb Te Ge2Sb2Te5:N

„ OUM Devices typically use the GeSbTe alloy system

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Congruent Crystallization in the GexSbyTez System
Sb

Sb 2Te 3
147
124

225

415

Te GeTe Ge

„ Rapid, reversible changes between the disordered and

ordered atomic structure can be made to happen for
compositions along the pseudobinary tie-line shown above.

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Amorphous Phase Crystalline Phase

TEM
Images

Electron
Diffraction
Patterns

Material Characteristics
z Short-range atomic order
z Low free electron density
z High activation energy
z High resistivity
z Long-range atomic order
z High free electron density
z Low activation energy
z Low resistivity

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X-ray Diffraction of Ge2Sb2Te5
(one minute isochronal anneals)

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Annealing Dependence of Ge2Sb2Te5
Electrical Resistivity
(ten minute isochronal anneal)

1E+4
Relative Resistivity

Ea = 0.21eV
1E+3

Vitreous State Crystalline State

1E+2

1E+1

Ea = 0.02 eV
1E+0
150 170 190 210 230 250

o
Annealing Temperature ( C)

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Phase-Change Properties of “tie-line” GeSbTe
Alloys From DTA Measurements

Alloy System GeSb2Te4 Ge2Sb2Te5 Ge2Sb2.Te5 Ge4SbTe5

solid -> liquid:
melting point: (oC) 617 632 634 690
heat of fusion: (J/cm3) 587 622 559 576

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Thermal and Mechanical Properties
of Ge2Sb2Te5 Alloys

H.K. Lyeo et al., Appl. Phys. Lett.

Thermal Conductivity (W/m K): 0.3 (amorph)
89 (2006) 151904
0.45 – 0.95 (fcc)
1.4 – 1.53 (hcp)

Kuo/Favro WSU Thermal Wave

Heat Capacity (J/cm3K): 1.25 Laboratory measurement

Density (g/cm3): 6.20 (fcc) N. Nobokuri et. al, J. Appl.

Phys. 78, 690 (1995)

Linear Thermal Expansion

Coefficient (K-1) [300K - 900K] 23.5 ppm W. Porter ORNL

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Selected Material Properties
Selected Material Properties
Thermal Specific Thermal Electrical Thermal
Material Conductivity Heat Diffusivity Resistivity Expansion
K C α ρ Coefficient
(J/cm K s) (J/cm3 K) (cm2/s) (Ω cm) (ppm/K)

Al 0.56 2.43 0.230 3 x 10-6 23.6

*Si 1.41 1.61 0.870 doping dependent 2.33
*Poly Si 0.34 1.61 0.185 doping dependent 2.33
TiW 0.6 2.04 0.290 7 x 10-5
TiAlN 0.3 0.7 0.420 2 x 10-3
*Si1.0N1.1 0.02 1.4 0.014 comp. dependent 3.0
*SiO2 0.014 3.1 0.004 1 x 1016 0.6
(ZnS).8 – (SiO2).2 0.0066 2.04 0.003 1 x 1015 (est)
BCB 0.0015 0.7 0.002 1 x 1019 52
Polyimide 0.0016 0.7 (est) 0.002 4 x 1016

* C.H. Mastrangelo PhD Thesis “Thermal Applications of Microbridges” UCB (1991)

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Threshold Switching in Chalcogenide Alloys

CURRENT Chalcogenide alloys (alloys that

contain elements such as Se
and Te from Group VI of the
Periodic Table) exhibit
Ith
electronic threshold switching.
This phenomenon allows
Vh V th
GeSbTe – based OUM cells to
V O LTA G E be programmed at low voltage
whether they are in the resistive
or conductive state.

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„ The OUM cell is programmed by application of a

current pulse at a voltage above the switching
threshold.

„ The programming pulse drives the memory cell into

a high or low resistance state, depending on current
magnitude.

„ Information stored in the cell is read out by

measurement of the cell’s resistance.

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Programming of OUM Device (schematic)

Amorphizing
RESET Pulse
t1
Tm
Temperature

Crystallizing
(SET) Pulse

Tx
t2

Ta
Time
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„ OUM devices are programmed by electrically

altering the structure (amorphous or crystalline)
of a small volume of chalcogenide alloy.

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Data Storage Region in a Planar OUM
Memory Cell

Crystalline Chalcogenide

Amorphous Chalcogenide

Resitive
Electrode

OUM device when

programmed to the
RESET or
(high-resistance) state.

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Current
OUM

Voltage

Schematic
Actual

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„ Simple planar offset structures have been
used to investigate basic device physics

TiW
SiO2
TiW
GeTeSb Phase Change Alloy

SiO2
Ti A l N TiW

SiO2

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Programming Curves for Planar Offset Device
1E+6

Resulting Programmed Resistance (Ohms)

1.6 1E+5
Current (mA)

1.2 Programming Current

Range

0.8 1E+4
Read Voltage
Range

0.4

1E+3
0 0.2 0.4 0.6 0.8 1 0.0 0.5 1.0 1.5 2.0

Device Voltage (V) Programming Current (mA)

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Programming Curves for Low Current Device

Resulting Programmed Resistance (Ohms)

250

200
Current (µA)

150

100

50

0
0 0.2 0.4 0.6 0.8 1 1.2

Device Voltage (V) Programming Current (µA)

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Temperature Dependence of
Programming Characteristics

1.E+06

The high resistance,

Resistance (Ohms)

1.E+05 “Reset,” state shows

activated, semiconductor
1.E+04 – like behavior while the
low resistance, “Set,” state
1.E+03 shows essentially
temperature independent
1.E+02 metallic behavior
0 50 100 150

Operating Temperature ( oC)

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„ Excellent data retention has been reported on large arrays
of OUM devices :

„ B. Gleixner, A. Pirovano, I. Sarkur, F. Ottogalli, E. Tortorelli, M. Tosi,

and R. Bez, “Data Retention Characterization of Phase-Change Memory
Arrays,” Proc. Intl. Rel. Phys. Symp. 542 (2007).

„ Array data shows intrinsic retention failure < 1 PPB at 85C for 1E5
hours – adequate for high-density array applications.

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B. Gleixner, et al. Proc. Intl. Rel. Phys. Symp. 542 (2007).

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„ OUM cells can have extraordinary cycle life – single cells

have been tested to more than 1013 write/erase cycles without
failure.

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Cycle Life > 1013 Write/Erase Cycles
6
Log Device Resistance

Programming Pulse Width: 50 nsec

4
Programming Current: 1 and 1.7 mA

2
2 4 6 8 10 12 14
Log Num ber of Programm ing Cycles

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„ OUM devices have a very large dynamic range

and can be programmed to intermediate
resistance values for multi-state data storage.

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Multi-State Storage
1E+6
DEVICE RESISTANCE (ohms)

1E+5

1E+4

1E+3
2.07

2.82
2.16

2.26

2.35

2.45

2.54

2.73
2.63
1.42

1.51

1.60

1.70

1.79

1.88

1.98
2.

2.

2.

2.

2.

2.

2.

3.

3.

3.

3.

3.

3.

3.

3.

4.
20

32

44

56

68

80

92

04

16

28

40

52

64

76

88

00
PROGRAMMING CURRENT (mA)

„ Multiple-bit storage in each memory cell (10 pulses

per step, repeated ten times.)
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Technology

Device Modeling

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Device Modeling

„ Simple analytical models are used to show trends

with material properties and size for spherical
equivalent structure.

„ Numerical model includes complete device

geometry and detailed mesh evaluation.

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Numerical simulation is used to predict the
behavior of OUM devices
„ Chalcogenide behavior is based on bulk
properties of the alloy.
„ Bulk properties can be quantified.

Objective
„ Model well-understood bulk properties.
„ Predictive capability for alternate device
structures.
„ Sensitivity analysis of device structure variations.

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Model Considerations

„ Phase-change Nucleation
Crystal growth
Heat of fusion

„ Electrical Electric field

Current density
Percolation conduction

„ Thermal Heat equations

Percolation conduction

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„ Crystalline volume fraction as a function of
temperature and time is given by the
Johnson-Mehl- Avrami equation.
Crystalline Volum e Fraction vs. Log (t)
1

0.9
400 C
0.8
350 C
0.7
300 C
to = 2E-36 sec
0.6
p= 1
0.5
250 C
Ea = 3.7 eV
0.4

200 C 0.3
Ea: activation energy T: temperature
0.2
150 C p: nucleation rate t: time
0.1

0
Ko scaling factor
-1 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10
0 Log t (sec)

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„ Both electrical and thermal conductivity are
described by a two-component percolation
system.

1E4
17% ratio=104
electrical
conductivity (σ)
Overall Conductivity

1E3

1E2

1E1
ratio=6
thermal conductivity (k)
1E0
0 20 40 60 80 100
Volume Fraction of High Conductivity Component

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„ The device can be broken into a mesh, with
finite difference calculations performed at
each mesh point.
The device can be broken into a mesh, with finite difference
calculations performed at each mesh point.

„ The mesh has variable spacing to allow both detailed

The mesh has variable spacing to allow both detailed electrical
electrical analysis and accurate thermal accounting
analysis and accurate thermal accounting with the least number of
with the least number of mesh points.
mesh points.

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Initial Conditions

Compute Implicit electrical solution of the

Electrical Solution
mesh followed by explicit
of Array
calculation of temperature
allows time/temperature/
Increment Time electrical phase-dependent
properties to be varied in time.
Iterate Heat Equation
for this Timestep
Modify Heat- Time
Dependent Variables

Yes Significant No
Change?

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Speed Power Tradeoff
Speed Power Tradeoff
1.E-08

1900
1500
120
100

0
80
1.E-09
Quench time (s)

0
0
60
mer 40

0
Po l y 0
200 G
1.E-10 BPS
SiO
100 Si N
1.E-11

1.E-12
1.E-05 1.E-04 1.E-03 1.E-02
Power to reset in 5ns (W)
„ Simulation results for different device structure and dielectric materials
and scaling the device equivalent spherical diameter from 1,900 to 100 A.
„ . Scaling results in lower power and faster memory operation.

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Strong Ovonyx Proprietary Position

220
200
180
160
140
120
100
80
60
40
20
0
'99 '00 '01 '02 '03 '04 '05 '06
Patents Issued Applications Filed

ƒ Licensable Patents (115 issued + 81 filed) as of Dec06

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ƒOvonyx Ranked 8th Worldwide in Semiconductor Manufacturing
Category in 2006 by IEEE Spectrum in terms of Originality, Growth,
Generality and Impact of IP.

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Advantages

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Cost/Bit Reduction

„ Small active storage medium

„ Small cell size – small die size
„ Simple manufacturing process – low step count
„ Simple planar device structure
„ Low voltage – single supply
„ Reduced assembly and test costs

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Near-Ideal Memory Qualities
„ Non-volatile
„ High endurance – >1013 demonstrated
„ Long data retention – >10 years
„ Static – no refresh overhead penalty
„ Random accessible – read and write
„ High switching speed
„ Non-destructive read
„ Direct overwrite capability
„ Low standby current (<1µA)
„ Large dynamic range for data (>40X)
„ Actively driven digit-line during read
„ Good array efficiency expected
„ No memory SER – RAD hard
„ No charge loss failure mechanisms
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Highly Scalable

„ Performance improves with scaling

„ Only lithography limited
„ Low voltage operation
„ Multi-state demonstrated
„ 3D multi-layer potential with thin films
„ Small storage active medium

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Logic Process Compatible

„ Late low-temperature processing

– Doesn’t compromise P-channel devices

„ Adds 2 to 4 mask steps to conventional CMOS logic

process with low topography

„ Low-voltage operation

„ Enables economic merged memory/logic

„ Enables realistic System-On-a-Chip (SOC) products:

– Logic/Non-volatile memory/Data memory/Linear

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Merged Memory Logic

„ MDL and MFL

– 16-64Mbit, .5-2M gates
„ Provides higher performance, reduced power,
reduced package count, and increased reliability
„ Costly and difficult with DRAM or Flash
„ OUM substitutes for DRAM a/o Flash
– Enabling reduction in cost/complexity

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System-On-a-Chip (SOC) Compatible

„ Linear, SRAM, DRAM, Flash, DSP, CPU, FPLD, ROM

„ 4M to 64M, 2M gates on 100mm2 die

„ OUM unified solution, 24 to 26 masks with five metal layers

„ Reduction to realistic cost/complexity

„ Simplicity reduces development time

– Keeps technology and products current

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Risk Factors

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Risk Factors

„ Reset current < min W switch current

„ Standard CMOS process integration
„ Alloy optimization for robust high temp operation and speed
„ Cycle life endurance consistency
„ Endurance testing to 1014 – DRAM
„ Defect density and failure mechanisms

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Product/Manufacturing
Technology

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„ Read operations are performed at a voltage below

the threshold voltage, Vt, to avoid upset, so control of
Vt in a memory array is a critical manufacturing issue.

„ Vt is seen to be stable with changes in temperature of test

structures.

„ Vt can also be adjusted by tailoring reset current if needed.

„ Variations in programming characteristics due to

layer thickness and compositional uniformity of the
chalcogenide alloy have been investigated.

„ OUM arrays have demonstrated manufacturability

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Current - Voltage vs. Temperature
3

2.5
38 C
Device Current (mA)

2 60 C
80 C
100 C
1.5
120 C
140 C
1 160 C
180 C
0.5

0
0 0.5 1
Device Voltage (v)

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R-I Curve & Threshold Voltage vs. Current
(breakdown structure)

1E+7 1.2

Threshold Voltage (V)

Resistance (OHMS)

1E+6
0.8

1E+5 0.6

0.4
1E+4
0.2

1E+3 0
0 1 2 3 4 5 0 1 2 3 4 5
Programming Current (mA) Reset Current (mA)

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Current - Voltage vs. Reset

3.5
Device Current (mA)

3
2.5
2
1.5
1
0.5
0
0 0.5 1 1.5
Device Voltage (v)

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Vh and Vth vs. Electrode Spacing

1.5
Voltage (volts)

1 T HRESHOLD

HOLDING
0.5

0
0E+0 2E-6 4E-6 6E-6 8E-6 1E-5
Electrode Spacing (cm)

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R-I Scanned Across Wafer
(non-breakdown structure)

1E+6

fixed reset level

(4 mA, 40 nsec)
Resistance (OHMS)

1E+5
6 die, two devices per die,
scanned diagonally across
1E+4
3” wafer

1E+3
0 1 2 3 4
Programming Current (mA)

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Compositional Dependence of Laser-Induced
Crystallization Speed in GeTeSb Alloy Films

GeTe
50

40

100
ns
%)
(at
Ge

30

70
ns

200
ns
20
Ge2Sb2Te5
GeSb2Te4
50n

10
s

GeSb4Te7
30n

Te
s

0 10 20 30 40 50
Sb(at%) Sb2Te3

Noboru Yamada, “Potential of Ge-Sb-Te Phase-change Optical

Disks for High-Data-Rate Recording”, SPIE v.3109, pp28-37. (1997).

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Disturb Considerations

„ Read Disturb
– Read is performed in the OFF mode for the reset state
– For the set state, read is mildly constructive
– For the reset state, read current is negligibly small
– I read < I set
„ Write Disturb
– ∆T = 20oC at 1000Å spacing – simulation
„ Conclusion
– No known disturb issue with the presently-planned
array architecture and read/programming scheme as
long as:
- Vread < Vth
- Matchstick space > ~1000Å

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DC Read Effect
Vread = 0.5V
Vth = 0.8V
1E+7
Resistance (ohms)

1E+6

1E+5

1E+4
no set states

1E+3
1E+1 1E+2 1E+3 1E+4 1E+5 1E+6
Time (sec)

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Initial Target Markets

„ Flash - pin compatible „ Encryption

„ FPLD, FPLA „ Neural computing

- pin compatible
„ Digital Signal Processing
„ DRAM - pin compatible
„ Power switching
„ Embedded macros
„ Smart cards
„ SOC macros
„ Serial EEPROM
„ SRAM -cache, battery, fast

„ ROM - pin compatible

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Conclusion

„ Near ideal memory qualities

„ Broadens system applications

– Embedded, System-On-a-Chip (SOC), other products

„ Highly scalable

„ Risk factors have been identified

„ Time to productize

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For additional information:

Phone: 248.299.6022
Fax: 248.659.1500
E-mail: webmasters@ovonyx.com
Address: 2956 Waterview Drive; Rochester Hills,
MI 48309

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