Question Bank

Course: B.Tech.
Branch: ECE
Year and Semester: 4th Year, 8th Semester
Subject Code and Name: EC-406, VLSI DESIGN & TECHNOLOGY
Subject Teacher: Deepti Prit Kaur

Topics Covered: Introduction: Introduction to Computer-aided design tools for digital

systems. Hardware description languages, Introduction to VHDL, Data objects, Classes and
data types, Operators, Overloading, Logical operators. Types of delays, Entity and
Architecture declaration. Introduction to behavioural, dataflow and structural models.
VHDL Statements: Assignment statements, sequential Statements and process,
Conditional statements, Case statements, Array and loops, Resolution functions, Packages &
Libraries, Concurrent statements.
Combinational Circuit Design: VHDL models and simulation of combinational circuits
such as Multiplexers, Encoders, Decoders, Code converters, Comparators, Implementation
of Boolean functions etc.

Section A
1. Define CAD and how it designs a logic circuit.
2. Discuss the Signal, Variable and Constant Classes in VHDL, with examples. Give any two points
of differences between Signal and Variable class.
3. List the scalar data types in VHDL. Discuss each one with examples.
4. Name four modeling techniques used in VHDL to describe digital circuits.
5. Which modeling style supports the highest level of abstraction in VHDL.
6. What are the types of delays in VHDL? Explain how they can be modeled in the VHDL designs with
examples.
7. What is process statement? Define sensitivity list in a process statement.
8. Define the terms ‘Entity’ and ‘Architecture’ in VHDL.
9. Compare different Hardware Description Languages.
10. List all the logical operators in VHDL.

Section B

1. Using traditional design technique, design a 2-input AND gate.

2. What does VHDL stand for? Write VHDL description for a 2-input NAND gate.
3. Write an entity-architecture pair for a 4-to-1 multiplexer.
4. Write VHDL description of a 2-input XOR gate using basic gates.
5. Design a VHDL code of Half adder.

1
 6. What is dataflow modeling in VHDL? Write dataflow model for a 2:1 MULTIPLEXER using
VHDL.
7. Give an example of a signal assignment statement in VHDL. Also determine the order of
execution of the following statements, if B = 0 and A changes from 0 to 1
W <= not A;
X <= not B;
Y <= W and B;
Z <= A and X;
O <= Y or Z;
8. Write behavioral model for AOI logic circuit.
9. Design a VHDL code for a 3 bit binary to gray code converter.
10. Write VHDL code for design of full adder using half adders and basic gates.

Section C

1. Label all the components of the program given below in the following categories-
a. Keyword
b. User-defined name
c. Symbol
d. Operator

ENTITY xor_gate IS
PORT( a,b: IN BIT; y: OUT BIT);
END xor_gate;

ARCHITECTURE behave OF xor_gate IS

SIGNAL w, x, y, z: BIT;
BEGIN
W <= not a;
X <= not b;
Y <= w and b;
Z <= a and y;
O <= y or z;
END behave;
2. Discuss the concurrent behavior of the statements in the VHDL program, with reference to
program given in the previous question.
3. Write VHDL description for 3:8 decoder in VHDL using behavioral modeling.
4. Draw a diagram showing basic design flow for HDL based method of digital system design.
5. Write VHDL description for a 8-to-3 priority encoder in VHDL using behavioral (sequential)
modeling.