POWER EFFICIENT CHANNELIZER FOR SOFTWARE DEFINED RADIO USING VLSI

ABSTRACT

Multiple communication channel support in RF transmission, such as that in a Software Defined Radio
(SDR) warrants the use of channelizers to extract required channels from the received RF frequency band and to
perform follow-on baseband processing. This paper describes the process of channelization as it applies to low
power and high-efficiency applications in wireless and Satellite Communications (SATCOM) domains. Smaller
bandwidths and changing requirements of bandwidth calls for a programmable channel selection mechanism
whereby channels and the resulting bandwidth can be selected based on target application, which is the primary
principle in the Software Defined Radio based systems. Evolving wireless standards, advances in FPGA
technologies available at a much lower Non-Recurring Engineering (NRE) costs than those for a comparable custom
designed ASIC make programmable channelizer a viable solution. Radiation hardness is an essential requirement for
parts used in space systems. This paper addresses the importance of methods to meet radiation requirements:
selection of robust technologies and hardening by design.

INTRODUCTION

1.1 OVERVIEW

Software Controllable Architectures (SCA) are more adaptable to multi-standard and multi-channel
communication systems. FPGA based channelizers are essential components and enable channel selection to be
configurable based on the end application. The goal is to obtain maximum use of a single design through software
reconfiguration of hardware assets and dynamic configuration and selection of channels, while ensuring highest
level of fidelity of signals received at the destination.
Multiple access systems are widely used in satellite and terrestrial communications (such as JTRS land
mobile radio), paving the way for SDR, which promises interoperability and compatibility among disparate
standards. The use of such systems in SATCOM reduces the power requirements and also allows frequency reuse
between the satellite beams. Wideband and narrow band techniques are two main categories. Power efficiency of
any of these techniques can be improved by adding forward error correction coding (FEC) with a bandwidth penalty
and improved bandwidth efficiency will be become more and more relevant with congested channels. This has to be
achieved without jeopardizing the data quality. Systems have to be designed to coordinate carrier frequency, phase
and symbol timing. Synchronous CDMA, orthogonal FDMA and wavelet-packet multiple access are all viable
options. In this work, we will concentrate on the critical aspects of channelizer design itself, trade-offs for low-
power requirements, programmability, implementation details and radiation effects.

1.2 BACKGROUND

1.2 .1 Channel coding

The primary goal of channel coding is to reduce impairments in a reconstructed signal that was affected by
transmission errors and Automatic Repeat Request (ARQ) to further improve channel conditions. Various forms of
channel coding are employed in a transmitter including
Cyclic Redundancy Check (CRC) bits for error detection and Forward error correction (FEC) bits for error
correction. These operations can easily be performed on a programmable device from commercially available FPGA
vendors. For example, in the CRC function, configurable parameters include
- Variable length generator polynomial
- Variable data width from 1 to width of polynomial
- Specified initial value

1.2 .2 Channelizer

Several techniques in channelization are suitable for RF communication channels including Digital down
Conversion, Polyphase Fast-Fourier Transform (Polyphase FFT) Filter Banks and Frequency Domain Filtering. A
multichannel digital receiver is used typically to down convert a set of frequency division multiplexed (FDM)
channels from a sampled data signal stream. Conversely, a multichannel digital transmitter simultaneously up-
converts a number of baseband signals to assemble a set of FDM channels and send them into a single data signal
stream.

The system has RF receivers on the front end which digitize the input channels (for example, ten 20 MHZ
channels). The frontend comprises of Analog to Digital Conversion (ADC) subsystem which forms the first part of
the digital transceiver. Analog signals are mixed with locally generated signal, and band pass filtered. In the process
the received wideband signal is split into quadrature channels (I and Q) that is digitized. An IQ balancer is generally
used prior to the channelizer or can be made a subcomponent of the channelizer itself. Each incoming channel is
assigned a unique Channel ID. The digitized channels are fed to the channelizer which selectively extracts desired
channels and desired number of channels. The digital section of the receiver is called a channelizer or zero-IF
demodulator. The channelizer maps RF (or near RF) directly to baseband. For mobile/hand-held wireless
applications for which SDR is considered to be increasingly suitable, a premium is also placed on power dissipation.
Figure 1 shows a basic wideband transceiver. The extracted channels both control and data portions are then post-
processed in channel processors for demodulation and decoding of real data. During transmit, the payload data is
encoded and modulated and then sent to the channelizer which generates necessary channels for onward
transmission. The number of channel processors (y) depends on the number of active channels at the output of the
channelizer. For programmability, input frequency, output channels and bandwidth parameters can be set as desired,
and can be changed at any given time.

1.3 VERILOG HDL

Verilog HDL is a Hardware Description Language (HDL). A Hardware Description Language is a language
used to describe a digital system, for example, a computer or a component of a computer. One may describe a digital
system at several levels. For example, an HDL might describe the layout of the wires, resistors and transistors on an
Integrated Circuit (IC) chip, i. e., and the switch level. Or, it might describe the logical gates and flip flops in a
digital system, i. e., the gate level. An even higher level describes the registers and the transfers of vectors of
information between registers. This is called the Register Transfer Level (RTL). Verilog supports all of these levels.
However, this handout focuses on only the portions of Verilog which support the RTL level.
Verilog allows hardware designers to express their design with behavioral constructs, deterring the details
of implementation to a later stage of design in the design. An abstract representation helps the designer explore
architectural alternatives through simulations and to detect design bottlenecks before detailed design begins.

1.4 OUTLINE OF THE PROJECT

A power efficient channelizer for software defined radio is being designed using verilog FPGA. Here the
main two blocks of importance are CIC filter block and FFT block. These blocks are designed using Verilog HDL
using the Altera Model Sim simulation tool and for the synthesis Xilinx ISE tool is used.
Thus in our work both inputs and outputs will be streams of binary data. The output from the channel will
be received as such given in the input without the intervention of noise and the efficiency also will be high. Our
channelizer can be utilized in the transmitter and receiver circuits of software defined radio.

LITERATURE SURVEY
2.0 SOFTWARE DEFINED RADIO
A software-defined radio system, or SDR, is a radio communication system where components that have
typically been implemented in hardware (e.g. mixers, filters, amplifiers, modulators/demodulators, detectors, etc.)
are instead implemented using software on a personal computer or embedded computing devices. While the concept
of SDR is not new, the rapidly evolving capabilities of digital electronics are making practical many processes that
were once only theoretically possible.

2.0.1 Receiver architecture

Most receivers utilize a variable-frequency oscillator, mixer, and filter to tune the desired signal to a
common intermediate frequency or baseband, where it is then sampled by the analog-to-digital converter. However,
in some applications it is not necessary to tune the signal to an intermediate frequency and the radio frequency signal
is directly sampled by the analog-to-digital converter (after amplification).

Real analog-to-digital converters lack the discrimination to pick up sub-microvolt, nanowatt radio signals.
Therefore a low-noise amplifier must precede the conversion step and this device introduces its own problems. For
example if spurious signals are present (which is typical), these compete with the desired signals within the
amplifier's dynamic range. They may introduce distortion in the desired signals, or may block them completely. The
standard solution is to put band-pass filters between the antenna and the amplifier, but these reduce the radio's
flexibility - which some see as the whole point of a software radio. Real software radios often have two or three
analog "channels" that are switched in and out. These contain filters, amplifiers and sometimes a mixer.

2.1 FPGA FUELING SOFTWARE DEFINED RADIO TECHNOLOGY

With the proliferation of wireless standards—including wide area 3G, 2.5G, and local area 802.11 networks
—future wireless devices will need to support multiple air-interfaces and modulation formats. Software defined
radio (SDR) technology enables such functionality in wireless devices by using a reconfigurable hardware platform
across multiple standards. With FPGA and data converter technology continuously evolving, the SDR concept is
increasingly becoming a reality. Altera® programmable logic devices, along with a comprehensive portfolio
of intellectual property (IP) cores and state-of-the-art design software, offer an ideal platform for efficiently
implementing SDR technology.

2.2 FIELD PROGRAMMABLE GATE ARRAY

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer
or designer after manufacturing—hence "field-programmable". The FPGA configuration is generally specified using
a hardware description language (HDL), similar to that used for an application-specific integrated circuit(ASIC)
(circuit diagrams were previously used to specify the configuration, as they were for ASICs, but this is increasingly
rare). FPGAs can be used to implement any logical function that an ASIC could perform. The ability to update the
functionality after shipping, partial of the portion of the design[1] and the low non-recurring engineering costs
relative to an ASIC design (notwithstanding the generally higher unit cost), offer advantages for many applications.

2.2.1 FPGA design and programming

To define the behavior of the FPGA, the user provides a hardware description language (HDL) or
a schematic design. The HDL form is more suited to work with large structures because it's possible to just specify
them numerically rather than having to draw every piece by hand. However, schematic entry can allow for easier
visualization of a design.

Then, using an electronic design automation tool, a technology-mapped net list is generated. The netlist can
then be fitted to the actual FPGA architecture using a process called place-and-route, usually performed by the
FPGA Company’s proprietary place-and-route software. The user will validate the map, place and route results
via timing analysis, simulation, and other verification methodologies. Once the design and validation process is
complete, the binary file generated (also using the FPGA company's proprietary software) is used to (re)configure
the FPGA.
PROPOSED MODEL

3.0 DESIGN APPROACH

The overall objective of this work has been to develop a low-power Channelizer design that can be
implemented on FPGA device(s). The design consists of schematic entry and RTL descriptions in Verilog. Specific
tasks include:
3.1 IMPROVEMENTS OF POLYPHASE CHANNELIZER

Efficient M-Path Polyphase channelization architecture is designed for highly efficient and low-cost (power
and area) designs. For providing a complete solution to the problem on hand, we need to address two aspects:
1)Programmability.
2) Low-Power and efficient design techniques.
In a channelizer design, we need to perform basic channelization and secondary signal processing operations.
The main functional blocks in a polyphase system are shown in Figure 2, with down conversion of the incoming
channel with a complex heterodyne, followed by a digital low-pass filter and a down-sampling operation as required
by the decimator.

3.1.1 Low power, low weight techniques:

Reusability, software downloaded bit streams save area, weight and package size. Clocking biases
conventionally have been used to reduce dynamic power. Selective operation of parts of the device is another
method that can save power dissipation. In addition, Multi-layer, 3-D packaging techniques are paving the way into
low-power and low weight implementations.

3.2 Resource sharing:

It is clear from Figure 2 that the structure needed at the input of the M-point FFT is similar to all channels,
except for channel co-efficient. These channel co-efficient can be generated on the FPGA, separately for each
channel and passed to the FFT. Alternatively, the coefficients for all channels can be pre calculated and loaded into a
Content Addressable Memory (CAM) in the FPGA. The front-end processing units consisting of commutator and
polyphase segment is grouped into what we are referring to as “Polyphase Frontend”. Programmable parameters
include decimation rate, channel Id, bandwidth and center frequency, are supplied to Channel Coefficient Generator
(CCG) and Decimation Rate Generator (DRG). This design is capable of generating channel coefficients and
decimation rates that are unique to each channel. The polyphase frontend is recursively called M times to perform
the operation for M channels. Thus it has an interesting and a much desirable byproduct for programmable
channelizers. We initially noted that polyphase channelizers support fixed set of frequency plans with equally
spaced channels. However, this design enables us to overcome that obstacle thus supporting multiple frequency
plans with the overhead of an extra FFT logic. Since low-power is our criterion, the decrease in speed due to this
design is an acceptable trade-off. This improved architecture is shown in Figure3.1.
3.3 GENERATE A COMPUTER SIMULATION MODEL.

Simulation model is developed in Verilog for subcomponents of the system. A subtask of this step includes
generation of functional tests to verify the functionality. Block level and system level tests, with various
configurations of programmable parameters are vital part of functional testing. This gives flexibility of modifying
the frequency plans of a wideband channel and thus simulating different target applications.

3.4 CIC FILTER

It is easy to understand the CIC filter in the frequency domain. As shown in Figure 1, the CIC filter is a
cascade of digital integrators followed by a cascade of combs (digital differentiators) in equal number. Between the
integrators and the combs there is a digital switch or decimator, used to lower the sampling frequency of the combs
signal with respect to the sampling frequency of the integrators.

Figure 3.2 General CIC filter

Each integrator contributes to the CIC transfer function with a pole. Each comb section contributes with a zero of
order D, where D is the frequency decimation ratio. The CIC transfer function in the Z-plane becomes:
 ( 1− z− )
[ ]
N
D D− 1 N

H (z) = H (z) H (z) =

N N
= ∑ z −k

( z )
I C N
1 − − 1 k= 0

We must be careful here because we have two sampling frequencies in the system,
related by D. If we evaluate the z-transference at the output sampling frequency
z=exp(j2πfs/D), the transference becomes

A( f ) = [ s in( π f )
s in( π f / D )
][
N

≈ D.
s in( π f )
πf
] N

f o r D > >1

It is important to make few remarks:

1The filter gain is approximately DN.
2The CIC transfer function has nulls at each multiple of the output sampling frequency f=fS/D.
3There are only two control parameters the number of integrator/comb stages N and the decimation ratio D. In
the Graychip N is fixed at 5.
4The CIC has a wide transition band. Strictly speaking, the passband is small (the amplitude “droops” quickly)
and there is substantial aliasing specially around the first mirror image. This signify that the CIC filter must
be accompanied of an anti-aliasing filter or be used on narrow-band spectrums.

3.4.0 Proposed Cascaded Integrator Comb filter design

For our design we have internally five stages of integrator and combination block in the CIC filter with one
decimator. Whereas totally there are 8 stages for CIC filter is made for the fact to give 8 inputs to the FFT block

Figure 3.3
3.4 FAST FOURIER TRANSFORM

A fast Fourier transform (FFT) is an efficient algorithm to compute the discrete Fourier transform (DFT)
and its inverse. A DFT decomposes a sequence of values into components of different frequencies. This operation is
useful in many fields but computing it directly from the definition is often too slow to be practical. An FFT is a way
to compute the same result more quickly: computing a DFT of N points in the obvious way, using the definition,
takes O(N 2) arithmetical operations, while an FFT can compute the same result in only O(N log N) operations. The
difference in speed can be substantial, especially for long data sets where N may be in the thousands or millions in
practice, the computation time can be reduced by several orders of magnitude in such cases, and the improvement is
roughly proportional to N/log(N). An FFT computes the DFT and produces exactly the same result as evaluating the
DFT definition directly; the only difference is that an FFT is much faster. Let x0, ...., xN-1 be complex numbers.
The DFT is defined by the formula

Figure 3.4 8 point fft model of our design

SIMULATION RESULTS

4.1 SYSTEM VIEW

FPGA technology provides the signal-processing engineer with the ability to construct a custom data path
that is tailored to the application at hand. FPGA reconfigurable DSP system is shown in Figure 4.1.

RESULTS

Figure 4.2 top module view

The block diagram shown above is the top module of our design. Thus in this module we designed we have
totally 13 pins. Where data, decimation value, clock and reset are the input pins, where as the out0 to out7 and
output ready are the output pins.

RTL VIEW OF DESIGN

Figure 4.3
The schematic of internal view of top module is shown in Figure 4.5. We have five stages in the integration
and combination block of the CIC filter. To provide 8 inputs to the FFT block the CIC filter we designed is made to
have 8 stages. To provide synchronization we have the timing controller.

OUTPUT IN FPGA KIT

The design can be verified in any of the compatible FPGA kits of our design. In this kit level the inputs and
outputs are available at the digital level only. In the specified kit the binary values of input and outputs can be
verified with LEDs only.
In any specified kit out outputs will be the same as inputs data given. This is working of a channel to
transmit the given input as such to the output without any interference of noise signals. The power efficiency is
meant in our design in terms of chip area occupied in the kit.
The two main types of FPGA family are Spartan family and Virtex family. The Spartan series targets
applications with a low-power footprint, extreme cost sensitivity and high-volume; e.g. displays, set-top
boxes, wireless routers and other applications. The Virtex series of FPGAs have integrated features such as wired
and wireless infrastructure equipment, advanced medical equipment, test and measurement, and defense systems. In
addition to FPGA logic, the Virtex series includes embedded
fixed function hardware for commonly used functions such as multipliers, memories, serial transceivers and
microprocessor cores.

CONCLUSION & FUTURE WORK

5.1 CONCLUSION

The programmable channelizer can be used for rapid prototyping and deployment of special targeted
applications in multi-standard and wideband civil defense and electronic warfare where variable channel selection is
more suitable than a fixed channel selection and securing communications wherein the frequency plan can change as
needed to prevent intrusion.
Efficiency in terms of architecture optimizations such as those made in the Polyphase FFT and
implementation aspects leading to smaller area, low power, radiation hardness and low cost seem very promising.
Innovative design enhancements from engineering community, coupled with process improvements from FPGA
vendors can play a crucial role in satellite communications and in producing fast, small and efficient
communications systems that can be used both in aerospace and commercial arenas.

5.2 FUTURE WORK

In future the no of stages used in the cic filters can be increased and more efficiency can be obtained. Since
the advantage here is that the platform used is reconfigurable thus the hardware can be reused for several designs.

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