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INTRODUCTION
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gm/I inherent to MOS transistors operated in strong inversion may therefore
cause an increase in power consumption.
2. The presence of additional sources of noise implies an increase in
power consumption. These include l/f noise in the devices and noise coming
from the power supply or generated on chip by other blocks of the circuit.
3. The need for precision usually leads to the use of larger dimensions for
active and passive components, with a resulting increase in parasitic capacitors
and power.
4. All switched capacitors must be clocked at a frequency higher than twice
the signal-frequency. The power consumed by the clock itself may be dominant
in some applications.
In this project dual threshold method is used to reduce the leakage current.
The advantage of the proposed method is, fast approach to analyze the total
leakage power of a large circuit block considering both the Igate and Isub. This
method has minimal Layout impact in reducing the leakage power without
incurring any delay in the circuit.
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1.2 FEATURE SIZE
Feature size reduction in MOSFETs has been the key enabler to the
continuation of Moore’s law. Just as significant as effective channel length Leff
reduction has been shrinking of the gate oxide thickness Tox. Feature size is
shown in Figure 1.1. Aggressive scaling is required to provide substantial
current at reduced voltage supplies and to suppress short-channel effects such as
drain-induced barrier lowering (DIBL), it results in the presence of significant
gate tunneling leakage current. Igate arises due to the finite probability of an
electron directly tunneling through the insulating SiO2 layer. Igate is the strong
exponential function of Tox as well as the voltage potential across the gate
oxide. Another key point is that for a pMOS device is typically one order of
magnitude smaller than an nMOS device with identical Tox and Vdd when
using SiO2. This is due to the much higher energy required for hole tunneling in
SiO2 and the fact that there are very few electrons associated with a pMOS
device.
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Another key point is that for a pMOS device is typically one order of
magnitude smaller than an nMOS device with identical Tox and Vdd when
using SiO2. This is due to the much higher energy required for hole tunneling in
SiO2 and the fact that there are very few electrons associated with a pMOS
device. However, in alternate dielectric materials the energy required for
electron and hole tunneling can be completely different. In the case of nitrided
gate oxides, pMOS Igate can actually exceed nMOS Igate, depending on the
nitrogen concentration. There are numerous process integration problems with
such high-k materials in particular their compatibility with Si and the resulting
mobility degradation which reduces drive current. Even this projection may be
optimistic as the introduction of new materials has much slower process than
very aggressive scaling of already existing solutions.
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1.3.3 GATE DIRECT TUNNELING LEAKAGE
The transisor gate leakage is shown if Figure 1.3 flows from the gate
through the “leaky” oxide insulation to the substrate. In oxide layers thicker
than 3–4 nm, this kind of current results from the Fowler-Nordheim tunneling
of electrons into the conduction band of the oxide layer under a high applied
electric field across the oxide layer. Component of leakage current is shown in
Figure1.4 and Figure1.5 for lower oxide thicknesses however, direct tunneling
through the silicon oxide layer is the leading effect. Mechanisms for direct
tunneling include electron tunneling in the conduction band (ECB), electron
tunneling in the valence band (EVB) and hole tunneling in the valence band
(HVB), among which ECB is the dominant one. The magnitude of the gate
direct tunneling current increases exponentially with the gate oxide thickness
Tox and supply voltage V.
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Figure 1.5 Components of tunneling current
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(since it increases Cox) and the lowest possible doping concentration in the
channel (since it decreases Cdep ) must be used. Higher temperature results in
larger S value, and hence, an increase in the OFF leakage current. In long
channel devices, the influence of source and drain on the channel depletion
layer is negligible. However, as channel lengths are reduced, overlapping source
and drain depletion regions cause the depletion region under the inversion layer
to increase. The wider depletion region is accompanied by a larger surface
potential, which attracts more electrons to the channel. Therefore, a smaller
amount of charge on the gate is needed to reach the onset of strong inversion
and the threshold voltage decreases. This effect is worsened when there is a
larger bias on the drain since the depletion region becomes even wider.
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CHAPTER 2
LITERATURE REVIEW
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Low voltage low power VLSI sub system describes about the
linear relationship between oxide thickness and threshold voltage
Low voltage low power CMOS design techniques for deeps of
submicron ICs explains about source of power consumption and ways to
achieve dual threshold voltage
Power minimization by simultaneous dual threshold assignment
describes about the simultaneous assignment of dual threshold
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In the ACTIVE state, the sleep transistor is on. Therefore, the circuit
functions as usual. In the STANDBY state, the transistor is turned off, which
disconnects the gate from the ground. Note that to lower the leakage, the
threshold voltage of the sleep transistor must be large. Otherwise, the sleep
transistor will have a high leakage current, which will make the power gating
less effective. Additional savings may be achieved if the width of the sleep
transistor is smaller than the combined width of the transistors in the pull-down
network.
To guarantee the proper functionality of the circuit, the sleep transistor
has to be carefully sized to decrease its voltage drop while it is on. The voltage
drop on the sleep transistor decreases the effective supply voltage of the logic
gate. Also, it increases the threshold of the pull-down transistors due to the body
effect. This increases the high-to-low transition delay of the circuit. This
problem can be solved by using a large sleep transistor. On the other hand,
using a large sleep transistor increases the area overhead and the dynamic power
consumed for turning the transistor on and off. Because of this dynamic power
consumption, it is not possible to save power for short idle periods. There is a
minimum duration of the idle time below which power saving is impossible.
Increasing the size of the sleep transistors increases this minimum duration.
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Since using one transistor for each logic gate as shown in Figure
2.2 results in a large area and power overhead, one transistor may be used for
each group of gates as depicted. To find the optimum size of the sleep transistor,
it is necessary to find the vector that causes the worst case delay in the circuit.
This requires simulating the circuit under all possible input values, a task that is
not possible for large circuits.
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The drawbacks of gating the power supply is
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When IG is ignored, the leakage current has three main
components IREV, IGIDL and IOFF. The last component is typically much
larger than the first two. Bringing the voltage of nMOS Bulk below zero volts
decreases IOFF, but it increases IREV and IGIDL. This is because the strong
bulk biasing increases GIDL and drain to bulk tunneling leakages to the point
where they become limiting on advanced processes. To avoid this, RBB should
use the lowest effective voltages. This suggests that there is an optimum
substrate voltage for which the total leakage current is at a minimum.
When Vss is increased to apply RBB while reducing Vdd - Vss to
approximately 350 mV with a VDD value of 1 V. In addition to the RBB effect
on IOFF, this rail-to-rail voltage reduction limits GIDL, drain to bulk
tunneling, and gate leakage components while applying approximately 650 mV
body bias to the NMOS transistors. The amount of power supply collapse is
limited because an excessive collapse of the core voltage would result in non-
state-retentive sleep mode, which is undesirable in many applications. Briefly,
state loss occurs when the total leakage current of the transistors holding a logic
state exceeds that of the “on” transistors.
The drawbacks of gating the power supply is
• This method become less effective as the supply voltage is scaled down
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CHAPTER 3
METHODOLOGY
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Gate tunneling current furthermore has a strong dependence on
the Vgs and Vgd of a device, leading to state dependence. The maximum gate
tunneling current and for the occurs when the input is at Vdd and Vs= Vd= 0v
for the gate nMOS device. In this case, tunneling current is at its maximum with
equal current flowing to the source and drain nodes. At the same time, the
pMOS device exhibits subthreshold leakage current. As the input voltage is
decreased, is reduced by more than one order of magnitude when Vgs = Vth,
nmos and becomes zero when Vgs=0.
As the input voltage decreases and the output voltage increases, Vgd will
become negative resulting in a reverse gate tunneling current from the drain to
the gate node. However, this reverse gate tunneling occurs when the nMOS
transistor is off and tunneling is restricted to the gate-to-drain overlap region,
due to the absence of a channel as shown in Figure 3.1. Since the gate-to-drain
overlap region is substantially smaller than the channel region, reverse
tunneling current is much smaller than the forward tunneling current when the
device is on, and hence can be ignored.
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Tanner EDA tools are used by more than 25,000 engineers for
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help them speed from concept to silicon efficiently. Some of the products
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for cell phones and notebook PCs.
3.2.1 T-SPICE
The essential analog design tool in the Tanner EDA Tool Suite
offers significant improvements in simulation speed and robustness. It delivers
smooth and efficient design flow from schematic to simulation to waveform
viewing. T-Spice offers options and commands not found in Berkeley SPICE or
most derivatives, such as design optimization, Monte Carlo analysis, multi-
dimensional parameters, or source and temperature sweeping. Tightly integrated
with Tanner EDA’s S-Edit schematic capture tool, T-Spice provides a state-of-
the-art analog design environment at an affordable price.
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3.2.2 S-EDIT
S-Edit, Tanner EDA’s schematic capture tool, has been completely re-
architected and rebuilt into a new tool with user interface, performance and
interoperability enhancements added. New is the ability to probe element and
sub-circuit terminal currents and charges. S-Edit uses the TCL scripting
language, which makes it fully expandable, as well as enabling easy
modification of current designs. Integrated productivity tools, such as Design
Checker and Library Browser, plus multiple libraries and language support for
English, Chinese, Russian and Japanese, all combine to deliver a comprehensive
and interactive design environment.
In addition, S-Edit supports integrated analog simulation with
automatic conversion from Cadence® and View Draw® schematics. Users can
run simulations and cross-probe from S-Edit, making the design process real-
time and more efficient. The ability to view operating point simulation results
directly on the schematic is another S-Edit productivity enhancing feature.
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CHAPTER 4
RESULTS AND DISCUSSION
The Full Adder circuit and Array multiplier is simulated using SPICE tool.
From that response the advantage of the proposed system can be clearly known
C B A S C+1
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
4.1.1 SCHEMATIC:
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Figure - 4.1 : SCHEMATIC DIAGRAM OF 28T FULL ADDER WITH
OUT DUAL THRESHOLD
4.1.2 WAVEFORM :
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Figure 4.2 Output waveform
4.1.3 POWER RESULTS
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Average power consumed -> 1.273518e-005 watts
Max power 2.593316e-005 at time 1.21014e-006
Min power 2.069169e-028 at time 1.45456e-006
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4.2.1 SCHEMATIC:
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Figure - 4.3 : Schematic Diagram of 28T Full Adder With Dual Threshold
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4.2.2. WAVE FORM
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4.3 4X 4 ARRAY MULTIPLIER WITHOUT DUAL THRESHOLD
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4.3.2 SCHEMATIC:
Figure 4.6 Schematic Diagram of 4x4 array Multiplier without dual threshold
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4.3.3. WAVE FORM
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4.4 4X 4 ARRAY MULTIPLIER WITH DUAL THRESHOLD
4.4.1. SCHEMATIC:
Figure 4.8 Schematic Diagram of 4x4 array Multiplier with dual threshold
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4.4.2. WAVE FORM
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4.5 POWER ANALYSIS TABLE
Circuits Average power consumed
(watts)
Full adder with out dual threshold 1.273518e-005 watts
Full adder with dual threshold 4.169098e-009 watts
Array Multiplier without dual threshold 4.365293e-008 watts
Array Multiplier with dual threshold 8.565493e-010 watts
CHAPTER 5
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CONCLUSION AND PHASE II WORK SCHEDULE
5.1 CONCLUSION
The leakage power has been reduced for the circuits like Full Adder
circuit and Array Multiplier using Dual threshold method. This technique can be
applied to complex circuit so that the Leakage power can be reduced. This
method has 40 to 50% leakage power reduction. This project is carried out by
tanner EDA simulation tool.
5.2 WORK SCHEDULE FOR PHASE II:
The work for the phase II is scheduled to be the design of the low
power FIR filter with the designed dual threshold adder and the 4×4 Array
Multiplier.
REFERENCES
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1. Anindya ghosh, Debapriyo ghosh, “Optimization of Static Power,
devices for 1 V operation,” IEICE Trans. Electron., vol. E79-C, no. 12,
pp. 1720–1724, 1996.
7. Panda, S. Kumar, N.M. Sarkar, “Transistor count optimization of
conventional CMOS full adder with submicron channel length”
International conference Computer and devices for communication 2009.
8. S. Shigematsu et. al., “A 1-V high speed MTCMOS circuit scheme for
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