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NS HIP6602
® W
R NE UCT
S
D E D FO E PROD 4B)
M EN TUT d ISL661
COM SUBSTI Data
R E
NOT SSIBLE A, an Sheet August 2000 FN4838.1
O I S L 6614
P ,
6014
(ISL6
TEMP. RANGE
PART NUMBER (°C) PACKAGE PKG. NO. PWM1 1 14 VCC
LGATE1 4 11 BOOT1
PVCC 5 10 BOOT2
PGND 6 9 UGATE2
LGATE2 7 8 PHASE2
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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HIP6602
Block Diagram
PVCC BOOT1
UGATE1
VCC
+5V
PHASE1
SHOOT-
10K THROUGH
PROTECTION
PWM1 PVCC
10K LGATE1
PGND PGND
CONTROL
+5V
LOGIC
PVCC BOOT2
10K
UGATE2
PWM2
PHASE2
SHOOT-
10K THROUGH
PROTECTION
GND PVCC
LGATE2
HIP6602
PGND
Typical Application - 2 Channel Converter Using a HIP6302 and a HIP6602 Gate Driver
+5V
+12V BOOT1
+12V
FB COMP UGATE1
VCC
VSEN VCC
PHASE1
ISEN1
PWM2
PWM2 UGATE2
ISEN2 PHASE2
FS/DIS
LGATE2
GND
GND PGND
2
HIP6602
Typical Application - 4 Channel Converter Using a HIP6303 and HIP6602 Gate Driver
UGATE1
VCC
PHASE1
LGATE1
+5V
DUAL PVCC
DRIVER +5V/12V
HIP6602
FB COMP BOOT2 +12V
VSEN VCC
UGATE2
ISEN1
PWM1 PHASE2
PGOOD PWM1
PWM2
EN PWM2
LGATE2
ISEN2
MAIN
CONTROL
GND PGND
VID HIP6303
+VCORE
ISEN3
FS/DIS PWM3
+12V BOOT3 +12V
PWM4
GND ISEN4
UGATE3
VCC
PHASE3
LGATE3
DUAL PVCC
DRIVER +5V/12V
HIP6602
BOOT4 +12V
UGATE4
PWM3 PHASE4
PWM4
LGATE4
GND PGND
3
HIP6602
Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
Maximum Operating Junction Temperature. . . . . . . . . . . . . . . 125°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V ±10%
Supply Voltage Range PVCC . . . . . . . . . . . . . . . . . . . . . 5V to 12V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
4
HIP6602
Functional Pin Descriptions PHASE pin. The bootstrap capacitor provides the charge to
turn on the upper MOSFETs. See the Internal Bootstrap
PWM1 (Pin 1) and PWM2 (Pin 2) Device section under DESCRIPTION for guidance in
The PWM signal is the control input for the driver. The PWM choosing the appropriate capacitor value.
signal can enter three distinct states during operation, see the
three-state PWM Input section under DESCRIPTION for further VCC (Pin 14)
details. Connect this pin to the PWM output of the controller. Connect this pin to a +12V bias supply. Place a high quality
bypass capacitor from this pin to GND. To prevent forward
GND (Pin 3) biasing an internal diode, this pin should be more positive
Bias and reference ground. All signals are referenced to this then PVCC during converter start-up.
node.
Description
LGATE1 (Pin 4) and LGATE2 (Pin 7)
Lower gate drive outputs. Connect to gates of the low-side Operation
power N-Channel MOSFETs. Designed for versatility and speed, the HIP6602 two channel,
dual MOSFET driver controls both high-side and low-side
PVCC (Pin 5)
N-Channel FETs from two externally provided PWM signals.
This pin supplies the upper and lower gate drivers bias.
Connect this pin from +12V down to +5V. The upper and lower gates are held low until the driver is
initialized. Once the VCC voltage surpasses the VCC Rising
PGND (Pin 6) Threshold (See Electrical Specifications), the PWM signal
This pin is the power ground return for the lower gate takes control of gate transitions. A rising edge on PWM
drivers. initiates the turn-off of the lower MOSFET (see Timing
Diagram). After a short propagation delay [TPDLLGATE], the
PHASE2 (Pin 8) and PHASE1 (Pin 13)
lower gate begins to fall. Typical fall times [TFLGATE] are
Connect these pins to the source of the upper MOSFETs provided in the Electrical Specifications section. Adaptive
and the drain of the lower MOSFETs. The PHASE voltage is shoot-through circuitry monitors the LGATE voltage and
monitored for adaptive shoot-through protection. These pins determines the upper gate delay time [TPDHUGATE] based
also provide a return path for the upper gate drive. on how quickly the LGATE voltage drops below 1.0V. This
UGATE2 (Pin 9) and UGATE1 (Pin 12) prevents both the lower and upper MOSFETs from
conducting simultaneously or shoot-through. Once this delay
Upper gate drive outputs. Connect to gate of high-side
period is complete the upper gate drive begins to rise
power N-Channel MOSFETs.
[TRUGATE] and the upper MOSFET turns on.
BOOT 2 (Pin 10) and BOOT 1 (Pin 11)
Floating bootstrap supply pins for the upper gate drivers.
Connect the bootstrap capacitor between these pins and the
Timing Diagram
PWM
TPDHUGATE
TPDLUGATE
TRUGATE
TFUGATE
UGATE
LGATE
TRLGATE
TFLGATE
TPDLLGATE TPDHLGATE
5
HIP6602
A falling transition on PWM indicates the turn-off of the The bootstrap capacitor must have a maximum voltage
upper MOSFET and the turn-on of the lower MOSFET. A rating above PVCC + 5V. The bootstrap capacitor can be
short propagation delay [TPDLUGATE] is encountered chosen from the following equation:
before the upper gate begins to fall [TFUGATE]. Again, the
Q GATE
adaptive shoot-through circuitry determines the lower gate C BOOT ≥ ------------------------
∆V BOOT
delay time, TPDHLGATE. The PHASE voltage is monitored
and the lower gate is allowed to rise after PHASE drops
below 0.5V. The lower gate then rises [TRLGATE], turning Where QGATE is the amount of gate charge required to fully
on the lower MOSFET. charge the gate of the upper MOSFET. The ∆VBOOT term is
defined as the allowable droop in the rail of the upper drive.
Three-State PWM Input
As an example, suppose a HUF76139 is chosen as the
A unique feature of the HIP6602 drivers is the addition of a
upper MOSFET. The gate charge, QGATE , from the data
shutdown window to the PWM input. If the PWM signal
sheet is 65nC for a 10V upper gate drive. We will assume a
enters and remains within the shutdown window for a set
200mV droop in drive voltage over the PWM cycle. We find
holdoff time, the output drivers are disabled and both
that a bootstrap capacitance of at least 0.325µF is required.
MOSFET gates are pulled and held low. The shutdown state
The next larger standard value capacitance is 0.33µF.
is removed when the PWM signal moves outside the
shutdown window. Otherwise, the PWM rising and falling Gate Drive Voltage Versatility
thresholds outlined in the ELECTRICAL SPECIFICATIONS The HIP6602 provides the user flexibility in choosing the
determine when the lower and upper gates are enabled. gate drive voltage. Simply applying a voltage from 5V up to
Adaptive Shoot-Through Protection 12V on PVCC will set both driver rail voltages.
6
HIP6602
PVCC and VCC pins. The bootstrap capacitor value in the tied together and to a +12V supply. Figures 5 through 7
test circuit is 0.01µF. show the same characterization for PVCC tied to +5V
instead of +12V. The gate supply voltage, PVCC, within the
The power dissipation approximation is a result of power
HIP6602 sets both upper and lower gate driver supplies at
transferred to and from the upper and lower gates. But, the
the same 5V level for the last three curves.
internal bootstrap device also dissipates power on-chip
during the refresh cycle. Expressing this power in terms of
Test Circuit
the upper MOSFET total gate charge is explained below.
+5V OR +12V
The bootstrap device conducts when the lower MOSFET or +5V OR +12V
+12V
its body diode conducts and pulls the PHASE node toward 0.01µF
GND. While the bootstrap device conducts, a current path is
PVCC BOOT1
formed that refreshes the bootstrap capacitor. Since the 2N7002
upper gate is driving a MOSFET, the charge removed from 0.15µF
UGATE1
the bootstrap capacitor is equivalent to the total gate charge CU
PHASE1
of the MOSFET. Therefore, the refresh power required by VCC
the bootstrap capacitor is equivalent to the power used to 0.15µF LGATE1
charge the gate capacitance of the upper MOSFETs. PWM1 100kΩ
2N7002
P REFRESH = f SW Q V = f SW Q V CL
LOSS PVCC U PVCC
HIP6602
PGND
where QLOSS is the total charge removed from the bootstrap 0.01µF
capacitors and provided to the upper gate loads. BOOT2
GND
2N7002
In Figure 1, CU and CL values are the same and frequency
UGATE2
is varied from 10kHz to 2MHz. PVCC and VCC are tied CU
together to a +12V supply. PWM2 PHASE2
Figure 2 shows the dissipation in the driver with 1nF loading LGATE2
on both gates and each individually. Figure 3 is the same as 2N7002 100kΩ
Figure 2 except the capacitance is increased to 3nF. CL
POWER (mW)
CL = 1nF, CU = 0nF
600 600
CU = CL = 2nF
400 400
CU = 1nF, CL = 0nF
CU = CL = 1nF
200 200
0 0
0 500 1000 1500 0 500 1000 1500 2000
FREQUENCY (kHz) FREQUENCY (kHz)
7
HIP6602
1200
1200
PVCC = VCC = 12V PVCC = VCC = 12V
1000
1000
CU = CL = 3nF 500kHz
800
POWER (mW)
800
POWER (mW)
600
600 CU = 3nF, CL = 0nF
200kHz
CL = 3nF, CU = 0nF 400
400
100kHz
10kHz
200 200
30kHz
0 0
0 500 1000 1500 1 2 3 4 5
FREQUENCY (kHz) GATE CAPACITANCE (CU = CL ), (nF)
800 350
PVCC = 5V, VCC = 12V CU = CL = 5nF PVCC = 5V, VCC = 12V
700 300
CU = CL = 4nF
CU = CL = 1nF
600
CU = CL = 3nF 250
POWER (mW)
500
POWER (mW)
CL = 1nF, CU = 0nF
200
400
150
300 CU = 1nF, CL = 0nF
CU = CL = 2nF 100
200
CU = CL =1nF
100 50
0 0
0 500 1000 1500 2000 0 500 1000 1500 2000
FREQUENCY (kHz) FREQUENCY (kHz)
FIGURE 5. POWER DISSIPATION vs FREQUENCY, PVCC = 5V FIGURE 6. POWER DISSIPATION vs FREQUENCY, PVCC = 5V
600
PVCC = 5V,
VCC = 12V
500
1.5MHz
2MHz 1MHz
400
POWER (mW)
300
500kHz
200
100kHz
200kHz
100
30kHz
0
1 2 3 4 5
GATE CAPACITANCE (CU = CL), (nF)
8
HIP6602
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