2011.01.12.

RayeR's homepage / FlashROM SPI pr…

FlashROM SPI programmer for parallel port

March 23, 2008 Since I am such a meddler, what you like tinkering in the BIOS codes and can not have peace until the screen nezčerná
good:) and also need to be able to manually reprogram FlashROM. Before I flashek in parallel, which were on board or in DIL32 PLCC32
socket, hotflash easily solved, when I had prepared in advance of the second chip with a BIOS function. The one I put into the slot in exchange
for running poorly programmed and reprogrammed chip.
Now I'm on my new motherboard Gigabyte GA-P31-DS3L met with a new type of memory - high-speed SPI FlashROM Winbond
25X40VSIG SMD SO8 case, which is soldered directly onto the plate. South bridge Intel ICHx no longer support both variants FWH and SPI.
With certain chipset registers and pins can be selected by the interface is primarily used for BIOS. Because of the SMD components will save
a dime at base, generally reducing the costs of production and managers to have more $ for better cars and bitches;). We then left šťouralům
than pick up a soldering iron ... To be with the flash could reasonably work připájel I had the exact DIL8 slot. Second base, then I DIL8 připájel
the motherboard. Because I would be there for the solder around the base (opposite the SATA connector) you get, I let it dangle on two pieces
of 4-wire braces:

Followed by a production programmer. The SPI device connected to the PC but just an ordinary parallel port, 5 wire, a few resistors and
connectors. Participation is based on the type of cable programming SPI BSD for programming Atmel AVR microcontrollers. Advertised
W25X40V memory is designed for 3.3 V supply voltage, so I separated the data line resistors, to suffer more stress from LPT. It also serves as
a damping resistor, because without them for very long (1.5 m) flat cable with no shielding between the signal line causing crosstalk and the
incorrect data. Interestingly, the AVR MCU me with the same function without the hassle of cables. I used to power an external source.

The whole thing then pay back the universal plošňáku looks like this:

http://rayer.ic.cz/elektro/spipgm.htm 1/2
2011.01.12. RayeR's homepage / FlashROM SPI pr…

Another thing that is only software I had to write. First, it was necessary to program the lowest layer, which works with LPT registers and
sets / reads the required level of the SPI lines. On this topic I refer to the book Burkhard Kainka - Using the PC interface of the HEL Publisher
1997, from which I once taught how to blink, its first LED on the LPT. But the Internet is a resource on this subject more than enough.
Furthermore, I would have said something to the SPI bus itself. It consists of three lines: SCK - Serial Clock (up to tens of MHz), MISO -
Master Output Slave Input, MOSI - Master Output Slave Input in this case, there is also an auxiliary control line # CS - Chip Select. The
communication typically takes place between two devices, one of which is the master (in this case the PC), which controls the SCK clock (there
is a resting level of 0.) And sends commands / data on MOSI line while simultaneously reads data from the MISO line. Slave device (in this
case memory) then responds to the clock SCK by the falling edge of clock sends a bit on the MISO line and on the rising edge of bit clock
reads MOSI line. Byte is sent in MSB first, LSB last. After completion of the transfer master clock returns to idle level (logical 0). The bus is
therefore contrary to the I2C to be full duplex. Slave devices do not identify any address. In order to connect to multiple slave SPI lines, it must
be master of every device connected to a separate control line CS # to the log. 0 Zn activates a slave device (the others have SPI outputs in
high impedance state to affect the ongoing communication (SPI devices have a 3-state outputs are required pull-ups). In the case of SPI Flash
memory is used for CS # start and end frame so that it can not be conveniently connected to the ground. more tell how the next picture is being
read from memory:

First, the Master will start moving beyond CS # to the log. 0 and the memory is activated. Then the master clock and starts sending first byte
command 3h - reading from memory. Memory figuring out what on earth is it for her and we know that it has yet to address. Then the master
sends the next 3 bytes. Memory address decoding and immediately starts another byte to send data. If the master requests data from the
following addresses, hours and leave it automatically increments the memory address. Other incoming data from the master are ignored. End
of the master frame shift close to idle hours log. 0 and CS # transition to idle state log. 1st
Memory supports a standard set of commands, including the need to read, write, delete pages, erasing sectors, erasing the entire chip,
lock, unlock, identifying the manufacturer and type of chip JEDEC, reading the status register ... Some are single-byte commands, with different
parameters and data. Some memory corresponds sending data, the others are not. For more details, see the datasheet for more memory.
The next step was to then write a function for sending and receiving blocks of flats and data processing functions for the end of each Flash
memory orders. The current version allows you to identify the type of mind / I see and read the data block size from the address / y read the
entire file into memory / d, a programmable memory of the / p, delete all the memory / e to unlock the write protect bits / u . Other parameters / l
= You can set the base address and the LPT / d = extension of the SCK pulse in microseconds (excluding the Windows version, where the
timer is not available with higher resolution than 1 ms). The download package are 3 versions of DOS, Windows and Linux (Linux version I
tested).
Due to the limited speed of the LPT and serial transmission mode read or write takes tens of seconds to minutes. Chip erase time
depends on the speed of the internal mechanisms of memory and takes about ten seconds to drive. Faster communication would be achieved
by the microcontroller, preferably with a hardware SPI controller, which communicates with the PC either 8-bit on LPT or USB. Demonstration
projects, with memory M25P32 Wed:

SPI FlashROM Programmer 1.0 (C) 2008 by Martin Rehak; rayer list ^ * GB Compiled by GCC 3.4.5 (mingw special) at 6:41:28 p.m., Mar 26 2008 SPI connected to the LPT port at I / O Ba

July 21, 2010 , in cooperation with people from the projects FlashROM and coreboot , which I gave the source code SPIPGM, support was
added mojeho SPI programmer flashovacího in this versatile instrument. At the same time also created the DOS version (compiled under
DJGPP ), you can download here . Users had the opportunity to flashromu programming through LPT port and users SPIPGM again broad
support for different types of flash memory. SPI to LPT port programmer to select the:
FlashROM rayer_spi-p [other instructions]

I did a comparison test with four megabytes memory FlashROM M25P32 Wed:

Program reading lubrication

SPIPGM 2:41 0:21 (without verification)
FlashROM 2:44 3:34 (with verification)

Speed reading is on par, while deletion is in flashromu slower because it has forced the verification (ie a complete reading). In addition, I use a
single chip erase command. The current version flashromu currently no indicator of the operations performed, so do not panic and go for coffee
in the meantime:)

Back

Updated July 28, 2010 at 1:29

http://rayer.ic.cz/elektro/spipgm.htm 2/2