Report 1111

Intelligent device for blinds in traffic areas
CHAPTER 1
INTRODUCTION
According to the World Health Organization, there are 45 million blind people in the world,
which amounts to an estimated 1h to 2h of the population in industrialized countries. This figure
cannot be neglected, and the problems encountered by blind people in their everyday life need to be
addressed. In particular, these people are faced with huge difficulties moving in cities, where
streets, public transportation systems and shopping malls represent hostile ever-changing
environments. As a result, blind people are in danger while moving on their own, and their
autonomy is limited. Indeed, if blind people can generally remember their way to some places, they
cannot know in advance what obstacles they will stumble upon. In consequence, the fear of the
unknown often leads them to restrict their universe to a small set of known places. They do not dare
going anywhere else, thus experiencing limited travel freedom. This is the reason why numerous
electronic locomotion assistance systems have been developed.Electronic devices are significantly
cheaper
It is a novel project that is aimed to develop a device with which the blind would be able to
autonomously detect important information for safely negotiating pedestrian crossing in traffic
areas. We design and develop a micro controller based solution for the blind which can bring him
confidence and can be a accident preventive mechanism in the real time world.
In this project we use the RF transmitter kept ion the traffic signals and this is controlled by
the micro controller as shown in the block diagram above, as the traffic signals keeps on changing ,
the micro controller will transmit the status through the RF TX continuously. The main aim of the
project is to design and develop an intelligent device for the blind such that it can help them in the
places like the traffic signals.When the blind person comes close to the traffic signal, he will have
an Receiver which will pick up the traffic signal status and then it will tell the same using the
speech processing unit . It can tell him that its read now and later it will tell him its about to change
to green and green now and now its again changing to red and in the same way it will be in the loop
continuously. The project is developed using the ARM micro controller and the 8051 micro
controller together.
CHAPTER 2
DEPT OF ECE,RYMEC Page 1

SYSTEM DEVELOPMENT
Now we are coming to know what are the hardware parts used in our projects and what are
the activities of each part and their features. The figure 2.1 shows the block diagram of our project.
Our project employs a ARM micro-controller based design. We use the RF transmitter kept
in the traffic signals and this is controlled by the micro controller as shown in the block diagram
below, as the traffic signals keeps on changing, the micro controller will transmit the status
through the RF transmitter continuously.
When blind person comes close to the traffic signal, he will have an receiver which will pick
up the traffic status and then it will tell the same using the speech processing unit. It can tell him
that its red now and later it will tell him its about to change to green and green now and now its
again changing to red and in the same way it will be in loop continuously.
We have used two sensors and depending on the sensor activation, it can detect any obstacle
either towards right or towards left which is again conveyed using a speech processing unit.
Thus this device can be life saving and very helpful for the blind people throughout the world.
2.1BLOCK DIAGRAM:

TRANSMITTER SIDE
○ RED
MICROCONTROLL DRIVER UNIT
○ ORANG
ER
E
○ GREEN
RF Tx
RECEIVER SIDE
RIGHT
SENSOR
RF Rx DECODE MICROCONTROL DRIVER

R LER UNIT
LEFT SPEECH SPEAK

UNIT
Fig 2.1:depicting the hardware arrangement in model
2.2 ARM MICROCONTROLLER

The ARM is a 32-bit reduced instruction (RISC) instruction set architecture (ISA) developed
by ARM Holdings. It was known as the Advanced RISC Machine, and before that as the Acorn
RISC Machine. The ARM architecture is the most widely used 32-bit ISA in terms of numbers
produced. They were originally conceived as a processor for desktop personal computers
by Computers, market now dominated by the x86 family used by IBM PC compatible
and Apple Macintosh computers. The relative simplicity of ARM processors made them suitable for
low power applications. This has made them dominant in the mobile and embedded electronics
market, as relatively low cost, and small microprocessors and microcontrollers.
The ARM7TDMI is a member of the Advanced RISC Machines (ARM) family of general
purpose 32-bit microprocessors, which offer high performance for very low power consumption
and price. The ARM architecture is based on Reduced Instruction Set Computer (RISC)
principles, and the instruction set and related decode mechanism are much simpler than those of
micro programmed Complex Instruction Set Computers. This simplicity results in a high
instruction throughput and impressive real-time interrupt response from a small and cost-effective
chip. Pipelining is employed so that all parts of the processing and memory systems can operate
continuously. Typically, while one instruction is being executed, its successor is being decoded,
and a third instruction is being fetched from memory.
The ARM memory interface has been designed to allow the performance potential to be
realised without incurring high costs in the memory system. Speed-critical control signals are
pipelined to allow system control functions to be implemented in standard low-power logic, and
these control signals facilitate the exploitation of the fast local access modes offered by industry
standard dynamic RAMs.
2.2.1Basic Characteristics of ARM7TDMI

The principle feature of the ARM 7 microcontroller is that it is a register based load and-
store architecture with a number of operating modes. While the ARM7 is a 32 bit microcontroller, it
is also capable of running a 16-bit instruction set, known as “THUMB”. This helps it achieve a
greater code density and enhanced power saving. While all of the register-to-register data
processing instructions are single-cycle, other instructions such as data transfer instructions, are
multi-cycle. To increase the performance of these instructions, the ARM 7 has a three-stage
pipeline. Due to the inherent simplicity of the design and low gate count, ARM 7 is the industry
leader in low-power processing on a watts per MIP basis. Finally, to assist the developer, the ARM

core has a built-in JTAG debug port and on-chip “embedded ICE” that allows programs to be
downloaded and fully debugged in-system. In order to keep the ARM 7 both simple and cost-
effective, the code and data regions are accessed via a single data bus. Thus while the ARM 7 is
capable of single-cycle execution of all data processing instructions, data transfer instructions may
take several cycles since they will require at least two accesses onto the bus (one for the instruction
one for the data). In order to improve performance, a three stage pipeline is used that allows
multiple instructions to be processed simultaneously. The pipeline has three stages; FETCH,
DECODE and EXECUTE. The hardware of each stage is designed to be independent so up to three
instructions can be processed simultaneously. The pipeline is most effective in speeding up
sequential code. However a branch instruction will cause the pipeline to be flushed marring its
performance.
ARM7TDMI BLOCK DIAGRAM

Scan Chain 2 Scan Chain 0
RANGEOUT0
RANGEOUT1
ICEBreaker
EXTERN1
EXTERN0
nOPC
nRW
MAS[1:0]
All
nTRANS Core Other
nMREQ
A[31:0] Signals
•
Scan Chain
1
D[31:0]
DIN[31:0] Splitter
•
DOUT[31:0] Bus
TAP controller

TCK TMS nTRST TDI TDO TAPSM[3:0] IR[3:0] SCREG[3:0]
Fig 2.1.1 block diagram of ARM7TDMI
2.2.2ARM7TDMI Processor core

The ARM7TDMI embedded CPU core is part of Fujitsu’s IPWare™ Library. The
Fujits ARM7TDMI processor core,developed by ARM, is implemented in Fujitsu’s
0.25µm process technology. This core contains all of the ARM7TDMI processor features,
including a 32-bit RISC engine, Thumb instruction set (smaller code size), debug
functions, multipli-er, and embedded ICE support logic. The ARM7TDMI processor is
supported by multiple hardware and software vendors through a wide array of
development tools and RTOS created by ARM. The ARM7TDMI processor supports
speeds up to 100 MHz(typical case) at 2.5V and 66 MHz (worst case) at 2.3V, 125C,
process slow. The core will consume 0.6 mW per MHz
2.2.3 The THUMB Concept

The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the
ARM7TDMI processor has two instruction sets:
• the standard 32-bit ARM set
• a 16-bit THUMB set
The THUMB set’s 16-bit instruction length allows it to approach twice the density of standard
ARM code while retaining most of the ARM’s performance advantage over a traditional 16-bit
processor using 16-bit registers. This is possible because THUMB code operates on the same 32-bit
register set as ARM code.
2.2.4Processor Operating States

From the programmer’s point of view, the ARM7TDMI can be in one of two states: ARM
state which executes 32-bit, word-aligned ARM instructions. THUMB state which operates with
16-bit, half word-aligned THUMB instructions. In this state, the PC uses bit 1 to select between
alternate half words. Transition between these two states does not affect the processor mode or the
contents of the registers.

Switching State
Entering THUMB state
Entry into THUMB state can be achieved by executing a BX instruction with the state bit
(bit 0) set in the operand register. Transition to THUMB state will also occur automatically on
return from an exception (IRQ, FIQ, UNDEF, ABORT, SWI etc.), if the exception was entered with
the processor in THUMB state.
Entering ARM state

Entry into ARM state happens:
1. On execution of the BX instruction with the state bit clear in the operand register.
2 .On the processor taking an exception (IRQ, FIQ, RESET, UNDEF, ABORT,SWI etc.). In this
case, the PC is placed in the exception mode’s link register, and execution commences at the
exception’s vector address.
2.1.5 Memory Formats

ARM7TDMI views memory as a linear collection of bytes numbered upwards from zero.
Bytes 0 to 3 hold the first stored word, bytes 4 to 7 the second and so on. ARM7TDMI can treat
words in memory as being stored either in Big Endian or Little Endian format.
Big Endian format

In Big Endian format, the most significant byte of a word is stored at the lowest numbered byte and
the least significant byte at the highest numbered byte. Byte 0 of the memory system is therefore
connected to data lines 31 through 24.
Higher Address 31 24 23 16 15 8 7 0 Word Address

8 9 10 11 8
4 5 6 7 4
0 1 2 3 0
Lower Address • Most significant byte is at lowest address
• Word is addressed by byte address of most significant byte
Figure 2.1.5(a): Big endian addresses of bytes within words
Little Endian format

In Little Endian format, the lowest numbered byte in a word is considered the word’s least
significant byte, and the highest numbered byte the most significant. Byte 0 of the memory system
is therefore connected to data lines 7 through 0.
Higher Address 31 24 23 16 15 8 7 0 Word Address

11 10 9 8 8
7 6 5 4 4
3 2 1 0 0
Lower Address • Least significant byte is at lowest address
• Word is addressed by byte address of least significant byte
Figure2.1.5(b): Little endian addresses of bytes within words
2.1.6 ARM7 INTERNALS core block diagram

Fig 2.1.6
ARM7 INTERNALS
• ARM core modes of operation:

• User (usr): Normal program execution state
• FIQ (fiq): Data transfer state (fast irq, DMA-type transfer)
• IRQ (iqr): Used for general interrupt services
• Supervisor (svc): Protected mode for operating system support
• Abort mode (abt): Selected when data or instruction fetch is aborted
• System (sys): Operating system ‘privilege’-mode for user
• Undefined (und): Selected when undefined instruction is fetched
2.1.7 ARM7 register set
Fig 2.1.7
The ARM7TDMI contains a Current Program Status Register (CPSR), plus five Saved
Program Status Registers (SPSRs) for use by exception handlers. These registers
• hold information about the most recently performed ALU operation
• control the enabling and disabling of interrupts
• set the processor operating mode
The arrangement of bits is shown in Figure 2.1.7: Program status register format
The condition code flags

The N, Z, C and V bits are the condition code flags. These may be changed as a result of
arithmetic and logical operations, and may be tested to determine whether an instruction should be
executed.In ARM state, all instructions may be executed conditionally.
The control bits

The bottom 8 bits of a PSR (incorporating I, F, T and M[4:0]) are known collectively as the control
bits. These will change when an exception arises. If the processor is operating in a privileged
mode,they can also be manipulated by software.
The T bit::This reflects the operating state. When this bit is set, the
processor is executing in THUMB state, otherwise it is
executing in ARM state. This is reflected on the TBIT
external signal.
Note that the software must never change the state of the
TBIT in the CPSR. If this happens, the processor will
enter an unpredictable state

2.1.8THUMB EXTENSION
• Thumb-instruction decoder is placed

in pipeline
• Change to Thumb-mode happens by
turning the state of multiplexers feeding
the instruction decoders and data bus
• A1 selects the 16-bit half word from
the 32-bit bus
Example of instruction conversion

Thumb-instruction:ADD
Rd,#constant is converted to
unconditionally executed ARM-

instruction ADD Rd,Rn,#constant

Only the lower register set is in use
so the upper register bit is fixed to
zero and source and destination are
equal. The constant is also 8-bit
instead of 12-bit available in ARM-
mode
2.1.9 Thumb-state registers
• Only lower part of the register immediately available
• Upper register set (R8-R15) can be used with assembler code
• Instructions MOV, CMP and ADD are available between register sets

2.2Wireless Transmitter Module - TX1 - 433.92MHZ
Features:
 Complete RF Transmitter Module no
external components and no tuning

required.
 High Performance SAW Based
Architecture with a Maximum Range of
100 feet at 4800 bps data rate.
 Interface directly to Encoders and
Microcontrollers with ease.
1 2 3 4
 Low Power Consumption suitable for
battery operated devices.
 4 Pin Compact size module

Pin Details:  Can be directly used in your PCB
 Straight Pin out is the standard in
These modules.
PIN 1 RF OUT
 Right angle Pin out is optional
PIN 2 DATA IN
 Can be used with Fixed Code and
PIN 3 GROUND
PIN 4 VCC Rolling Code Encoders or direct with

microcontrollers
2.2.1Specification
PARAMETER MINIMUM TYPICAL RANGE UNITS

Modulation method ON-OFF KEYED (OOK) Modulation (AM)
Voltage 2.7 3 5.2V DC
Supply Current 5 5.5 mA
Stand by Current 3 micro A
Output power into
-2 0 0 dBm
50ohms
Overall frequency
-250 250 KHz
accuracy
Data input low 0 0.8 Volts
Data input High >0.8 Vcc Volts
Operating temp. Range 0 70 Deg. Cel
Operating frequencies 433.67 433.92 434.17 MHZ
Max. Data rate 2400 Bps
Antenna External1/4 Wave Whip, Helical or PCB Trace
Package SMD
2.3Wireless Receiver Module - RX1- 433.92 MHZ

2.3.1Introduction:
This is the Radio Frequency Receiver Module, which can facilitate the designers to design
their remote control applications in the quickest way. The circuit is designed with SMD components
and the module size is small enough to fit in to any application. This Receiver Module is Super-
Regenerative Version Without Decoder using Amplitude Modulation or in other words ON-OFF
Keyed Modulation (OOK)
Application Note:
Pin 1 : Gnd
Pin 2 : Data
Pin 3 : Linear Output
Pin 4 : Vcc
Pin 5 : Vcc
Pin 6 : Gnd
Pin 7 : Gnd
Pin 8 : Antenna (About 30 – 35 cm)
Modulation: AM
Supply Voltage: 5V DC
Specifications of RX1:

Model SR Mode Power Data Rate (bps) Sensitivity (dbm) Power Consumption Modulation Channel Width
RX1 SR +5V DC 300~5K - 106 dbm 3.23 mA (5V) AM 1 MHZ
Notes:
SR: Super-Regenerative; AM: Amplitude Modulation
2.3.2Application Details:
Above RF module does not include the decoder IC, thus you have to either add the
decoder IC in your circuit or implement the decoder software in micro controller by yourself.
Our Rolling Code Decoder choices are available for your design. For Rolling Code
application, you may use Microchip’s Keeloq Encoder IC – HCS 301/P (8 Pin DIP) on the
transmitter side and HCS 512/P Keeloq Decoder IC on the Receiver side. However, we can
provide you software implemented Decoder on PIC16F628A-I/P that will provide the same
functionality like HCS512/P.
On the PCB layout of your control board, be very careful in the following point so that
no data loss can happen: During PCB layout stage, be sure that the ground of the Micro
controller and the Receiver Module are not looped. Draw out separate PCB tracks from the
Ground to the MCU ground and the Receiver Ground. Keep the ground line as short as
possible to the receiver. Also ensure that the MCU is located at about an inch away from the
Receiver Module. This is to avoid any data loss due to frequency interference.
Check with our Sales People for your requirements of programmed Rolling Code
Encoder / Decoder ICs Low Cost RF two button Remote Control with Decoder PCB, 12
output decoder, RF Relay Switch unit and Antenna. We can supply these to you as ready to
use OE sub-assemblies for integrating into your designs.
2.3.3 Noise Immunization
This RF receiver is sensitive to RF noise in the pass band because the desired transmitter
signals are at very low power levels. Some common noise sources are microprocessors, brush-type
motors and high-speed logic circuits. If the rise time and fall time of the clock in a microprocessor
are fast enough to produce harmonics in the frequency range of the receiver input and the
harmonics fall within the pass band of the receiver, then special care must be taken to reduce the
level of the harmonic at the antenna port of the receiver.

Based on above analysis, the following actions have to be taken:

• Microprocessor choice:Choose those microprocessors that has lowest rise time and lowest
fall time, if available.
• Brush-type motor choice:Choose that brush-type motor, which has spark suppression built in
or better not to use such type of motors.
• Logic circuits choice:High-speed logic circuits generate noise similar to microprocessors.
Thus better to choose those circuits with the lowest rise time and the lowest fall time, if
available.
• Place the receiver and its antenna as far from the noise source as possible.
• During PCB layout, keep line lengths at a minimum that carry high-speed logic signals or
supply brush type motors. Such lines work like antennas that radiate the unwanted noise.
• If possible, enclose the noise source in a grounded metal box and use RF-decoupling on the
input/output lines.
• It is advisable to use separate voltage regulator for the RF receiver. If the same voltage
regulator has to be used for cost purpose, then a decoupler circuit is recommended so that
high frequency noise can be screened.
• The ground path from the receiver module should go directly to the power ground, in
between, no other ground paths can join in, otherwise, noise will be introduced in and
receiver function will be greatly influenced.
2.3.4 DC Characteristics:
Symbol Parameter Conditions Min. Typ. Max. Unit
Vcc Operating Supply Voltage MIN3.5 MAX5.5 5 6
I Tot Operating Supply voltage 4.5 -
1 Data=+200µA(High) Vcc -0.5 Vcc V

V Data Data Out 1 Data = -10µA(Low) - 0.3 V
2.3.5 Electrical Characteristics:
Characteristics Sym. Min. Typ. Max. Unit
Operating Radio Frequency FC 300 - 434 Mhz

Sensitivity Pref - 119 dB
Channel Width - 500 +500 Khz
Noise Equivalent BW NEB 5 4 Khz
Baseboard Data Rate 3 Kb/s
Receiver Turn On Time 3 ms
2.4 HT12A/HT12E Series of Encoders

The encoders are a series of CMOS LSIs for remote control system applications. They are
capable of encoding information which consists of N address bits and 12ĘN data bits. Each ad-
dress/data input can be set to one of the two logic states. The programmed addresses/data are
transmitted together with the header bits via an RF or an infrared transmission medium upon receipt
of a trigger signal. The capability to select a TE trigger on the HT12E or a DATA trigger on the
HT12A further enhances the ap-plication flexibility of the 212 series of encoders. The HT12A
additionally provides a 38kHz car-rier for infrared systems.
Features
• Operating voltage :2.4V~5V for the HT12A Ę 2.4V~12V for the HT12E
• Low power and high noise immunity CMOS technology
• Low standby current: 0.1 A (typ.) at VDD=5V
• HT12A with a 38kHz carrier for infrared transmission medium
• Minimum transmission word
• Four words for the HT12E .One word for the HT12A
• Built-in oscillator needs only 5% resistor Data code has positive polarity
• Minimal external components
PIN ASSINGMENT

Pin Description
Internal
Pin Name I/O Description
Connection
CMOS IN
Pull-high
(HT12A)
NMOS Input pins for address A0~A7 setting
A0~A7 I
TRANSMISSION These pins can be externally set to VSS or left open
GATE
PROTECTION
DIODE
(HT12E)
NMOS
TRANSMISSION
GATE Input pins for address/data AD8~AD11 setting
AD8~AD11 I
PROTECTION These pins can be externally set to VSS or left open
DIODE
(HT12E)
Input pins for data D8~D11 setting and transmission en-
CMOS IN able, active low
D8~D11 I
Pull-high These pins should be externally set to VSS or left open
(see Note)
DOUT O CMOS OUT Encoder data serial transmission output
Latch/Momentary transmission format selection pin:
CMOS IN
L/MB I Latch: Floating or VDD
Pull-high
Momentary: VSS
2.5HT12D/HT12F Series of Decoders:

The 212 decoders are a series of CMOS LSIs for remote control system applications. They
are paired with HoltekŦs 212 series of encoders (refer to the encoder/de-coder cross reference table).
For proper operation, a pair of encoder/decoder with the same number of ad-dresses and data format
should be chosen. The decoders receive serial addresses and data from a programmed 2 12 series of
encoders that are transmitted by a carrier using an RF or an IR transmission medium. They compare
the serial input data three times continu-ously with their local addresses. If no error or un-matched
codes are found, the input data codes are decoded and then transferred to the output pins. The VT
pin also goes high to indicate a valid transmission.
The 212 series of decoders are capable of decoding information that consist of N bits of
address and 12ĘN bits of data. Of this series, the HT12D is arranged to pro-vide 8 address bits and
4 data bits, and HT12F is used to decode 12 bits of address information
Features
• Operating voltage: 2.4V~12V
• Low power and high noise immunity CMOS technology
• Low standby current
• Capable of decoding 12 bits of information Binary address setting
• Received codes are checked 3 times
• Address/Data number combination Ę HT12D: 8 address bits and 4 data bits Ę HT12F: 12
address bits only
• Built-in oscillator needs only 5% resistor Valid transmission indicator
• Easy interface with an RF or an infrared transmission medium
• Minimal external components
• Pair with HoltekŦs 212 series of encoders 18-pin DIP, 20-pin SOP package
Applications
• Burglar alarm system
• Smoke and fire alarm system Garage door controllers
• Car door controllers
• Car alarm system Security system
• Cordless telephones
• Other remote control systems

2.6 LPC2148 IC:
The LPC2148 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with real
time emulation and embedded trace support, that combine microcontroller with embedded high
speed flash memory ranging from 32 kB to 512 kB. A 128-bit wide memory interface and a unique
accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical code
size applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with
minimal performance penalty.
Due to their tiny size and low power consumption, LPC2148 are ideal for applications
where miniaturization is a key requirement, such as access control and point-of-sale. Serial
communications interfaces ranging from a USB 2.0 Full-speed device, multiple UARTs, SPI, SSP
to I2C-bus and on-chip SRAM of 8 kB up to 40 kB, make these devices very well suited for
communication gateways and protocol converters, soft modems, voice recognition and low end
imaging, providing both large buffer size and high processing power. Various 32-bit timers, single
or dual 10-bit ADC(s), 10-bit DAC, PWM channels and 45 fast GPIO lines with up to nine edge or
level sensitive external interrupt pins make these microcontrollers suitable for industrial control
and medical systems.
FEATURES:
• 16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.
• 8 kB to 40 kB of on-chip static RAM and 32 kB to 512 kB of on-chip flash memory. 128-bit
wide interface/accelerator enables high-speed 60 MHz operation.
• In-System Programming/In-Application Programming (ISP/IAP) via on-chip boot loader
software. Single flash sector or full chip erase in 400 ms and programming of 256 bytes in
1ms.
• EmbeddedICE RT and Embedded Trace interfaces offer real-time debugging with the on-
chip RealMonitor software and high-speed tracing of instruction execution.
• USB 2.0 Full-speed compliant device controller with 2 kB of endpoint RAM.
• In addition, the LPC2146/48 provides 8 kB of on-chip RAM accessible to USB by DMA.
• One or two (LPC2141/42 vs. LPC2144/46/48) 10-bit ADCs provide a total of 6/14 analog
inputs, with conversion times as low as 2.44 s per channel.

• Single 10-bit DAC provides variable analog output (LPC2142/44/46/48 only).

• Two 32-bit timers/external event counters (with four capture and four compare channels
each), PWM unit (six outputs) and watchdog.
• Low power Real-Time Clock (RTC) with independent power and 32 kHz clock input
• Multiple serial interfaces including two UARTs (16C550), two Fast I2C-bus (400 kbit/s),
SPI and SSP with buffering and variable data length capabilities.
• Vectored Interrupt Controller (VIC) with configurable priorities and vector addresses.
• Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package.
• Up to 21 external interrupt pins available.
• 60 MHz maximum CPU clock available from programmable on-chip PLL with settling time
of 100 s.
• On-chip integrated oscillator operates with an external crystal from 1 MHz to 25 MHz.
• Power saving modes include Idle and Power-down.
• Individual enable/disable of peripheral functions as well as peripheral clock scaling for
additional power optimization.
• Processor wake-up from Power-down mode via external interrupt or BOD.
• Single power supply chip with POR and BOD circuits:
• CPU operating voltage range of 3.0 V to 3.6 V (3.3 V  10 %) with 5 V tolerant I/O pads.
BLOCK DIAGRAM:

2.7 Fast general purpose parallel I/O (GPIO)

Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow
setting or clearing any number of outputs simultaneously. The value of the output register may be
read back, as well as the current state of the port pins.
LPC2141/42/44/46/48 introduce accelerated GPIO functions over prior LPC2000 devices:

• GPIO registers are relocated to the ARM local bus for the fastest possible I/O timing.
• Mask registers allow treating sets of port bits as a group, leaving other bits unchanged.
• All GPIO registers are byte addressable.
• Entire port value can be written in one instruction.
Features
• Bit-level set and clear registers allow a single instruction set or clear of any number of bits
in one port.
• Direction control of individual bits.
• Separate control of output set and clear.
• All I/O default to inputs after reset.
10-bit ADC
The LPC2141/42 contain one and the LPC2144/46/48 contain two analog to digital
converters. These converters are single 10-bit successive approximation analog to digital
converters. While ADC0 has six channels, ADC1 has eight channels. Therefore, total number of
available ADC inputs for LPC2141/42 is 6 and for LPC2144/46/48 is 14.
Features
• 10 bit successive approximation analog to digital converter.
• Measurement range of 0 V to VREF (2.0 V ≤ VREF ≤ VDDA).
• Each converter capable of performing more than 400,000 10-bit samples per second.
• Every analog input has a dedicated result register to reduce interrupt overhead.
• Burst conversion mode for single or multiple inputs.
• Optional conversion on transition on input pin or timer match signal.
• Global Start command for both converters (LPC2142/44/46/48 only).

2.8UARTs :
The LPC2141/42/44/46/48 each contain two UARTs. In addition to standard transmit and
receive data lines, the LPC2144/46/48 UART1 also provide a full modem control handshake
interface.
Compared to previous LPC2000 microcontrollers, UARTs in LPC2141/42/44/46/48
introduce a fractional baud rate generator for both UARTs, enabling these microcontrollers to
achieve standard baud rates such as 115200 with any crystal frequency above 2 MHz. In addition,
auto-CTS/RTS flow-control functions are fully implemented in hardware (UART1 in
LPC2144/46/48 only
Features:
• 16 byte Receive and Transmit FIFOs.
• Register locations conform to ‘550 industry standard.
• Receiver FIFO trigger points at 1, 4, 8, and 14 bytes
• Built-in fractional baud rate generator covering wide range of baud rates without a need for
external crystals of particular values.
• Transmission FIFO control enables implementation of software (XON/XOFF) flow control
on both UARTs.
• LPC2144/46/48 UART1 equipped with standard modem interface signals. This module also
provides full support for hardware flow control (auto-CTS/RTS).
CHAPTER 3
8051 MICROCONTROLLER

A microcontroller is an economical computer-on-a-chip built for dealing with specific tasks, such as
displaying or receiving information through LEDs or remote controlled devices. The most
commonly used set of microcontrollers belong to to 8051 Family. 8051 Microcontrollers continue
to remain a preferred choice for a vast community of hobbyists and professionals. Through 8051,
the world became witness to the most revolutionary set of microcontrollers.
3.18051 FAMILY
Intel fabricated the original 8051 which is known as MCS-51. The other two members of the 8051
family are:
i. 8052 – This microcontroller has 256 bytes of RAM and 3 timers. In addition to the standard
features of 8051, this microcontroller has an added 128 bytes of RAM and timer. It has 8K bytes of
on chip program ROM. The programs written for projects using 8051 microcontroller can be used
to run on the projects using 8052 microcontroller as 8051 is a subset of 8052.
ii. 8031 – This microcontroller has all the features of 8051 except for it to be ROM-less. An
external ROM that can be as large as 64 K bytes should be programmed and added to this chip for
execution. The disadvantage of adding external ROM is that 2 ports (out of the 4 ports) are used.

Hence, only 2 ports are left for I/O operations which can also be added externally if required for
execution.
Comparison of 8051 family members:

Features 8051 8052 8031
RAM(bytes) 128 256 128
ROM 4K 8K 0K
Timers 2 3 2
Serial port 1 1 1
I/O pins 32 32 32
Interrupt sources 6 8 6
3.1.1VARIOUS 8051 MICROCONTROLLERS

8051 microcontrollers use two different kinds of memory such as UV- EPROM, Flash and NV-
RAM. Hence 8051 will not be seen in the part number even though it is the most popular member
of the 8051 family.
i) 8751 – This microcontroller is the UV-EPROM version of 8051. This chip has only 4K
bytes of UV-EPROM. It is required to have access to the PROM burner and the UV-EPROM eraser
to erase the contents inside the chip before it is programmed again. The disadvantage of using this
memory is the waiting time of around 20 minutes to erase the contents in order to program it again.
Due to this limitation, manufacturers fabricated flash and NV-RAM versions of 8051.
ii ) AT89C51 from Atmel Corporation – Atmel fabricated the flash ROM version of 8051
which is popularly known as AT89C51 (‘C’ in the part number indicates CMOS). The flash
memory can erase the contents within seconds which is best for fast growth. Therefore, 8751 is
replaced by AT89C51 to eradicate the waiting time required to erase the contents and hence
expedite the development time. To build up a microcontroller based system using AT89C51, it is
essential to have ROM burner that supports flash memory. Note that in Flash memory, entire
contents must be erased to program it again. The contents are erased by the ROM burner. Atmel is
working on a newer version of AT89C51 that can be programmed using the serial COM port of
IBM PC in order to get rid of the ROM burner.
Part ROM RAM I/O pins Timer Interrupt Vcc Packaging

Number
AT89C51 4K 128 32 2 6 5V 40
AT89C52 8K 128 32 3 8 5V 40
AT89C1051 1K 64 15 1 3 3V 20
AT89C2051 2K 128 32 3 8 3V 20
AT89LV51 4K 128 32 2 6 3V 40
AT89LV52 8K 128 32 3 8 3V 40
Table – Versions of 8951 from Atmel (All ROM Flash)
There are different versions of packaging and various speed of the products mentioned in the above
table.
Part Number Speed Pins Packaging Use
AT89C51-12PC 12MHz 40 DIP Plastic Commercial
Table – Various Speeds of 8051 from Atmel
Note: The part number AT89C51-16PC where AT – Atmel, C - CMOS (consumes less
power), 12 - Speed as 12 MHz, P – Plastic DIP packaging, C - Commercial use. AT89C51-
12PC is favourably used by students for their projects.
iii) DS5000 from Dallas Semiconductor – Dallas Semiconductor fabricated the NV-RAM version
of the 8051 which is known as DS5000. The PC serial port is utilized to load the program onto the
in-built ROM. The advantage of NV-RAM memory is the facility to erase the contents one byte at a
time.
v.
Part RAM ROM Timers I/O pins Interrupts Vcc Packaging
Number
DS5000-8 128 8K 2 32 6 5V 40
DS5000- 128 32K 2 32 6 5V 40
32
DS5000T- 128 8K 2 32 6 5V 40
8
DS5000T- 128 32K 2 32 6 5V 40
8
Table – Versions of 8051 from Dallas Semiconductor

Note: ‘T’ signifies the real time clock (RTC) which is different from the timer. Even though
the power is turned off, the real – time clock generates and displays the date and the time of
day.
The variety range of speed and packaging versions of DS5000 which is shown in the Table 1.5
Part Number NV-RAM Speed
DS5000-8-8 8K 8MHz
DS5000-8-12 8K 12MHz
DS5000-32-8 32K 8MHz
DS5000-32-12 32K 12MHz
DS5000T-8-12 8K 12MHz
DS5000T-32-8 32K 8MHz
Table – Versions of 8051 Dallas Semiconductor
v) One - Time - Programmable (OTP) versions of the 8051 – This version of microcontroller is
cheaper and available from various manufacturers. The manufacturers use OTP microcontroller for
mass production because the price per unit is very cheap.
FEATURES OF 8051
The main features of 8051 microcontroller are:
• RAM – 128 Bytes (Data memory)
• ROM – 4Kbytes (ROM signify the on – chip program space)
• Serial Port – Using UART makes it simpler to interface for serial communication.
• Two 16 bit Timer/ Counter
• Input/output Pins – 4 Ports of 8 bits each on a single chip.
• 6 Interrupt Sources
• 8 – bit ALU (Arithmetic Logic Unit)
• Harvard Memory Architecture – It has 16 bit Address bus (each of RAM and ROM) and 8
bit Data Bus.
• 8051 can execute 1 million one-cycle instructions per second with a clock frequency of
12MHz.
• This microcontroller is also called as “System on a chip” because it has all the features on a
single chip. The Block Diagram of 8051 Microcontroller is as shown in Figure

3.1.2 MEMORY ARCHITECTURE
The 4 discrete types of memory in 8051 are:

i) Internal RAM – This memory is located from address 0 to 0xff. The memory locations
from 0x00 to 0x7F are accessed directly. The bytes from 0x20 to 0x2F are bit-addressable. Loading
R0 and R1 the memory location from 0x80 to 0xFF can easily accessed.
ii) Special Function Registers (SFR) – Located from address 0x80 to 0xFF of the memory
location. The same instructions used for lower half of Internal RAM can be used to access SFR’s.
The SFR’s are bit addressable too.
iii) Program Memory – This is read only memory which is located at address 0. With the help
of 16 bit Special Function Register DPTR, this memory can also save the tables of constants.
iv) External Data Memory – Located at address 0. The Instruction MOVX (Move External)
should be used to access the external data memory.

3.1.3 HISTORY OF 8051 AND KEY DEVOLOPMENTS

Intel Corporation fabricated the 8 – bit microcontroller which was referred as MCS-51 in 1981. This
microcontroller was also referred as “system on a chip” because it has 128 bytes of RAM, 4Kbytes
of ROM, 2 Timers, 1 Serial port, and four ports on a single chip. The CPU can work for only 8bits
of data at a time because 8051 is an 8-bit processor. In case the data is larger than 8 bits then it has
to be broken into parts so that the CPU can process conveniently. Most manufacturers have put
4Kbytes of ROM even though the quantity of ROM can be exceeded up to 64 K bytes.
Intel permitted other manufacturers to fabricate different versions of 8051 but with the limitation
that code compatibility should be maintained. This has added advantage that if the program is
written then it can be used for any version of 8051 despite of manufacturer.
As years passed by, the quality of technology surpassed the expectation of the greatest minds, with
gadgets becoming smaller, sleeker and more efficient. Microcontrollers were seen as the answer to
the requirements raised in advanced electronics. This is the reason why manufacturers have now
focused their production around the following main developmental aspects:
i) Ease-of-use
ii)Market availability
iii) Less power usage
iv) Smaller processing power
v) More integrated features like RF and USB
vi) Smaller form factors
3.1.4 APPLICATIONS
The 8051 has been in use in a wide number of devices, mainly because it is easy to integrate into a
project or build a device around. The following are the main areas of focus:
i)Energy Management:Efficient metering systems help in controlling energy usage in homes and
industrial applications. These metering systems are made capable by incorporating microcontrollers.

ii)Touch screens:A high number of microcontroller providers incorporate touch-sensing

capabilities in their designs. Portable electronics such as cell phones, media players and gaming
devices are examples of microcontroller-based touch screens.
iii)Automobiles: The 8051 finds wide acceptance in providing automobile solutions. They are
widely used in hybrid vehicles to manage engine variants. Additionally, functions such as cruise
control and anti-brake system have been made more efficient with the use of microcontrollers.
iv)Medical Devices:Portable medical devices such as blood pressure and glucose monitors use
microcontrollers will to display data, thus providing higher reliability in providing medical results.
3.1.5 PROGRAMMING ENVIRONMENT AND PROGRAMMER

Formerly, programmers used machine language for coding. A machine language is a
program that consists of 0s and 1s which was very dreary for the humans to program any computer.
In due course of time, assembly language was developed in order to speed up the programming and
make it error-free. Assembly language is a low level language which uses an assembler to translate
the program into machine code. The high level programming languages such as BASIC, Pascal,
Forth, C, C++, and Java are available to code the program for 8051. These high level languages
make use of a Compiler to translate into machine code. For example, when a program is written in
C, the program needs to be translated into machine language using C compiler. Usually, Assembly
and C language is widely used for 8051 programs as compared to the other high level languages.
The 8051 provides a total of four ports for I/O operations. 8051 has 40 pins, of which 32
pins are set aside for the four ports. PO, P1, P2, and P3 each have 8 pins and can be used for either
input or output. The remaining pins are designated as Vrt, GND, XTAL1, XTAL2, RST, EA,
ALE/PROG and PSEN.
8051 allows you to manipulate one or all of the bits of a port, thus providing programmers
with a unique and powerful feature. 8051 provides the programmer with the ability to read, write
and modify each port to customize applications as much as possible.

3.1.6 INPUT/OUTPUT PORTS:
All 8051 microcontrollers have 4 I/O ports each comprising 8 bits which can be configured
as inputs or outputs. Accordingly, in total of 32 input/output pins enabling the microcontroller to be
connected to peripheral devices are available for use.
Pin configuration, i.e. whether it is to be configured as an input (1) or an output (0), depends
on its logic state. In order to configure a microcontroller pin as an input, it is necessary to apply a
logic zero (0) to appropriate I/O port bit. In this case, voltage level on appropriate pin will be 0.
Similarly, in order to configure a microcontroller pin as an input, it is necessary to apply a

logic one (1) to appropriate port. In this case, voltage level on appropriate pin will be 5V (as is the
case with any TTL input). This may seem confusing but don't loose your patience. It all becomes
clear after studying simple electronic circuits connected to an I/O pin.


INPUT/OUTPUT PIN
Figure above illustrates a simplified schematic of all circuits within the microcontroller connected
to one of its pins. It refers to all the pins except those of the P0 port which do not have pull-up
resistors built-in.
OUTPUT PIN
A logic zero (0) is applied to a bit of the P register. The output FE transistor is turned on, thus
connecting the appropriate pin to ground.

INPUT PIN
A logic one (1) is applied to a bit of the P register. The output FE transistor is turned off and
the appropriate pin remains connected to the power supply voltage over a pull-up resistor of high
resistance.
Port 0
The P0 port is characterized by two functions. If external memory is used then the lower
address byte (addresses A0-A7) is applied on it. Otherwise, all bits of this port are configured as
inputs/outputs.
The other function is expressed when it is configured as an output. Unlike other ports consisting of
pins with built-in pull-up resistor connected by its end to 5 V power supply, pins of this port have
this resistor left out. This apparently small difference has its consequences:
If any pin of this port is configured as an input then it acts as if it “floats”. Such an input has
unlimited input resistance and indetermined potential.

When the pin is configured as an output, it acts as an “open drain”. By applying logic 0 to a port bit,
the appropriate pin will be connected to ground (0V). By applying logic 1, the external output will
keep on “floating”. In order to apply logic 1 (5V) on this output pin, it is necessary to built in an
external pull-up resistor.
Port 1
P1 is a true I/O port, because it doesn't have any alternative functions as is the case with P0,
but can be configured as general I/O only. It has a pull-up resistor built-in and is completely
compatible with TTL circuits.
Port 2
P2 acts similarly to P0 when external memory is used. Pins of this port occupy addresses
intended for external memory chip. This time it is about the higher address byte with addresses A8-
A15. When no memory is added, this port can be used as a general input/output port showing
features similar to P1.
Port 3
All port pins can be used as general I/O, but they also have an alternative function. In order
to use these alternative functions, a logic one (1) must be applied to appropriate bit of the P3
register. In terms of hardware, this port is similar to P0, with the difference that its pins have a pull-
up resistor built-in.
PINS CURRENT LIMITATIONS

When configured as outputs (logic zero (0)), single port pins can receive a current of 10mA.
If all 8 bits of a port are active, a total current must be limited to 15mA (port P0: 26mA). If all ports
(32 bits) are active, total maximum current must be limited to 71mA. When these pins are
configured as inputs (logic 1), built-in pull-up resistors provide very weak current, but strong
enough to activate up to 4 TTL inputs of LS series.
3.1.6 MEMORY ORGANIZATION
The 8051 has two types of memory and these are Program Memory and Data Memory.
Program Memory (ROM) is used to permanently save the program being executed, while Data
Memory (RAM) is used for temporarily storing data and intermediate results created and used
during the operation of the microcontroller. Depending on the model in use most a few Kb of ROM
and 128 or 256 bytes of RAM is used.
All 8051 microcontrollers have a 16-bit addressing bus and are capable of addressing 64 kb
memory. It is neither a mistake nor a big ambition of engineers who were working on basic core
development. It is a matter of smart memory organization which makes these microcontrollers a
real “programmers’ goody“.
3.1.7 PROGRAM MEMORY
The first models of the 8051 microcontroller family did not have internal program memory.
It was added as an external separate chip. These models are recognizable by their label beginning
with 803 (for example 8031 or 8032). All later models have a few Kbyte ROM embedded. Even
though such an amount of memory is sufficient for writing most of the programs, there are
situations when it is necessary to use additional memory as well. A typical example is so called
lookup tables. They are used in cases when equations describing some processes are too
complicated or when there is no time or solving them.

E
A=0 In this case, the microcontroller completely ignores internal program memory and executes
only the program stored in external memory.
EA=1 In this case, the microcontroller executes first the program from built-in ROM, then the
program stored in external memory.
In both cases, P0 and P2 are not available for use since being used for data and address
transmission. Besides, the ALE and PSEN pins are also used.
3.1.8 DATA MEMORY
As already mentioned, Data Memory is used for temporarily storing data and intermediate results
created and used during the operation of the microcontroller. Besides, RAM memory built in the
8051 family includes many registers such as hardware counters and timers, input/output ports, serial
data buffers etc. The previous models had 256 RAM locations, while for the later models this
number was incremented by additional 128 registers. However, the first 256 memory locations

(addresses 0-FFh) are the heart of memory common to all the models belonging to the 8051 family.
Locations available to the user occupy memory space with addresses 0-7Fh, i.e. first 128 registers.
This part of RAM is divided in several blocks.
The first block consists of 4 banks each including 8 registers denoted by R0-R7. Prior to accessing
any of these registers, it is necessary to select the bank containing it. The next memory block
(address 20h-2Fh) is bit- addressable, which means that each bit has its own address (0-7Fh). Since
there are 16 such registers, this block contains in total of 128 bits with separate addresses (address
of bit 0 of the 20h byte is 0, while address of bit 7 of the 2Fh byte is 7Fh). The third group of
registers occupy addresses 2Fh-7Fh, i.e. 80 locations, and does not have any special functions or
features.
3.1.9 ADDITIONAL RAM
In order to satisfy the programmers’ constant hunger for Data Memory, the manufacturers decided
to embed an additional memory block of 128 locations into the latest versions of the 8051
microcontrollers. However, it’s not as simple as it seems to be… The problem is that electronics
performing addressing has 1 byte (8 bits) on disposal and is capable of reaching only the first 256
locations, therefore. In order to keep already existing 8-bit architecture and compatibility with other
existing models a small trick was done.
What does it mean? It means that additional memory block shares the same addresses with locations
intended for the SFRs (80h- FFh). In order to differentiate between these two physically separated
memory spaces, different ways of addressing are used. The SFRs memory locations are accessed by
direct addressing, while additional RAM memory locations are accessed by indirect addressing.
3.2INTERRUPT PRIORITIES
It is not possible to forseen when an interrupt request will arrive. If several interrupts are enabled, it
may happen that while one of them is in progress, another one is requested. In order that the
microcontroller knows whether to continue operation or meet a new interrupt request, there is a
priority list instructing it what to do.
The priority list offers 3 levels of interrupt priority:

1. Reset! The absolute master. When a reset request arrives, everything is stopped and the
microcontroller restarts.
2. Interrupt priority 1 can be disabled by Reset only.
3. Interrupt priority 0 can be disabled by both Reset and interrupt priority 1.
The IP Register (Interrupt Priority Register) specifies which one of existing interrupt sources have
higher and which one has lower priority. Interrupt priority is usually specified at the beginning of
the program. According to that, there are several possibilities:
• If an interrupt of higher priority arrives while an interrupt is in progress, it will be

immediately stopped and the higher priority interrupt will be executed first.
• If two interrupt requests, at different priority levels, arrive at the same time then the higher
priority interrupt is serviced first.
• If the both interrupt requests, at the same priority level, occur one after another, the one
which came later has to wait until routine being in progress ends.
• If two interrupt requests of equal priority arrive at the same time then the interrupt to be
serviced is selected according to the following priority list:
1. External interrupt INT0
2. Timer 0 interrupt
3. External Interrupt INT1
4. Timer 1 interrupt
5. Serial Communication Interrupt
3.3IP REGISTER(Interrupt Priority)
The IP register bits specify the priority level of each interrupt (high or low priority).
• PS - Serial Port Interrupt priority bit

○ Priority 0
○ Priority 1
• PT1 - Timer 1 interrupt priority
○ Priority 0
○ Priority 1
• PX1 - External Interrupt INT1 priority
○ Priority 0
○ Priority 1
• PT0 - Timer 0 Interrupt Priority
○ Priority 0
○ Priority 1
• PX0 - External Interrupt INT0 Priority
○ Priority 0
○ Priority 1
\3.5 APR9600 Single-Chip Voice Recording & Playback Device:
The APR9600 devi ce offers true single-chip voice recording, non-volatile storage, and
playback capability for 40 to 60 sec-onds. The device supports both random and sequential access
of multiple messages. Sample rates are user-select-siable, allowing designers to customize their
design for unique quality and storage time needs. Integrated output amplifier, microphone amplifier,
and AGC circuits greatly mplify sys-tem design. the device is ideal for use in portable voice
recorders, toys, and many other consumer and industrial applications.
APLUS integrated achieves these high levels of storage capa-bility by using its proprietary
analog/multilevel storage tech-nology implemented in an advanced Flash non-volatile memory
process, where each memory cell can store 256 volt-age levels. This technology enables the
APR9600 device to reproduce voice signals in their natural form. It eliminates the need for
encoding and compression, which often introduce distortion.
Features
• Single-chip, high-quality voice recording & playback solution

• No external ICs required

• Minimum external components
• Non-volatile Flash memory technology
• No battery backup required
• User-Selectable messaging options
• Random access of multiple fixed-duration messages
• Sequential access of multiple variable-duration messages
• User-friendly, easy-to-use operation
• Programming & development systems not required
• Level-activated recording & edge-activated play back switches
• Low power consumption
• Operating current: 25 mA typical
• Standby current: 1A typical
• Automatic power-down
• Chip Enable pin for simple message expansion
CHAPTER 5
APPLICATIONS
• Used in heavy traffic areas by the blind people.

• Effective detection of change in signal colours by the blind.
• Used in providing directions(left, right, etc)
• Used in research and development.
• Can be implemented in small devices that are used to support blind people.
CHAPTER 6
FUTURE ENHANCEMENT

This device can be further used in various simple objects carried by the blind people .This device
can be further enhanced to detect obstacles in all areas. This device can be used in R&D to further
enhance the device. With the available time and the facilities provided we could complete the
project as suggested by the guide. We have done the project for traffic and obstacle but the same
can also be done for other facilities like identification of the objects at home or the work place ,
which can increase the confidence and can be more user friendly. We have used the ARM7 . The
ARM Cortex M3 is the latest and can have many features built into them for more applications to
be developed.
CHAPTER 7
CONCLUSION

We live in era of rapid change moving towards the society of machines that has the information and
knowledge. We require seamless, easy to use, high quality machines anywhere and anytime. The
design of individual device has been long cherished desired to help the blind people to walk in
traffic areas.
BIBLIOGRAPHY
[1] Ager, D. V., 1981, The Nature of the Stratigraphic Record [2nd ed.]: London, Macmillan Press, 122
p.

[2] Albritton, C. C., 1963, The Fabric of Geology: Reading, Mass., Addison-Wesley Publishing Co.,
372 p.
[3]Borradale, L. A. et al., 1961, The Invertebrata: Cambridge, Cambridge University Press.
[4] Dowben, R. M., 1971, Cell Biology: New York, Harper & Row.
[5] Drake, E. T., 1968, Evolution and environment: New Haven, Connecticut, Yale University Press,
478 p
[6] Hunt, J. M., 1979, Petroleum Geochemistry and Geology: San Francisco, W.H. Freeman & Co.,
617 p.
[7.]Jacobs, J. A., 1963, The Earth's Core and Geomagnetism: New York, Pergamon Press, the
Macmillan Company, 137 p.
[8] Lyell, C., 1853, Principles of Geology: Boston, Little, Brown.
[9] MacMahon, T. A., 1984, Muscles, Reflexes and Locomotion: Princeton, Princeton University
Press.
[10] Mader, S. S., 1976, Inquiry into Life: Dubuque, Iowa, Wm. C. Brown Co.
[11] Strickberger, M. W., 1990, Evolution: Boston, Mass., Jones and Bartlett Publishers, Inc., 575 p.
[12] Tarling, D. H., and Tarling, M. P., 1977, Continental Drift: A Study of the Earth's Moving Surface
[2nd ed.]: London, Bell.








Report 1111

Hochgeladen von

Dokumentinformationen

Originalbeschreibung:

Copyright

Verfügbare Formate

Dieses Dokument teilen

Dokument teilen oder einbetten

Freigabeoptionen

Stufen Sie dieses Dokument als nützlich ein?

Sind diese Inhalte unangemessen?

Copyright:

Verfügbare Formate

Report 1111

Hochgeladen von

Copyright:

Verfügbare Formate

Intelligent device for blinds in traffic areas

DEPT OF ECE,RYMEC Page 1

DEPT OF ECE,RYMEC Page 2

RF Rx DECODE MICROCONTROL DRIVER

LEFT SPEECH SPEAK

Fig 2.1:depicting the hardware arrangement in model

2.2 ARM MICROCONTROLLER

DEPT OF ECE,RYMEC Page 3

2.2.1Basic Characteristics of ARM7TDMI

DEPT OF ECE,RYMEC Page 4

ARM7TDMI BLOCK DIAGRAM

DEPT OF ECE,RYMEC Page 5

Scan Chain 2 Scan Chain 0

DEPT OF ECE,RYMEC Page 6

TCK TMS nTRST TDI TDO TAPSM[3:0] IR[3:0] SCREG[3:0]

Fig 2.1.1 block diagram of ARM7TDMI

2.2.2ARM7TDMI Processor core

2.2.3 The THUMB Concept

2.2.4Processor Operating States

DEPT OF ECE,RYMEC Page 7

Entering ARM state

2.1.5 Memory Formats

Big Endian format

Higher Address 31 24 23 16 15 8 7 0 Word Address

Little Endian format

DEPT OF ECE,RYMEC Page 8

Higher Address 31 24 23 16 15 8 7 0 Word Address

2.1.6 ARM7 INTERNALS core block diagram

DEPT OF ECE,RYMEC Page 9

• ARM core modes of operation:

2.1.7 ARM7 register set

The condition code flags

The control bits

DEPT OF ECE,RYMEC Page 11

• Thumb-instruction decoder is placed

Example of instruction conversion

DEPT OF ECE,RYMEC Page 12

instruction ADD Rd,Rn,#constant

DEPT OF ECE,RYMEC Page 13

2.2Wireless Transmitter Module - TX1 - 433.92MHZ

external components and no tuning

 4 Pin Compact size module

DEPT OF ECE,RYMEC Page 14

PARAMETER MINIMUM TYPICAL RANGE UNITS

2.3Wireless Receiver Module - RX1- 433.92 MHZ

DEPT OF ECE,RYMEC Page 15

DEPT OF ECE,RYMEC Page 16

RX1 SR +5V DC 300~5K - 106 dbm 3.23 mA (5V) AM 1 MHZ

2.3.3 Noise Immunization

DEPT OF ECE,RYMEC Page 17

Based on above analysis, the following actions have to be taken:

Symbol Parameter Conditions Min. Typ. Max. Unit

Vcc Operating Supply Voltage MIN3.5 MAX5.5 5 6

I Tot Operating Supply voltage 4.5 -

1 Data=+200µA(High) Vcc -0.5 Vcc V

2.3.5 Electrical Characteristics:

Characteristics Sym. Min. Typ. Max. Unit

Operating Radio Frequency FC 300 - 434 Mhz

DEPT OF ECE,RYMEC Page 18

Sensitivity Pref - 119 dB

Channel Width - 500 +500 Khz

Noise Equivalent BW NEB 5 4 Khz

Baseboard Data Rate 3 Kb/s