Advanced MOSFET physics Scaling and its impact on the off-state

Reading: Chapter 5

EE231 – Vivek Subramanian Slide 3-1 EE231 – Vivek Subramanian Slide 3-2

MOS Scaling Reasons for Scaling

• Over the years, MOS devices have scaled in size • Speed, Speed, Speed!
1970’s ~ 10um – ID ↑ as L ↓ (decreased effective “R”)
– Today: ~0.12um – Gate area ↓ as L ↓ (decreased effective “C”)
• Reasons – Therefore, ↓ RC product (implies faster switch)
– Speed
– Density

EE231 – Vivek Subramanian Slide 3-3 EE231 – Vivek Subramanian Slide 3-4

1
 Scaling Theory Questions
• Constant Field Scaling: • For various reasons, voltage scaling lagged behind L
Parameter Scaling scaling for many years
Tox, L, W, xj 1/K
– Why?
• Parameter Dependence: Nsub K
VT ∝ tox N sub V 1/K – What were the consequences of this on:
• Power
1 Capacitance 1/K
gm ∝ Gate Delay CV/I 1/K • Reliability
tox
Power CV2/delay 1/K2
WL • Speed
Cox ∝
tox
Problems: This ignored parasitic • In modern devices, IDsat has essentially saturated – yet, we
Cmiller ∝ x j resistance, etc. continue to scale. Why?
EE231 – Vivek Subramanian Slide 3-5 EE231 – Vivek Subramanian Slide 3-6

The Short Channel Effect – Yau’s model Yau’s Model

QB
A D Vt = V fb + 2ϕ B +
n+ rj n+ COx
Xdep=Xdmax
B C Depletion qN sub AABCD W
region = V fb + 2ϕ B +
C ox LW

Xdmax
• Charge conservation requires:
QM + Qox + QS + QB = 0  2 X d max 
qN sub X d max rj  1 + − 1
• In a short channel device, not all field lines terminate in gate, so  r 
∆Vt ≡ Vt (L = ∞ ) − Vt (L ) =  j 
some balancing comes from S/D electrodes COx L
L + L′  2W  rj If we do not assume equal S/D depletion widths, we can extend the model:
= 1−  1+ − 1
2L  r L    
  2X S 2X D
qN sub X d max r j   1 + − 1 
j
− 1 +  1 +
• Area of trapezoid is:  r   r  
 j   j
 L + L′  ∆Vt =
Area = W   2C Ox L
 2 
EE231 – Vivek Subramanian Slide 3-7 EE231 – Vivek Subramanian Slide 3-8

2
 Consequences of Yau’s model Barrier-lowering Models - Qualitative
• Yau’s model tells us that:  2X S   2X D 
qN sub X d max r j   1 + − 1 +  1 + − 1  V fb = φ MS ≈ − 0.9V log Id
 rj   rj  
  n+ n+
∆Vt =
2C Ox L at V g = VFB , barrier = Vbi ~ 0.9V
Vd
• Consequently, ∆VT can be minimized by: V gs = 0, barrier ~ 0.5V
– Using a larger L
V gs = Vt , barrier ~ 0.1V Vg
– Decreased VDS (which reduced the drain depletion region
– Increased NSUB (at least, within the range of doping we normally
use)
Long L Shorter L Even shorter L
– Decreasing tox
– Decreasing xj
• Yau’s model is overly simplistic
– Uses geometry to distribute charge, instead of actually solving
Poisson’s equation
– Assumes that the channel potential is essentially uniform Vd Vd
throughout channel. This is inaccurate in devices with L < 1 µm

EE231 – Vivek Subramanian Slide 3-9 EE231 – Vivek Subramanian Slide 3-10

Quantitative Barrier Lowering Models Quasi-2D model of DIBL

• General outline 0 L

n+ y n+
– Develop Poisson’s equation in the channel including both
vertical and lateral field components Vs(y), ϕs(y)
E(y) E(y + ∆y)

• This is complicated, and usually requires some sort of Xdmax

simplifying assumptions, due to the 2D nature of the integral • Step 1: Set up Poisson’s equation, including both lateral and vertical field
components.
– Solve for ϕS as a function of position Vg − V fb − ϕ S
X d maxWE y ( y + ∆y )ε S − X d maxWE y ( y )ε S − ∆yW ε Ox = ∆yWX d max qN sub
TOx
dE y V g − V fb − ϕ S
– Find the peak value of ϕS ε S X d max ∆y − ∆yε Ox = ∆yX d max qN sub
dy TOx
dE y ε Ox V g − V fb − ϕ S qN sub dE y d 2ϕ S
− = =−
– Use this value in the standard VT equation to find VT as a dy ε S TOx X d max εS dy dy 2
function of L and VDS

EE231 – Vivek Subramanian Slide 3-11 EE231 – Vivek Subramanian Slide 3-12

3
 Quasi-2D model of DIBL Analysis of the quasi-2D model
ϕ S ( y ) = A sinh ( y / l ) + B sinh ((L − y ) / l ) + C
• The boundary conditions are:
– ϕS(0) = Vbi, the built-in voltage across the Source/Body junction
– ϕS(L) = Vbi + VDS l≡ 3TOx X d max

• The solution to: ε Si / ε Ox

ϕs A & B are functions of Vg, Vd
d 2φ dE y qN sub ε Ox V g − V fb − ϕ S
− 2 = = +
dy dy εS ε S TOx X d max
• is: sinh ( y / l ) sinh ((L − y ) / l )
V bi

ϕ s ( y ) = VsL + (Vbi + VDS − VsL ) + (Vbi − VsL ) L L>>l, no DIBL

sinh (L / l ) sinh (L / l )
ε S TOx X d max y

l≡ = 3TOx X d max
• Where: ε Ox C Ox

n+, S
VsL = VGS − VT

n+, D
Cd<<Cox+Cdep

EE231 – Vivek Subramanian Slide 3-13 EE231 – Vivek Subramanian Slide 3-14

VT calculation
Consequences:
• We know: ϕ ( y ) = V + (V + V − V ) sinh ( y / l ) + (V − V ) sinh ((L − y ) / l )
sinh (L / l ) sinh (L / l ) ∆Vt (L, Vd ) ≡ Vt (long Channel ) − Vt (L, Vd )
s sL bi DS sL bi sL

ε S TOx X d max ∆Vt = [3(Vbi − 2ϕ B ) + Vds ]e − L / l + 2 (Vbi − 2ϕ B )(Vbi − 2ϕ B + Vds )e − L / 2l

l≡ = 3TOx X d max
ε Ox
≈ (Vds + 1V )e − L / l ≈ Vds e − L / l
• To find VT, we need to calculate the peak value of ϕS. To do this, we
find the value of ϕS for which: Large l is bad! C Ox

dϕ S Large Tox and/or Xdmax

=0
dy are bad! Small l
• Then, we can proceed to find VT: large l

2ϕ B = ϕ peak (L, V g = Vt , Vd )
log∆Vt

∆Vt (L, Vd ) ≡ Vt (long Channel ) − Vt (L, Vd )

∆Vt = [3(Vbi − 2ϕ B ) + Vds ]e − L / l + 2 (Vbi − 2ϕ B )(Vbi − 2ϕ B + Vds )e − L / 2l
≈ (Vds + 1V )e − L / l ≈ Vds e − L / l L

EE231 – Vivek Subramanian Slide 3-15 EE231 – Vivek Subramanian Slide 3-16

4
 Questions
Effect of body bias on SCE • Based on the previous analysis, can you think of justification for
superhalo-type structures
VT
VBS=2V
VBS=1V n+ • Can you provide some insight into why we are moving towards SOI
VBS=0V
p (-)
• What is the impact of polysilicon depletion on SCE and DIBL

backgate • Consider a NAND-gate. How could we implement the body contact

L
for the upper NMOS? Consider: V dd

– Density
– Static power consumption

VBS ↑⇒ X d max ↑⇒ l ↑⇒ SCE ↑ AB

EE231 – Vivek Subramanian Slide 3-17 EE231 – Vivek Subramanian Slide 3-18

Narrow width effects The Narrow Width effect

bird beak
• MOSFETs are isolated from each other using LOCOS isolation (older n+ VT

technologies) or shallow trench isolation (newer technologies)

Oxide
n+
w p+ W
bird beak

Oxide
Si
The Reverse narrow width effect
Oxide w
VT log Id
w p+ shallow trench

• Consequences: isolation(STI)
– Due to 2D oxidation effects, the gate oxide is often thicker near the
Oxide
Si
edges of the device width w W
1 pA Vg
– In STI devices in particular, fringing fields or oxide thinning near shallow trench 0.4 V 0.7 V
the edges can sometimes make the effective oxide thickness isolation(STI)
smaller near the edges of the device width
Can model this as a very narrow parallel MOSFET with a reduced VT

EE231 – Vivek Subramanian Slide 3-19 EE231 – Vivek Subramanian Slide 3-20

5
 Reverse Short Channel Effect Reverse Short Channel Effect
• We often use pocket implants to suppress punchthrough. • Result:
VT reverse
S D

n+ n+
Large-angle titled ion implantation(LATI)
p normal
p+ p+
pocket implant L

• Consequence: Net increase in NA as L decreases • Questions:

• Think about the benefits with respect to process-induced variation
S S D
D
• Impact on junction capacitance
n+ n+ n+ n+ • Impact on junction leakage
p
p+
p
p+
• Impact on junction breakdown
p+ p+
pocket implant

EE231 – Vivek Subramanian Slide 3-21 EE231 – Vivek Subramanian Slide 3-22

Bulk or Sub-surface Punchthrough Comparison of DIBL and sub-surface puncthrough

log I d
n+ n+ log Id

Vd bulk
surface
Vd

V g
Vg

n+ p n+
No significant change in S Significant degradation in S
p+ Substrate or well doping
engineering,specifically,
retrograde profile and
Punch through super steep retrograde (SSR).
implant

EE231 – Vivek Subramanian Slide 3-23 EE231 – Vivek Subramanian Slide 3-24

6
 Potentials in a MOSFET

On-state characteristics of scaled MOSFETs

EE231 – Vivek Subramanian Slide 3-25 EE231 – Vivek Subramanian Slide 3-26

Goal: To develop improved MOSFET I-V equations Mobility Measurement

• Clearly, accurate mobility measurements are crucial to accurate models
WµCOx
Id
Vds=50mV
to measure µ , use : I d = (Vg − Vt )Vd
L
µ is a function of Vg , N sub , VBS , TOx for Vd << Vt , eg., Vd = 50mV
WµVd
Id = Qi
V L
velocity saturation vsat Qi = COx(Vg − Vt )
µE VT
Vg
E Problem: inaccurate at Vg~Vt
series resistance and other effects
G An accurate way to determine Qi(Vg):
A
~ C gS/D
S/D dQi
C gS / D =
Cgb dVg
n+ n+

Qi = ∫ C gS / D dVg
B
Vg

EE231 – Vivek Subramanian Slide 3-27 EE231 – Vivek Subramanian Slide 3-28

7
 Mobility Dependencies Scattering Effects
• Mobility depends on doping (decreases with doping) 1
Coulombic scattering: interface charge or
µn µ Qinv
ionized impurities µ increases with Vg
(cm2/V.s)
due to screening by Qinv
− 13
900 EOx
−2
∝ EOx surface Idsat(Vg=Vdd)
NA roughness
scattering
1 1 1 1 Vg
scattering rate ∝ = + +
µ µ phon µ coul µ surface roughness
roughness leads to oxide
Coulombic scattering picture
• Mobility depends on transverse electric field (generally should thickness variation; so ϕ S ( X Ox ) fluctuates
decrease with field due to increased scattering)
µ
µ ? scattered path

Measured
Expected Mobile Carrier Screening makes µ
increase with increasing Qinv
Vg
Vg/TOx

EE231 – Vivek Subramanian Slide 3-29 EE231 – Vivek Subramanian Slide 3-30

The Universal Mobility Curve Effective Field

Qdep + Qinv / 2 Vg − Vt
µ (Vg , TOx , N sub , Vsb ) = µ (Eeff )
µeff Eeff = COxVt + COx
electrons holes εS Eeff = 2
µ0 540 185 Qinv = COx (Vg − Vt ) εS
µ0 COx (Vg + Vt )
µ eff =
1 + (Eeff / E0 ) ν
ν 1.8 1 Qdep
Vt = V fb + 2ϕ B + =
E0 in Si 0.7MV/cm 0.45MV/cm
COx 2ε S
+ + ε Ox (Vg + Vt )
Qdep + Qinv / 2 For n /NMOS or p /PMOS =
Eeff ≡ Qdep Q TOx 2ε S
εS
Eb = V fb + 2ϕ B ≈ 0, Vt ≈ dep Vg + Vt
εS COx =
Qdep + Qinv therefore Qdep = COxVt 6TOx
Et =
Et
εS µ

PMOS
n+ n+
n + /PMOS 2.3V

Eb - bottom of inversion layer

Eb + Et Qdep + Qinv / 2 V + Vt − 2.3V n + poly

= ≡ Eeff Eeff = g
2 εS 6TOx
p + poly
Vg +Vt
TOx

EE231 – Vivek Subramanian Slide 3-31 EE231 – Vivek Subramanian Slide 3-32

8
 Universal Surface Mobilities Velocity Saturation
µ eff E
V
Data Model A: v=
• Phonon Scattering Vsat
vsat
1+ E / Esat
• Coulombic Scattering v = µ eff E
~107 cm/s

Model A At E<<Esat
• Surface Roughness
Scattering At E>>Esat v = constant (= Esat µ eff )
Ey
Es at
4x104 V/cm Velocity overshoot

(Vg+Vt+0.2V)/6Tox can be
shown to be the average
vertical electric field in the
inversion layer.

EE231 – Vivek Subramanian Slide 3-33 EE231 – Vivek Subramanian Slide 3-34

Square law MOSFET Model (Including Vsat) An improved velocity saturation model
• We follow the same methodology as the square law, except, we insert
our modified v vs. E relationship • Problem
dφ
µ eff
– The previous model significantly underestimates the velocity for
I d = WQinv ( y )v( y ) = WCOx (V g − Vt − φ )
dy
dφ low and intermediate field strengths
y 1+ / E sat
0 L dy V
Data
I dφ dφ Vsat
= WCOx (V g − Vt − φ )µ eff
vsat
Id + d dI d ~107 cm/s
E sat dy dy =0⇒
dVds Model A
 Id 
I d dy = ∫ dφ WCOx (V g − Vt − φ )µ eff
L Vds
∫ − 
E sat 
 2(V g − Vt ) 
= E sat L 1 + − 1
0 0
 Vdsat
 E sat L  Ey
 Vds   V    Es at
I d  L +  = WC Ox µ eff V g − Vt − ds Vds 4x104 V/cm
 E sat   2  Vdsat < Vg − Vt
– We need a model that is more accurate over the entire region of
1 WCOx µ eff  V  In general, Vdsat ↓ as L ↓ operation
Id = Vg − Vt − ds Vds
V L  2 
1 + ds
Esat L
Correction for vsat

EE231 – Vivek Subramanian Slide 3-35 EE231 – Vivek Subramanian Slide 3-36

9
 Square law MOSFET model (including improved
Improved Velocity Saturation Model velocity saturation model)
Model B :
Better Model
v
vsat µ eff E
v= , E < Esat 2Vsat
Data 1 + E / Esat Esat =
Id µ eff
v = vsat , E > Esat Idsat
Eq. B Slope=WVsatCOx v ≤ vsat
I d ≤ WQinv vsat
E Eq. A
Esat at E = E sat

v=
µ eff Esat
= v sat V
Vg-Vt d
≤ Wvsat COx (Vg − Vt − Vds ) Eq.B
Vdsat
1 + Esat/Esat
E = Esat
µ eff E sat v = vsat at the drain end
= ⇒
2 µ eff E
vsat may be considered as a constant: v=
1 + E / Eeff
8x106 cm/s for e 2v sat
E sat = WCOx µ eff   
6x106 cm/s for h µ eff V  1 + Vds 
Id = Vg − Vt − ds  Vds Eq. A
L  2   Esat L 

EE231 – Vivek Subramanian Slide 3-37 EE231 – Vivek Subramanian Slide 3-38

MOSFET model (cont’d) MOSFET model (cont’d)

WCOx µ eff  V   
Id = Vg − Vt − ds  Vds 1 + Vds 
L  2   Esat L 
Also from equating Eq. A and Eq. B,
I d ≤ Wvsat COx (Vg − Vt − Vds )

Vdsat =
(V g − Vt )Esat L
Equating the above, we have:
WC Ox µ eff (V − Vt ) 2
Vg − Vt + Esat L
(V − V ) 2
I dsat =
2L
g
Vg − Vt
I dsat = WCOx vsat
g t
1+ Id
Vg − Vt + Esat L E sat L
Long L, ie. EsatL>>Vg-Vt
Large L, ie Esat L >> Vg − Vt Short L, ie Esat L << Vg − Vt Vdsat=Vg-Vt
WCOx µ eff 2vsat
I dsat = (Vg − Vt ) 2
E sat =
µ eff
Short L, ie. EsatL<<Vg-Vt
2L Vdsat=EsatL
(
I dsat = WCOx vsat Vg − Vt ) Vd

∝ 1/ L 5 V/µm 0.2 µm

I dsat (L → 0) V − Vt + E sat 0.25µm 2 + 3 * 0.25 2.75 1 1 1

= g = = = + average of Vg-Vt and EsatL
I dsat (L = 0.25µm ) Vg − Vt 2 2 Vdsat Vg − Vt Esat L

EE231 – Vivek Subramanian Slide 3-39 EE231 – Vivek Subramanian Slide 3-40

10
 Measured MOSFET IV Parasitic Source-Drain Resistance
contact metal dielectric spacer

G
gate
oxide
Rs Rd channel
S D

ID
N+ source or drain
CoSi2 or TiSi2

I dsat 0
• If Idsat0 ∝ Vg – Vt , I dsat =
I R
0 1 2 2.5
1 + dsat 0 s
VD(V) (Vgs − Vt )
• Idsat is reduced by about 15% in a 0.1µm MOSFET.
What are the two main differences between the
long and short channel length IV curves? • Vdsat = Vdsat0 + Idsat (Rs + Rd)

EE231 – Vivek Subramanian Slide 3-41 EE231 – Vivek Subramanian Slide 3-42

Questions Source Injection Velocity Limit

Vg s
• What is worse, parasitic resistance in the source or drain?
gate
• Which region to you expect to contribute the maximum resistance S D
V ds • Carrier velocity is limited
N+ N+
• Why not eliminate the extension?
by the thermal velocity when
contact metal dielectric spacer
the carriers first enter the
• Why not use a thicker silicide? gate -
channel from the source.
Ec
oxide
channel • Idsat = WBvthxQinv
Ev
= WBvthxCoxe(Vgs – Vt)
N+ source or drain
CoSi2 or TiSi2

EE231 – Vivek Subramanian Slide 3-43 EE231 – Vivek Subramanian Slide 3-44

11
 Channel Length Modulation Quasi-2D model of channel length modulation
• We know that channel length modulation is particularly important in • Framework
short-channel devices – We need to solve Poisson’s equation to find the actual extent of the
Vd > Vdsat Id
pinched off region. To proceed, we will consider that the only
δL=0
region of interest is the pinched off region:
δL
– Lateral dimension: ∆L
Vc ( y ) = Vdsat
Vd
Vdsa t – Vertical dimension: xJ (ASSUMPTION: The drain field only has a

I dsat =
Wµ eff COx (V g− Vt )
2 horizontal component, so we only need to worry about x < xj)
2( L − δ L ) Vg − Vt
1+
δL(Vd ) = ?? Esat (L − δL )
Xj n+

Choose x=xj y’
• We would like an equation to calculate the value of ∆L as a function of as the bottom y’ = δL

the various physical parameters and bias conditions of Gaussian box

EE231 – Vivek Subramanian Slide 3-45 EE231 – Vivek Subramanian Slide 3-46

Quasi-2D model of channel length modulation Quasi-2D model of channel length modulation
• Poisson’s Equation
• Poisson’s Equation – Based on the previous assumptions, we have:
– We have both ionized dopants and velocity-saturated mobile
carriers in the box of interest. dE y ε Ox V g − V fb − 2ϕ B − V ( y ') qN a + qN m Mobile carriers
+ =
– To simplify our analysis, we will make several assumptions about dy ' εS x j TOx εS
the vertical field (from the gate):
• We will assume that the field, Ex = 0 at x = xj. Calculated from the peak vertical field
• To remove the need for a 2D integral, we will approximate the slope
of the vertical field as constant in any vertical slice. – Now, we notice that the right hand side is just the total carriers in
the silicon. Therefore, we can rewrite the equation as:
E x (0, y )
E ( y ') = d 2V V g − V fb − 2ϕ B − V V g − V fb − 2ϕ B − Vdsat
xj Xj + = From QSi=ϕOxCox
dy ' 2 3TOx 3TOx
– Rearranging, we have: d V V − Vdsat
2

• since the field goes to zero at xj =

dy ' 2 3 X j TOx
d 2 (V − Vdsat ) V − Vdsat
= l ' ≡ 3 X j TOx
dy ' 2 l '2

EE231 – Vivek Subramanian Slide 3-47 EE231 – Vivek Subramanian Slide 3-48

12
 Quasi-2D model of channel length modulation Quasi-2D model of channel length modulation
• Solution: • Solution:
– we have: d 2 (V − Vdsat ) V − Vdsat – We know: y'
= l ≡ 3 X j TOx
'
V ( y ') = Vdsat + E sat l ' sinh
dy ' 2 l '2 l'
– The general solution to this equation is: – Therefore, we can proceed to calculate ∆L:
y' y' δL
V ( y ') − Vdsat = A sinh + B cosh V ( y ' = δL ) = Vd = Vdsat + E sat l ' sinh
l' l' l'
– Now, we know that the voltage at the edge of the pinch-off region  V − Vdsat 
δL = l ' sinh −1  d 
(y’=0) is Vdsat, and the field is Esat:  E sat l ' 
V ( y ' = 0) = Vdsat ⇒ B = 0
dV A y' A
E ( y ') = −
= cosh ⇒ E ( y ' = 0) = E sat = ⇒ A = E sat l '
dy ' l ' l' l'
– Therefore, the solution is:
y'
V ( y ') = Vdsat + E sat l ' sinh
l'
EE231 – Vivek Subramanian Slide 3-49 EE231 – Vivek Subramanian Slide 3-50

Output resistance MOSFET Device Design

• As a consequence of channel length modulation, the small-signal • Goals:
output resistance takes on a finite value
– Maximize IDsat
Id L Vd − Vdsat – Minimize Ioff
R0 ≈ – Minimize SCE, Punchthrough, etc
l ' I dsat
• Choices
Vd
– Tox: minimize (but watch for dielectric breakdown!!!)
– xJ: minimize (but watch for series resistance and silicide junction
• In addition, DIBL also constrains R0. In the DIBL limited regime, R0
leakage)
is independent of VDS DIBL
Rout – Body doping:
1 ∂I ∂I ∂VT CLM
• Adjust shallow to control VT and DIBL
= G0 = D = D
R0 ∂VD ∂VT ∂V D • Adjust deep to control VT, γ, and punchthrough
– Gate workfunction:
∆Vt ∝ (Vd + ...)e − L / l ' • Adjust VT (watch for series resistance, process complexity, poly-poly
Vdsat
Vd diodes, etc.)

EE231 – Vivek Subramanian Slide 3-51 EE231 – Vivek Subramanian Slide 3-52

13
 Scaled CMOS Issues Scaled CMOS Issues
• Goals: • Single Poly Processes
– Low VT to maximize speed – N+ Poly: Was used in >0.5µm processes (simple, well-understood).
– Ideally, symmetric devices for simplicity Results in a buried channel PMOS device (poor scalability)
• Technology Issues: – P+ Poly: Not very widely used, though it was extensively used in early
– Wells are usually doped to at least 1E16 cm-3 PMOS chips
– Choice between single poly doping and dual poly doping • Dual Poly Processes
• NMOS Implications – More complex, but allows production of surface channel NMOS and
– Easy to get VT < 0.5V by Boron doping and N+ Poly PMOS.
• PMOS Implications
– Difficult to get |VT| < 0.5V with N+ Poly
• Choices
– Use P+ Poly throughout (High resistance, need to overcompensate
NMOS, which reduced NMOS perfornace)
– Use dual poly doping (Assymetric gate resistance, P+/N+ poly diode at
invertor gate)

EE231 – Vivek Subramanian Slide 3-53 EE231 – Vivek Subramanian Slide 3-54

Comparison of Surface / Buried Channel PMOS

PMOS Transistors µp
• Advantages of buried channel n+ poly
2.4V
1 Q – Single poly process (buried-channel)
µ p ~ µn Vt = φ MS + 2ϕ B + B
3 C Ox – Higher mobility
p+ poly
≈0 • Disadvantages of buried channel (surface-channel)
Vg
– Worse short-channel effects
p + poly gate (dual poly process) n+ poly/PMOS n+ poly/NMOS
PMOS
n + poly gate p+ p p+ n+ n+
Vt
Xdep NMOS
Xdep
n+ poly/NMOS and p + poly/PMOS make a close twin n
PMOS(buried-channel)
p-sub
Vg=Vdd
Vg=0
n+ poly/PMOS (lightly doped sub) has Vt= -1.2 V. n+ gate sub
L
Na-
Nd+
Solution: Implant Boron to form thin P-layer at surface. This reduces |VT|, but Ef
pushes potential minimum below surface, resulting in a buried channel +
Ev

EE231 – Vivek Subramanian Slide 3-55 EE231 – Vivek Subramanian Slide 3-56

14
 Latchup Vdd Questions
Vin
I

V0 Vdd • Compare expected latchup performance in STI and LOCOS

p+
I1 PNP isolated structures
n+ n+ p+ p+ n+
PNP
NPN :
NPN n-well I2
I1 = α NPN I + I l '
NPN
p-sub
• How does a guard-ring work to improve latchup performance?
PNP :
p+
I
I 2 = α PNP I + I l

I dd
I1 + I 2 = I = I (α NPN + α PNP ) + I l + I l ' • Discuss the use of deep implant damage as a means of
controlling latchup.
Il + Il '
I=
holding current 1 − (α NPN + α PNP )
holding voltage
V dd latchup : α NPN + α PNP ≥ 1

EE231 – Vivek Subramanian Slide 3-57 EE231 – Vivek Subramanian Slide 3-58

15