ASC ’98, PREPRINT, September 13, 1998
Timing Jitter and Bit Errors in a 64-Bit Circular
Shift Register
Andrea M. Herr
Department of Physics and Astronomy, University of Rochester, Rochester, New York 14627
Marc J. Feldman and Mark F. Bocko
Department of Electrical and Computer Engineering, University of Rochester, Rochester, New York 14627
Abstract — The bit-error rate of a 64-bit single-flux-quantum
circular shift register, operating at a clock frequency of 10-16 GHz
was measured. Error incidence depends on the values of the clock
and data bias currents and on the clock frequency. Timing viola-
tion arising from thermal jitter is the dominant error mechanism.
The jitter per JTL stage is estimated to be 340 fs based on the error
rate data. This corresponds to a noise temperature of 10 K.
D
I. I NTRODUCTION
IGITAL ELECTRONICS based on the single flux quan-
tum (SFQ) offers an appealing alternative to conventional
transistor- based circuits. A feature of this technology is that
the clock must be delivered to each basic logic element. These
circuits typically have a regular systolic array architecture, in
which the data flow through the circuit without feedback (see,
for example, [2]). Circuits with recurrent data paths, in which
the data is required to circulate around closed loops, are subject
to more stringent timing constraints and must be carefully de-
signed with these in mind: the clock skew around a closed loop
must be zero. Timing errors in recurrent circuits are a likely
cause of circuit failure.
Perhaps the simplest recurrent rapid-single-flux-quantum
(RSFQ) circuit is the circular shift register (CSR). We have
demonstrated a 64-bit RSFQ CSR which showed correct opera-
tion to a clock frequency of 18 GHz, published in [1]. We have
also measured the bit error rate (BER) of the 64-bit CSR. BER is
defined as the probability that an error in circuit operation will
occur during a complete circulation of the data through all 64
stages of the register, as a function of frequency and bias cur-
rent. We assess the amount of thermally induced timing jitter
present in the circuit by analyzing the errors which are caused
by timing violations. These timing errors are distinct from the
functional errors previously considered in [3], [4], [5]. The shift
register cells used here follow the RSFQ timing convention as
defined in [7]. Therefore, the CSR may be considered a case
study of timing considerations in recurrent SFQ circuits.
Two types of timing errors are possible in our CSR. One oc-
curs when the data pulse follows the clock pulse too closely,
i.e. the data pulse arrives at the input of any one register cell
too early in the clock cycle, in violation of the hold time of the
cell [6]. Hold time violations can occur even during low-speed
Manuscript received September 15, 1998.
This work was supported in part by the University Research Initiative at the
University of Rochester, sponsored by the Army Research Office under Grant
No. DAAL03-92-G-0012.
1
circuit operation because once the SFQ pulses are introduced at
the circuit inputs they travel through the circuit at high speed.
The clock period does not affect the occurrence of hold time
errors since it is only the relative position of the data to the pre-
ceding clock pulse that is critical. Setup time violations, on the
other hand, occur when the clock follows the data too closely,
i.e. the data comes too late in the clock cycle. As the clock
period decreases, the likelihood of errors due to setup time vio-
lation increases. In effect, any variation in the position of either
the clock or data pulse, i.e. jitter, increases the hold and setup
time of the SFQ cell.
II. B IT-E RROR M EASUREMENT
The 64-bit CSR is comprised of eight columns of eight shift
register cells, alternately clocked in concurrent and counterflow,
as shown in Fig. 1; a schematic of the basic shift register cell
used in these experiments is shown in Fig. 7 of [8]. The overall
block clocking of the CSR is counterflow; the single exception is
the long JTL which connects the output of the first column to the
input of the last (labelled A to D in Fig. 1). There are three bias
leads which power the circuit: one each for the clock and data
paths, and another for the delay line. Adjusting these individual
dc-current biases changes the relative speed of the clock and
BIAS
DATA
IN CB JTL
A B C D
8 STAGES CONCURRENT
8 STAGES COUNTERFLOW
8 STAGES CONCURRENT
8 STAGES COUNTERFLOW
8 STAGES CONCURRENT
8 STAGES COUNTERFLOW
8 STAGES CONCURRENT
8 STAGES COUNTERFLOW
S
S S S S S S S
DATA OUT
CLOCK IN
Fig. 1. Block diagram of the 64-bit circular shift register. Notation:
CB–confluence buffer, S–splitter.
ASC ’98, PREPRINT, September 13, 1998 2

0
data pulses traveling through the register, making errors more or 10
less likely to occur. The error rate is expected to be a function f = 10.6 GHz
f = 13.4 GHz
of both the clock frequency and these externally supplied dc- f = 15.8 GHz

error rate (per 64 clock cycles)

currents. A more detailed description of the circuit architecture
may be found in [1].
The circuit was fabricated using the standard 1 kA/cm2
−5
10

HYPRES Niobium process [9]. The chip was mounted in a

dip-stick probe and submersed in liquid helium. Two -metal
shields and a Pb shield provided magnetic shielding.
To perform the error rate experiment, the three bias currents −10
10
were first set to values which maximized the circuit margins
for high-speed (15.8 GHz) operation: 30.5 mA for the clock,
25.0 mA for the data, and 3.5 mA for the delay line. These val-
ues define the nominal operating point of the circuit. The cur-
rent supplied to the delay line was held constant throughout the 10
−15

entire error-rate experiment. The clock and data bias currents 29 29.5 30 30.5 31 31.5
clock bias current (mA)
were individually varied to induce errors in circuit operation;
one of these two currents, the test bias, was changed while the Fig. 2. Measured (points) and best-fit error function dependence of
other was held constant at its nominal value. In this way, we BER on clock bias current. The three sets of data correspond to dif-
were able to isolate errors caused by the test current. Systematic ferent clock frequencies. The dashed line represents the nominal bias
adjustment of the supplied bias currents permitted errors to be point.
detected in each of four regimes: high and low clock bias, and
high and low data bias. 10
0

We could not verify the integrity of the data sequence after f = 10.6 GHz
each individual high-speed circulation, since it was not possible f = 13.4 GHz
f = 15.8 GHz
error rate (per 64 clock cycles)

to apply a fixed number of high-speed clock pulses to the regis-

ter input using our on-chip Josephson ring oscillator. Instead, we
−5
applied the multi-GHz clock signal for a relatively long time in- 10
terval before halting the high-speed operation in order to check
the data sequence for errors, as described in [1]. We were able
to determine only whether the data had survived all of the circu-
lations intact.
−10
The circulation time was varied between 190 ms and 10

60000 ms. One hundred experimental trials were performed for

each combination of bias condition and circulation time. The
circulation time was increased from the minimum to the maxi-
mum value, and then subsequently decreased until the minimum −15
value was again reached. Data were taken twice for all but the 10
22 23 24 25 26 27
longest circulation times; the reproducibility of the results was data bias current (mA)
thus confirmed. After each of the 100 individual experiments,
Fig. 3. Measured (points) and best-fit error function dependence of
the integrity of the data output was verified. If the data sequence BER on data bias current. The three sets of data correspond to different
contained errors, the CSR was said to have “failed.” The num- clock frequencies.
ber of observed circuit failures was counted for each set of 100
trials; hence the number of failures ranged from zero to 100. For
those trials which were repeated, the error counts from the two through n circulations is given by
sets of 100 trials were summed.
Automated data acquisition permitted the continuous collec- F = 1 , pn : (1)
tion of experimental data. It took nearly eight hours to obtain the
error counts for each bias point when the circulation time was The quantity F was measured directly in the experiment and is
varied over its full range. Hence, the entire experiment lasted given by
three weeks. The circuit worked continuously over this time pe- F = Nf =T (2)
riod. where Nf is the number of circuit failures observed during T
The BER of the circuit can be derived from the experimental experimental trials for a given combination of test bias and data
data. Let p = 1 , f be the probability that the integrity of the circulation time. It follows that
data is maintained during a single circulation through the entire
64-bit CSR (64 clock cycles). The BER of the circuit is the
1
f = , ln (1 , Nf =T ) (3)
probability, f , that the data sequence does not remain intact. The n
probability that the correct data sequence was not maintained for f  1.
ASC ’98, PREPRINT, September 13, 1998
Figs. 2 and 3 show the error rate of the 64-bit CSR as a func-
tion of the test bias current. The error rate of the CSR is fre-
quency independent in the high data bias and high clock bias
regimes. However, there is a fundamental difference between
the error rate curves in these two regimes. In the case of high
data bias, the error rate rises as the data bias is increased from
the nominal operating value. This indicates that the error is ei-
ther due to a hold time violation or a functional error induced in
one of the circuit components. In the high clock bias regime, the
error rate shows no dependence on the magnitude of the supplied
dc-current; the error rate is essentially constant. This indicates
that the error mechanism does not involve timing. We attribute
these errors to junction over-bias.
The error rate is both frequency and current bias dependent
as the data bias is decreased from its nominal value. This is
the unambiguous signature of a setup time violation. Circuit
simulations support this conclusion and indicate the error occurs
at point D in Fig. 1. Lowering the data bias current decreases the
speed of the data pulses traveling through the circuit, causing
them to come later in the clock cycle than they would at the
nominal operating point. The data arrives at the input of the first
counterflow register at point D progressively later in the clock
cycle until it arrives too close to the following clock pulse and a
setup time violation results. This timing violation was observed
to affect the data sequence in the same way each time; the last
“1” in a series of eight “1’s” was delayed by one clock cycle.
Finally, in the low clock bias regime, the error rate shows
two types of functional dependence. All three error-rate curves
are clearly dependent on the magnitude of the current; however,
we notice that the error-rate curves show no frequency depen-
dence until the clock rate reaches some threshold value (between
13 GHz and 15 GHz). This suggests that there are two distinct
error mechanisms involved. At frequencies below the thresh-
old, the error can be attributed to either a hold-time violation or
a functional error in one of the circuit elements; the signature
of hold time violation is that the first “1” in the series of eight
“1’s” advanced by one clock cycle. However, as the frequency
is increased, the likelihood of a setup time violation somewhere
within the circuit increases.
III. E FFECTIVE T EMPERATURE
Occasional circuit errors are caused by noise current arising
from thermal fluctuations in the shunt and bias resistors or in-
troduced from external sources. In the following, we will con-
sider only the effects of Johnson (thermal) noise in the resistors.
The amplitude of the noise current is Gaussian distributed with
standard deviation  equal to the root-mean-square noise current
produced by a resistance R at an absolute temperature T :
r
=
4kB T B (4)
R A to D. The value of R results from the parallel combination of
where kB is the Boltzmann constant and B is the bandwidth
of the measuring instrument. In our case, the instrument is the
, as fabricated.
Josephson junction itself, which is capable of responding to fre-
quencies from dc to the plasma frequency, fp . For the 1 kA/cm2
junctions used, fp  137 GHz. The total noise current from
multiple independent sources is the square root of the sum of
the squares of the individual noise currents; the noise currents
3
add in quadrature. In the case of the CSR, the resistance R is
the parallel combination of all of the resistors contributing to
the noise along the critical path.
An error in circuit operation will occur if the amount of noise,
In , is large enough to cause the operating margins to be ex-
ceeded when the circuit is biased with current Ib . That is, an
error will occur if the magnitude of the noise current exceeds
some threshold value, It = jIm , Ib j, where Im is the value
of bias current such that in the presence of noise, the error rate
of the circuit is 50%; Im is the current margin. It is important
to note that the value Im does not correspond to the high-speed
operating margins of the CSR quoted in [1]. In that case, two
trials were performed in which the data were made to circulate
through all 64-stages of the register for 200 ms. This corre-
sponds to more than 30 million circulations at 10 GHz. If the
data survived all of these trials intact, then the circuit was said
to have “passed.” The quoted margin is the value of bias current
for which this requirement was fulfilled; this corresponds to an
error rate of much less than 50%. Assuming that an error oc-
curred during only one of the 30 million circulations, the error
rate is approximately 3  10,8 .
If we integrate the Gaussian probability density outward from
the threshold current, It , to infinity, we obtain the probability
that the noise current will exceed the threshold value, and con-
sequently, the probability that the circuit will fail during any one
circulation of the data. Hence, we obtain
"r #
1 R
8kB T B jIb , Im j
BER = erfc
2 (5)
where erfc is the complementary error function.
This theoretical function was fit to the experimental error-rate
curves for low clock bias and low data bias currents, for which
the error mechanism is known to involve timing violations at
point D in Fig. 1. Jitter in the position of the clock pulse as it
arrives at points A and D, and jitter in the path the data travels
between points A and D both contribute; it is the relative timing
of clock and data which is important. Note that at each counter-
flow register stage along the first column of the CSR, the data
is synchronized with the clock, i.e. the data is always released
when the clock arrives at the input of the register cell. Since the
data pulse always reaches the input of the subsequent concurrent
cell well in advance of the next clock pulse, small variations in
the time of arrival of the data pulse at the input of any of the
concurrent registers in the first column do not affect the time at
which the data pulse reaches point D. Hence, the jitter which
causes the timing errors at point D is attributed to current noise
produced by the resistors in the clock path up the first and last
columns of registers, the clock splitter network between the two
columns, and the data path formed by the long connection from
the shunt and bias resistors along this critical path which yields
a value of 0.0112
The value of Ib used to fit the curves is the amount of test
current applied to the critical path. In the case of low data bias,
this is the amount of bias current supplied to the JTLs on the
output of the first column and the arm of the confluence buffer
traversed by the data pulse, about 9:4% of the total data bias
ASC ’98, PREPRINT, September 13, 1998
current. For the case of low clock bias, the relevant bias current
is that supplied to the clock lines of the first seven register stages
in the first and last register columns (these affect the time at
which the data is released from the last register in the column)
as well as the current supplied to the relevant arm of the splitter
network that carries the clock pulse to the clock input of the last
column. This is approximately 27:8% of the total clock bias
current.
The current bias operating margin, Im , and the absolute tem-
perature, T , were used as fitting parameters for the theoretical
error-rate function given by (5). An effective temperature of ap-
proximately 10 K gave the best overall fit to the data in these two
regimes. This is significantly higher than the physical tempera-
ture of 4.2 K. Additional noise sources may have been present,
or our simple threshold model may have underestimated the ef-
fect of thermal noise in the circuit, which includes nonlinear ele-
ments (the Josephson junction). The 10 K effective temperature
is consistent with results presented in [4] and [5].
IV. T IMING J ITTER
Entirely apart from the question of effective temperature, the
data can be used to determine the amount of timing jitter present
in the 64-bit CSR. To do so, we must quantify how changes in
the test bias current affect the relative positions of the clock and
data pulses.
In the case of low data bias current, we must determine how
the separation time between the conflicting data and clock pulses
is affected by the data bias current. To this end, numerous cir-
cuit simulations were performed and the separation time mea-
sured as a function of data bias current. Using this information,
the error-rate curves shown in Fig. 3, may be transformed so
that BER is given as a function separation time instead of bias
current.
Jitter in the circuit can be estimated again assuming a thresh-
old model; an error will occur if the jitter exceeds the timing
margins in the circuit. We assume the timing jitter is Gaussian
distributed with standard deviation t , the standard deviation of
the quadrature sum of timing jitter in both the clock and data
paths. Timing errors will occur if the jitter exceeds a threshold
tt = jt , tm j where t is the separation time between the con-
flicting clock and data pulses in the absence of noise and tm is
the separation time which results in a 50% failure rate, the “sep-
aration time margin.”
Following the procedure outlined in Section III we obtain
 
1 1
BER = erfc p jt , tm j :
2 (6)
2t
The standard deviation, t , and the timing margin, tm , were
used as fitting parameters for the theoretical error-rate function
given by (6). A standard deviation of 3.2 ps gave the best fit
4
to the experimental data for all three error-rate curves. The
JTL stages in the clock and data paths have Ic in the range
200-400 A. We estimate the shift register stage to have jitter
equivalent to that of two JTL stages. The critical path is com-
p
prised of the equivalent of 90 JTL stages. Hence, the timing
jitter per stage is approximately t = 90, or 340 fs. Note that
this is significantly larger than that reported in [10], in which jit-
ter was estimated based on linewidth measurements of an RSFQ
Josephson ring oscillator.
V. C ONCLUSION
Experiments to determine the bit-error rate of a 64-bit CSR as
a function of operating frequency and clock and data bias cur-
rents have been performed. The error-rate curves thus obtained
suggest an effective temperature of 10 K. Although this is much
higher than the bath temperature, it is in good agreement with
previously published results. In addition, we have determined a
timing jitter of 340 fs per JTL stage.
We have demonstrated that timing errors due to thermally-
induced jitter can be the dominant error mechanism in a large
SFQ circuit, eclipsing functional circuit errors. While error-rate
curves associated with functional errors have a very steep slope
as a function of current bias and extrapolate to near negligible
values [4], those associated with jitter-induced timing errors in
the CSR have a more gradual slope. On the other hand, tim-
ing errors always may be avoided with sufficiently conservative
design; this comes at the expense of operating frequency. It is
important to consider the effects of timing jitter when design-
ing a large SFQ circuit and to design conservatively in order to
attain an acceptable bit-error rate.
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[1] A. M. Herr, C. A. Mancini, N. Vukovic, M. F. Bocko, and M. J. Feld-
man, “High-speed operation of a 64-bit circular shift register,” IEEE Trans.
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