A FAST MULTIPLIER DESIGN USING SIGNED-DIGIT NUMBERS AND 3-VALUED LOGIC

I-Shi E. Chen and T. N. Rajashekhara

Department of Electrical Engineering
State University of Nev York at Binghamton
Binghamton, NY 13902-6000

A bs t rdc t

A multiplier design using 3-valued (ternary) logic and in the digit set {-l,O,l} of RBSD requires only one
redundant binary signed-digit (RBSD) numbers is ternary bit. Rajashekhara and Chen 161 have presented
presented in this paper. The use of 3-valued logic a scheme for RBSD addition using ternary logic. In
offers the advantage of reduced circuit complexity this paper, ve present the design of a multiplier unit
both i n terms of transistor count and interconnections using the RBSD adder cells presented in 1 6 1 . In
since each ternary bit can support one digit of the section 2 , we shall discuss briefly signed-digit
RBSD number system. The choice of RBSD number system numbers and RBSD addition. In section 3, ve shall
enhances the speed of multiplication by allowing carry discuss the multiplier design using 3-valued RBSD
free addition of partial products. While the internal adders. In section 4, ve shall summarize the
multiplication uses RBSD numbers, both the input contributions of this paper.
operands and the output product are assumed to be in
the standard tvo's complement form. MAGIC and SPICE 2. RBSD Addition and T e r n a r y L o g i c
softvare tools vere used t o produce VLSI design
layouts and circuit simulation results. Each digit of a signed-digit (SDI number
representation in radix r is made up of an element
from the digit set {-a, -(a-l),..., -1, 0, , (a-l),
1. Introduction a) vhere a is chosen to be Lr/2r to yield mininurs
In many computer applications such as signal and image redundancy. An SD number vith radix 2 and digit set
processing, computer graphics, and process control, (-l,O,l) is called redundant binary signed-digit
multiplication is one of the most vital functions. The (RBSD) number. Addition of tvo RBSD numbers can be
demand placed by these applications on the speed of carried out in parallel in three steps as shown in
multiplication is motivating researchers to look for Figure 1 and described by equations (11, ( 2 1 , and (3).
alternative approaches for designing high speed An RBSD adder design using 3-valued logic is described
multipliers. Using non-conventional number system such in [ 6 1 . Ternary logic is very suitable for designing
as signed-digit numbers for designing fast arithmetic arithmetic units using RBSD number system since each
units is particularly gaining much attention in recent ternary bit can support one digit of the RBSD number.
years. Signed-digit number system offers the The truth table of ternary inverter gates used in
possibility of carry free addition by taking advantage designing RBSD adder circuit is given in Table 1.
of the redundancv associated vith this -
representation. Several papers have appeared xi+l- =i+2
in recent years exploring the use of
signed-digit numbers for designing fast Yi+l-
= "i+l
arithmetic units [l-61. Takagi et a1 [11 have r
presented a high speed multiplier design using I1 t'
redundant binary signed-digit numbers. In this i+2
paper, the partial products are added
pair-vise vhich reduces the number of - I
7
_I
additions in proportion to the logarithm of
the vord length. Booth recoding technique is yi - wi 111 .
%+l
also utilized to reduce the number of partial
products by a factor of tvo. Tvo partial
products are added in constant time, since the
partial products are represented in RBSD xi-*
I1 d-W'
i
number system. Rajashekhara and Kal I 4 1 have
presented an implementation of the same idea yi-+
vith reduced logic complexity making it
suitable for VLSI implementation. In both these
I
- W
i-1

designs RBSD numbers are represented using binary

logic vhich requires two bits per digit of RBSD Figure 1: RESD Adder Structure
number. Though these designs are able to achieve
higher speeds, the circuit complexity and the number xi + Yi = vi t 2*titl
of inter connections can be significantly reduced if a
proper choice of logic implementation compatible vith vi + ti = VIi t 2*t'i+l
the number system is made. Ternary or 3-valued logic VI. t t'i = s
blends itself vith RBSD number system since each digit i

CH28 19-1/90/0000-0881$01.OOO1991 IEEE

 Table 1
assumed to be in standard tvo's complement (TC) form
Truth t a b l e of Ternary Inverter Gates and the RBSD product is converted back to TC form thus
making the design suitable to be used as a building
Input (x) output ( i ) block in digital systems using binary number system.
STI PTI NTI Figure 2 shovs the block diagram of a 4x4 multiplier
unit. The multiplier and multiplicand operands are in
0 0 1 -1 TC form. The partial product generator (PPG) generates
1 -1 -1 -1 the partial product bits in RBSD form using bit-pair
-1 1 1 1 recoding technique. Figure 3 shovs the circuit diagram
of the PPG. This circuit is an implementation of
STI: Simple Ternary Inverter Table 2 which shovs the RBSD product bit as a function
PTI: Positive Ternary Inverter of TC multiplicand and multiplier bits. The multiplier
and multiplicand bits use binary logic with logic 0
NTI: Negative Ternary Inverter and 1 represented by voltage levels OV and 5V
respectively vhile the partial product bits use
A ternary T gate vhose function is described by ternary logic vith logic -1, 0, and 1 represented by
equation (4) is realized using PTI and NTI gates. An voltage levels OV, 2.5V, and 5V respectively. The
appropriate combination of T gates is used to realize partial product bits should yield 0, 1, -1, 2 , or -2
the RBSD adder functions described by equations (11, times the multiplicand depending on the pattern of
(21, and ( 3 ) . multiplier bits Bjtl, Bj, and Bj-l. The partial
T(y1,y2,y3: x ) = yi; i = 1 if x = -1 (4) product bits a (-a) in columns PP. . and PPjtitl
3+1
= 2 ifx=O represent 1 (-1) and 2 (-2) times the multiplicand
= 3 i f x = 1 respectively. Since the multiplier and multiplicand
are in TC form, a 1 in the most significant bit
vhere yl, y2, y3 are gate inputs, x is control input, position of the multiplier represents a negative
number and this is reflected in the partial product by
and yi is gate output. changing the sign of nonzero elements as seen in the
right tvo columns of Table 2. An example of obtaining
. RBSD Multiplier Design
3 the partial products is shovn belov:
The RBSD adder discussed above and described in I61 is B5B4B3B2B1B0 A SAqA 3A2AlA0
utilized for adding the partial products in designing Multiplier 0 1 1 0 1 1 Multiplicand 1 1 0 0 1 0
the multiplier. Bit pair recoding 171 of the
multiplier operand is employed to reduce the number of Partial product corresponding to BIBOB-l (110) is
partial products by a factor of 2. Partial products
are added in a pair-vise binary tree fashion 111 vhich 1 -1 0 0 -1 0 vhich is -1 times the mult pl icand .
reduces the number of partial product pairs to be
added in proportion to the logarithm of the word Partial product corresponding to B3B2B1 101) is
length of the multiplier operand. Since the add time
1 -1 0 0 -1 0 vhich is also -1 times the multiplicand.
is constant independent of the word length, the
multiplication time is of the order O(log2n) for an
Partial product corresponding to B5B4B3 (011) is
n-bit multiplier operand. Though the internal addition -1 1 0 0 1 0 0 vhich is 2 times the multiplicand.
is performed on RBSD numbers, the input operands are
A3 A2 AO
J J J J

PPG

RBSD
pp1 Product

RBSD ADDER
* to
TC +
4
TC
Product

.? .? .? ?
A 3 A2 A1 AO

PPG = Partial Product Generator

B B B B = Multiplier Operand, A A A A = Multiplicand Operand
3 2 1 0 3 2 1 0

Figure 2 Block Diagram of a 4x4 Multiplier

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To ensure proper positional veightages each subsequent
partial product is left shifted tvo digit positions
vith respect to the previous partial product before
the partial products are added.
It may be noted here that the complete circuit of
Figure 3 is used only for the PPG corresponding to the
HSB of the multiplicand (A3) in Figure 2. The PPG
corresponding to the next lover significant bit of the
multiplicand (AZ) consists of only part a of Figure 3
vith OV and 5V lines interchanged. All other PPGs
consist of only part b of Figure 3. The choice of only
portions of Figure 3 for partial product generation
significantly reduces the chip area for operands vith
large vord length.
The partial products are properly aligned and added
pair-vise using RBSD adder as shovn in Figure 2. For
n-bit operands, rn/21 partial products are generated
and pair-vise addition of these partial products
requires log2rn/21 levels of RBSD adders. Since
addition at each level is done in constant time
independent of operand length, the multiplication time
is of order O(10g2rn/21). Hovever, the product is
available in RBSD form. To make the design compatible
with other digital systems, it is desirable to convert
the RBSD product into TC form. The RBSD to TC
converter block shown in Figure 2 is designed using a
borrow look back ( B L B ) technique suggested by
Rajashekhara and Nale [51.

Figure 3 C i r c u i t Schematic of P a r t i a l P r o d u c t G e n e r a t o r (PPG)

Table 2
B i t - P a i r Recoding to Generate RBSD P a r t i a l P r o d u c t B i t s

Multiplier Multiplicand partial product

Bjtl Bj Bj-l Ai ppjti ppjtitl ppjti
( i f A i is not MSB) (if A i
0 0 0 0 0
0 0 1 a - -a
0 1 0 a -a
0 1 1 a -
1 0 0 -a -
1 0 1 -a -
1 1 0 -a - a
a
1 1 1 0 - a
Note: B jtl, Bj, Bj-l, Ai are in TC form. The logic levels
0 and 1 corresponds to 08 and SV respectively.
x means don't care.
a E {O,l).
PPjti and PPjtitl are in RBSD form. The logic levels -1,
0, and 1 corresponds to OV, 2.5V, and 5V respectively.
0 and -0 are the same a s 0.

883
4. Conclusion
In this paper, we have presented a multiplier design
vhich makes use of RBSD adders designed uslng 3-valued
logic. Bit pair recoding 1s employed to generate
partial products in RBSD for0 using TC multiplier and
multiplicand operands. VLSI layouts are produced for
RBSD adder and partial product generator circuits
using MAGIC software on SUN vork station. Figures 4
lnd 5 show the layouts of portions of RBSD adder and
partial product generator circuits respectively. Each
functional unit and the complete multiplier circuit
are simulated using SPICE circuit simulation software
to verify the correctness of design. Currently ve are
vorking on the VLSI layout far a prototype of the
complete multiplier unit including RBSD to TC
converter. Extending bit pair recoding to multi-bit
recoding [ 8 1 is an interesting approach to explore and
investigate the trade off betveen increased circuit
complexity of multi-bit recoding and reduced set of
partial products.
Figure 4 VLSI Layout of RBSD Adder C e l l
Representing equation ( l ) , Fig. 1
Figure 5 VLSI Layout of P a r t i a l P r o d u c t G e n e r a t o r F i g u r e 3.
884
4. References
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[21 S. Kawahito, M. Kamayerna, T. Higuchi, and H. Yama-
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-Valued Radix-2 Signed-Digit Arithmetic Circuits
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