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Ken Takeuchi
Toshiba, NAND Flash Circuit Designer: ‘93-’07
University of Tokyo, Associate Professor: ‘07-
Developed 6 world’s highest density NAND (0.7μm 16Mb, 0.4μm
Solid-state drive (SSD) and memory 64Mb, 0.25μm 256Mb, 0.16μm 1Gb, 0.13μm 2Gb, 56nm 8Gb)
150 Patents Worldwide (88 U.S.Patents)
system innovation ISSCC Takuo Sugano Outstanding Paper Award: ’07
ISSCC Program Committee (Memory): ‘07-
07
Dec.11, 2008 Stanford Univ. MBA: ‘03
Ken Takeuchi
Dept. of Electrical Engineering and Information Systems,
University of Tokyo
E-mail : takeuchi@lsi.t.u-tokyo.ac.jp
http://www.lsi.t.u-tokyo.ac.jp ISSCC 1999 IEDM 2000 ISSCC 2002 ISSCC 2006
250nm 256M Flash 160nm 1G Flash 130nm 2G Flash 56nm 8G Flash
Ken Takeuchi Advanced Flash Memory Devices 1 Ken Takeuchi Advanced Flash Memory Devices 2
Outline Outline
Gartner Dataquest
J. Elliott, WinHEC 2007, SS-S499b_WH07.
Ken Takeuchi Advanced Flash Memory Devices 5 Ken Takeuchi Advanced Flash Memory Devices 6
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Ken Takeuchi Advanced Flash Memory Devices 7 Ken Takeuchi Advanced Flash Memory Devices 8
Future Block
Application Software Abstracted SSD
S/DRAM (<1ns)
File System (OS)
MP3 Player Go vertical
DRAM (10ns) SD Card
NAND Controller integration to
Bad Block Management USB Memory improve system-
DRAM (10ns) Wear-leveling level performance.
NAND Controller ECC
1bit/cell NAND (20us)
Smart Media
NAND Flash Memory
2-4bit/cell NAND (1~10ms) SSD
K. Takeuchi, ISSCC 2008 Tutorial T-7.
Ken Takeuchi Advanced Flash Memory Devices 9 Ken Takeuchi Advanced Flash Memory Devices 10
Ken Takeuchi Advanced Flash Memory Devices 11 Ken Takeuchi Advanced Flash Memory Devices 12
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Bitline
Bitline
Bitline
Ken Takeuchi Advanced Flash Memory Devices 13 Ken Takeuchi Advanced Flash Memory Devices 14
Active area
Ken Takeuchi Advanced Flash Memory Devices 15 Ken Takeuchi Advanced Flash Memory Devices 16
9 After precharging, bit-lines are discharged through the memory cell. 20V 20V
Typical page size : 2-4kB
Ken Takeuchi Advanced Flash Memory Devices 17 Ken Takeuchi Advanced Flash Memory Devices 18
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・・・
NAND Circuit Design
Page
P buffer
b ff
SSD Overview
Page buffer
Memory cell array T.Tanaka, Symp. on VLSI
Circuits 1990, pp.105-106.
NAND Controller Design
All memory cells in a page are
programmed at the same time. Operating System for SSD
Program speed = Page size / Programming time
Green IT with SSD
= 8KByte / 800us Summary
= 10MByte/sec (56nm MLC) K. Takeuchi, ISSCC 2006,pp.144-145.
Ken Takeuchi Advanced Flash Memory Devices 19 Ken Takeuchi Advanced Flash Memory Devices 20
Page
All cells
Sequential Access programmed ?
・・・
Yes
High Speed Programming End
Page buffer
High Speed Read
During the verify-read, the program data in the page buffer
is updated so that the program pulse is applied ONLY to
insufficiently programmed cells. T.Tanaka, Symp. on VLSI Circuits 1992, pp.20-21.
Ken Takeuchi Advanced Flash Memory Devices 21 Ken Takeuchi Advanced Flash Memory Devices 22
Random Access : High Speed Programming (Cont’) Random Access : High Speed Programming (Cont’)
Incremental Program Voltage Scheme Problems of MLC programming
Word-line waveform
Number of memory cells
Program pulse Program voltage, Vpgm
increases by ⊿Vpgm. “0” “1” “2” “3”
⊿Vpgm
Ken Takeuchi Advanced Flash Memory Devices 23 Ken Takeuchi Advanced Flash Memory Devices 24
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Random Access : High Speed Programming (Cont’) Random Access : High Speed Programming (Cont’)
Vth
1st page data : “1” “0”
2-level cell 4-level cell
2nd page program
Ken Takeuchi Advanced Flash Memory Devices 25 Ken Takeuchi Advanced Flash Memory Devices 26
Random Access : High Speed Programming (Cont’) Random Access : High Speed Programming (Cont’)
Step2
Step3
p
Ken Takeuchi Advanced Flash Memory Devices 27 Ken Takeuchi Advanced Flash Memory Devices 28
Random Access : High Speed Read Random Access : High Speed Read (Cont’)
Problems of MLC read Solution : Multi-page Cell Architecture
Number of memory cells Number of memory cells
“0” “1” “2” “3” “0” “1” “2” “3”
X1
X1
X2
Vth Vth X2
Y1 Y2 Y1 Y2 1st page data : “1” “0” “0” “1”
2-level cell 4-level cell
2-level cell 4-level cell
① ② ③ 2nd page data
d t : “1” “0”
MLC SLC
Two bits in a cell are
Two bits in a cell are assigned ② ① ③
“1”-read “1”-read
assigned to two row
to two column addresses.
1st page read : ②, ③ Æ EXOR addresses.
3 operations (“1”-, “2”- and
In average, 1.5 operations.
“2”-read “3”-read) required. 2nd page read : ①
Twice faster than
Long random read.
conventional scheme.
“3”-read
Ken Takeuchi Advanced Flash Memory Devices 29 Ken Takeuchi Advanced Flash Memory Devices 30
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Sequential Access : High Speed Programming Parallel Operation : Increase Page Size
Page size trend
Parallel Operation By increasing the word-line length, the page size has been
extended to increase the write and read throughput.
Increase page size 9000
Bit-line
Multi-page operation 8000
7000
Page
Multi-chip operation (Interleaving)
e (Byte)
6000
5000 ・・・
T be
To b discussed
di d in
i “NAND C
Controller
t ll Circuit
Ci it Design”
D i ” section
ti
Page size
4000
2000
Page buffer
Ken Takeuchi Advanced Flash Memory Devices 31 Ken Takeuchi Advanced Flash Memory Devices 32
Parallel Operation : Increase Page Size (Cont’) Parallel Operation : Increase Page Size (Cont’)
Problems : SG-WL noise Solution : Raise neighboring SG BEFORE bit-line discharge
[Conventional read/verify-read]
Bit-line
SG-WL capacitive
SGD coupling
Selected 1.5V
WL31
WL bounce
WL0
Bit-line Bit-line
precharge discharge
K. Takeuchi, ISSCC 2006,pp.144-145. K. Takeuchi, ISSCC 2006,pp.144-145.
Ken Takeuchi Advanced Flash Memory Devices 33 Ken Takeuchi Advanced Flash Memory Devices 34
Parallel Operation : Increase Page Size (Cont’) Parallel Operation : Increase Page Size (Cont’)
Problems : WL-WL noise Solution
Ken Takeuchi Advanced Flash Memory Devices 35 Ken Takeuchi Advanced Flash Memory Devices 36
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Ken Takeuchi Advanced Flash Memory Devices 39 Ken Takeuchi Advanced Flash Memory Devices 40
Ken Takeuchi Advanced Flash Memory Devices 41 Ken Takeuchi Advanced Flash Memory Devices 42
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New block
Bitline ③ Cell program
4KB page (max) 8KB page (max)
512KB block 1MB block Page buffer
② Data-out,
ECC, Data-in NAND
2 Select-gate 2 Select-gate System performance controller
32 Word-lines Source-line 32 Word-lines degradation
Block copy time
In case a part of the block is over-written, a block copy = (T_Cell read+T_Data_out+TECC+T_Cell program)
operation is performed. Fast block copy required ×(# of pages per block)
= 125ms K. Takeuchi, ISSCC 2006,pp.144-145.
Ken Takeuchi Advanced Flash Memory Devices 43 Ken Takeuchi Advanced Flash Memory Devices 44
Pipeline Operation : Cache Page Copy Smaller Block Size: All Bit-line Architecture
Solution : Fast block copy All bit-line architecture
Step1 Step2 Step3 Step4 # of pages in a block is half.
Old block Old block
Old block
Page i
Old block
Block copy time is also half.
Page i+1
56nm NAND 43nm NAND
Cell Read Cell read (Alternate bit-line architecture) (All bit-line architecture)
New block New block New block New block
Cell program
Ken Takeuchi Advanced Flash Memory Devices 45 Ken Takeuchi Advanced Flash Memory Devices 46
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Vcc
Vpgm
(18V)
Vpass
(10V)
Vpass disturb cell
Vpgm disturb cell 10V
18V J. D. Lee, NVSMW 2006, pp. 31-33.
Vpass K.T.Park, SSDM 2006, pp.298-299.
(10V) D S
0V
0V
D ~8V S
Hot carriers generated at the select gate edge inject
Vcc
into the memory cell causing a Vth shift.
The Vth shift can be reduced by increasing SG-WL
Both selected and unselected cells suffer from the disturb. space.
K. D. Suh, ISSCC 1995, pp.128-129.
Ken Takeuchi Advanced Flash Memory Devices 51 Ken Takeuchi Advanced Flash Memory Devices 52
Vread (4.5V)
4.5V
Selected word-line
(0V)
D 0V S
Vread (4.5V)
Ken Takeuchi Advanced Flash Memory Devices 53 Ken Takeuchi Advanced Flash Memory Devices 54
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Ken Takeuchi Advanced Flash Memory Devices 57 Ken Takeuchi Advanced Flash Memory Devices 58
NAND I/F
HDD-like architecture : DRAM buffer to hide NAND random access
High power consumption
NAND Flash Memory High cost
C. Park, NVSMW 2006, pp.17-20.
Ken Takeuchi Advanced Flash Memory Devices 59 Ken Takeuchi Advanced Flash Memory Devices 60
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DRAM eliminated :
Random access of NAND
is faster than HDD.
Low p power consumption
p
Low cost
Multi-channel
Parallel operation
High bandwidth
Ken Takeuchi Advanced Flash Memory Devices 61 Ken Takeuchi Advanced Flash Memory Devices 62
Bitline
Ken Takeuchi Advanced Flash Memory Devices 63 Ken Takeuchi Advanced Flash Memory Devices 64
Dynamic wear-leveling
Wear-level only over empty and dynamic data. Physical block address
Static wear-leveling Block with static data is NOT used for wear-leveling.
Wear-level over all data including static data. Write and erase concentrate on the dynamic data block.
N.Balan, MEMCON2007.
SiliconSystems, SSWP02.
Ken Takeuchi Advanced Flash Memory Devices 65 Ken Takeuchi Advanced Flash Memory Devices 66
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Ken Takeuchi Advanced Flash Memory Devices 69 Ken Takeuchi Advanced Flash Memory Devices 70
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SATA-I
8/16/32/48/64GB
SATA-II
8/16/32/48/64GB
SLC 4KByte sector size fits better with SSD.
PATA
4/8/16/32GB (Single Level Cell)
R/W Speed: 57/32 64/45 100/80 160/160 800/800 1300/1300
Ken Takeuchi Advanced Flash Memory Devices 73 Ken Takeuchi Advanced Flash Memory Devices 74
Old block
is required.
9000 1200
32WLs 32WLs
8000
① Cell read 1000
7000
yte)
New block
e)
800
Page size (Byte
6000
degradation 0 0
Block copy time 0.25um 0.16um 0.13um 90nm 70nm 50nm 43nm 0.25um 0.16um 0.13um 90nm 70nm 50nm 43nm
Design rule Design rule
= (T_Cell read+T_Data_out+TECC+T_Cell program)
Fast block copy required ×(# of pages per block)
= 125ms K. Takeuchi, ISSCC 2006,pp.144-145.
Ken Takeuchi Advanced Flash Memory Devices 75 Ken Takeuchi Advanced Flash Memory Devices 76
http://msdn2.microsoft.com/en-us/library/ms912909.aspx http://www.tdk.co.jp/tefe02/ew_007.pdf
Ken Takeuchi Advanced Flash Memory Devices 77 Ken Takeuchi Advanced Flash Memory Devices 78
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Power Consumption
p
SSD Because of the scaling, the parasitic capacitance
(NAND Flash) increases and the power consumption doubles.
Æ Low power memory device required
HDD Capacity
Currently Gbyte Æ TByte required
Ken Takeuchi Advanced Flash Memory Devices 81 Ken Takeuchi Advanced Flash Memory Devices 82
8080
6060
Cwire-wire Cwire-wire M Pt
4040 F SrBi2Ta2O9
2020 I Hf-Al-O MFIS Structure
n+ n+ (Metal-Ferroelectric-
00
10 20 30 40 50 60 70
10 20 Feature
30 40 size
50 [nm]
60 70 Cwire-wire Cwire-wire p-Si Insulator-Semiconductor)
S. Sakai, NVSMW 2008, pp.103-104.
K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125.
Ken Takeuchi Advanced Flash Memory Devices 83 Ken Takeuchi Advanced Flash Memory Devices 84
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Vth (V)
-4
10
On states 0.8 Erased
urrent, Id (A)
10
-6 M Pt Programmed
F SrBi2Ta2O9 0.7
-8 1st 37.0 days
10 2nd I Hf-Al-O 0.6
3rd
n+
n n+
Drain Cu
-10
10
10 4th 33 5 d
33.5 days 0.5
0 5
p-Si 10
3
10
4
10
5
10 10
6
10
7 8
-12
10 Number of Cycles S. Sakai, NVSMW 2008, pp.103-104.
10 years
-14 Off states
10
0 2 4 6 8
10 10 10
Time, t (s)
10 10
Buffer layer improves Si‐ NAND
interface characteristics.
Ken Takeuchi Advanced Flash Memory Devices 87 Ken Takeuchi Advanced Flash Memory Devices 88
Co-design of NAND and Controller Circuits Co-design of NAND and Controller Circuits
By co-designing both NAND and NAND controller circuits,
the power consumption of SSD is reduced by 60%.
100
CE1, R/B1
• Low Power Circuit Technology
Operation current [mA]
NAND
NAND
Chip1
NAND
Chip2
NAND
Chip3
NAND
Chip4
6060
Selective BL precharge
& Advanced SL program – Selective bit-line precharge scheme
48%
Controller
4040 reduction
– Advanced source-line program
NAND Flash Power Detect
((PD))
2020
O
Memory 00
ALE, CLE, RE, WE, WP, IO 10 20 30 40 50 60 70
10 20 Feature
30 40 size
50 [nm]
60 70
Current waveform
of NAND Chip1
• Low Noise Circuit Technology
Time
Current waveform
of NAND Chip2 – Intelligent interleaving
Time
Current waveform
of NAND Chip3
Time
Current waveform
of NAND Chip4
Time
NAND Controller K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125. K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125.
Ken Takeuchi Advanced Flash Memory Devices 89 Ken Takeuchi Advanced Flash Memory Devices 90
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Controller
Channel 4 10
• Limitation of N 4
Ken Takeuchi Advanced Flash Memory Devices 91 Ken Takeuchi Advanced Flash Memory Devices 92
100
100
100 Algorithm Erased state “A” “B” “C”
Operattion current [mA]
8080
8080 Data load
6060
6060 Vth
Program pulse VA VB VC
4040 4040 1st page program 2nd page program
End
• Low power circuit of NAND required.
K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125. K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125.
Ken Takeuchi Advanced Flash Memory Devices 93 Ken Takeuchi Advanced Flash Memory Devices 94
Ken Takeuchi Advanced Flash Memory Devices 95 Ken Takeuchi Advanced Flash Memory Devices 96
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Vth
Vth VA VB VC
VA VB VC
1st page program 2nd page program
1st page program 2nd page program
[Conventional] [Proposed] [Conventional] [Proposed]
“A”-program complete / incomplete “A”-program complete “B”-program complete / incomplete “B”-program complete
Program inhibit Program inhibit “A”-program incomplete “C”-program complete / incomplete “C”-program complete / incomplete
Program inhibit Program inhibit “B”-program incomplete
Bit-line Bit-line Bit-line Bit-line
Word-line Word-line Word-line Word-line
VA VA VB VB
Time Time Time
Bit-line Time Bit-line Bit-line
Bit-line Bit-line Bit-line discharge Bit-line Bit-line discharge
precharge discharge precharge discharge precharge precharge
Ken Takeuchi Advanced Flash Memory Devices 97 Ken Takeuchi Advanced Flash Memory Devices 98
yte/sec]
Vth 100
23% reduction 100
Operation current [[mA]
VA VB VC 100
8080 系列1
Conventional
Ken Takeuchi Advanced Flash Memory Devices 99 Ken Takeuchi Advanced Flash Memory Devices 100
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Bit-line
Bit-line
Bit-line
Bit-line
Row decoder Row decoder Row decoder Row decoder Row decoder
Row decoder Row decoder Row decoder Row decoder Row decoder
Local source-line
Local source-line Source-line Local source-line Source-line
Source-line Local source-line Source-line ON
Switch decoder decoder
decoder decoder
Global source-line
Global source-line ON
K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125. K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125.
Ken Takeuchi Advanced Flash Memory Devices 103 Ken Takeuchi Advanced Flash Memory Devices 104
yte/sec]
Bit-line
100
23% reduction 100
100
Operation current [[mA]
8080 系列1
Conventional
K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125. K. Takeuchi, Symposium on VLSI CIrcuits, 2008, pp.124-125.
Ken Takeuchi Advanced Flash Memory Devices 105 Ken Takeuchi Advanced Flash Memory Devices 106
Ken Takeuchi Advanced Flash Memory Devices 107 Ken Takeuchi Advanced Flash Memory Devices 108
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R/B4 (chip4)
• Intelligent interleaving realizes highly reliable
●
● and high-speed SSD.
●
Ken Takeuchi Advanced Flash Memory Devices 109 Ken Takeuchi Advanced Flash Memory Devices 110
DRAM
MPU Core Logic Emerging Market: Power Crisis at data center
ROM Flash
SSD is expected to save power at data center.
Cache
Analog
3D SiP
3D-SiP Logic
SoC
ROM
Analog Flash Device, circuit and OS innovation required.
DRAM Cache Co-design of NAND and NAND controller circuits
MPU Core
OS optimization such as sector size optimization
Fe(Ferroelectric)-NAND flash memory device
To be presented at ISSCC in Feb. 2009@San Francisco.
3D-integrated SSD circuits
13.2. “A 1.8V 30nJ Adaptive Program-Voltage (20V) Generator
for 3D-Integrated NAND Flash SSD”
Ken Takeuchi Advanced Flash Memory Devices 111 Ken Takeuchi Advanced Flash Memory Devices 112
Thank you!
E-mail : takeuchi@lsi.t.u-tokyo.ac.jp
http://www.lsi.t.u-tokyo.ac.jp
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