TYPES OF PROCESSORS:

ARM PROCESSOR:
The ARM is a 32-bit reduced instruction set
computer (RISC) instruction set architecture (ISA) developed by ARM Holdings. It was
known as the Advanced RISC Machine, and before that as the Acorn RISC Machine.
The ARM architecture is the most widely used 32-bit ISA in terms of numbers
produced.They were originally conceived as a processor for desktop personal computers
by Acorn Computers, a market now dominated by the x86 family used by IBM PC
compatible computers. The relative simplicity of ARM processors made them suitable for
low power applications. This has made them dominant in the mobile and embedded
electronics market as relatively low cost and small microprocessors and microcontrollers.

As of 2007, about 98 percent of the more than one billion mobile phones sold each year
use at least one ARM processor.As of 2009, ARM processors account for approximately
90% of all embedded 32-bit RISC processors. ARM processors are used extensively in
consumer electronics, including PDAs, mobile phones, digital media and music players,
hand-held game consoles, calculators and computer peripherals such as hard drives and
routers.

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LINCEES COMPANIES:
The ARM architecture is licensable. Companies that
are current or former ARM licensees include Alcatel-Lucent, Apple Inc., Atmel,
Broadcom, Cirrus Logic, Digital Equipment Corporation, Freescale, Intel (through DEC),
LG, Marvell Technology Group, NEC, NVIDIA, NXP (previously Philips), Oki,
Qualcomm, Samsung, Sharp, STMicroelectronics, Symbios Logic, Texas Instruments,
VLSI Technology, Yamaha and ZiiLABS.

HISTORY:
After achieving some success with the BBC Micro computer, Acorn Computers Ltd
considered how to move on from the relatively simple MOS Technology 6502 processor
to address business markets like the one that would soon be dominated by the IBM PC,
launched in 1981. The Acorn Business Computer (ABC) plan required a number of
second processors to be made to work with the BBC Micro platform, but processors such
as the Motorola 68000 and National Semiconductor 32016 were unsuitable, and the 6502
was not powerful enough for a graphics based user interface.

Acorn RISC Machine: ARM2

The official Acorn RISC Machine project started
in October 1983. VLSI Technology, Inc was chosen as silicon partner, since it already
supplied Acorn with ROMs and some custom chips. The design was led by Wilson and
Furber, with a key design goal of achieving low-latency input/output (interrupt) handling
like the MOS Technology 6502 used in Acorn's existing computer designs. The 6502's
memory access architecture had allowed developers to produce fast machines without the
use of costly direct memory access hardware. VLSI produced the first ARM silicon on 26
April 1985 – it worked first time and came to be known as ARM1 by April 1985The first
"real" production systems named ARM2 were available the following year.

Apple, DEC, Intel: ARM6, StrongARM, Xscale:

In the late 1980s
Apple Computer and VLSI Technology started working with Acorn on newer versions of
the ARM core. The work was so important that Acorn spun off the design team in 1990
into a new company called Advanced RISC Machines Ltd. For this reason, ARM is
sometimes expanded as Advanced RISC Machine instead of Acorn RISC Machine.
Advanced RISC Machines became ARM Ltd when its parent company, ARM Holdings
plc, floated on the London Stock Exchange and NASDAQ in 1998.

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SUPPORTED VERSIONS OF LINUX,BSD AND SOLARIS:
LINUX

• Android
• Ångström
• Chrome OS
• Debian
• ELinOS
• Fedora
• Gentoo
• GoboLinux
• Maemo
• MontaVista
• Slackware
• T2 SDE
• Ubuntu
• webOS
• Wind River Linux

BSD

The following BSD derivatives support ARM processors:

• FreeBSD
• NetBSD
• OpenBSD

Solaris

• OpenSolaris

X86-64 PROCESSOR:
x86-64 is an extension of the x86 instruction
set. It adds support for vastly larger virtual and physical address spaces, 64-bit general
purpose registers, and numerous other enhancements. The original specification was
created by AMD, and has been implemented by AMD, Intel, VIA, and others. It is fully
backwards compatible with 32-bit code. Because the full 32-bit instruction set remains
implemented in hardware without any intervening emulation, existing 32-bit x86
executables run with no compatibility or performance penalties, although existing

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applications that are recoded to take advantage of new features of the processor design
may see significant performance increases.

AMD64:
The AMD64 instruction set is implemented in AMD's Athlon 64, Athlon 64 FX, Athlon
64 X2, Athlon II, Athlon X2, Opteron, Phenom, Phenom II, Turion 64, Turion 64 X2,
and later Sempron processors.

History of AMD64

AMD64 was created as an alternative to Intel and Hewlett Packard's radically different
IA-64 architecture. Originally announced in 1999 with a full specification in August
2000, the architecture was positioned by AMD from the beginning as an evolutionary
way to add 64-bit computing capabilities to the existing x86 architecture, as opposed to
Intel's approach of creating an entirely new 64-bit architecture with IA-64.

The first AMD64-based processor, the Opteron, was released in April 2003.

ARCHITECTURAL FEATURES:
The primary defining characteristic of AMD64 is the availability of 64-bit general-
purpose processor registers, i.e. rax, rbx etc., 64-bit integer arithmetic and logical
operations, and 64-bit virtual addresses. The designers took the opportunity to make other
improvements as well. The most significant changes include:

• 64-bit integer capability: All general-purpose registers (GPRs) are expanded

from 32 bits to 64 bits, and all arithmetic and logical operations, memory-to-
register and register-to-memory operations, etc., can now operate directly on 64-
bit integers..

• Additional registers: In addition to increasing the size of the general-purpose

registers, the number of named general-purpose registers is increased from eight
(i.e. eax, ebx, ecx, edx, ebp, esp, esi, edi) in x86-32 to 16 (i.e. rax, rbx, rcx, rdx,
rbp, rsp, rsi, rdi, r8, r9, r10, r11, r12, r13, r14, r15). It is therefore possible to keep
more local variables in registers rather than on the stack, and to let registers hold
frequently accessed constants

• Additional XMM (SSE) registers: Similarly, the number of 128-bit XMM

registers (used for Streaming SIMD instructions) is also increased from 8 to 16.

• Larger virtual address space: Current processor models implementing the

AMD64 architecture define a 64-bit virtual address format, of which the low-
order 48 bits are implementedThey are therefore able to address up to 256 TiB
(248 or 281,474,976,710,656 bytes) of virtual address space.

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 • Larger physical address space: Current implementations (starting from AMD
10th microarchitecture) of the AMD64 architecture can address up to 256 TiB (248
or 281,474,976,710,656 bytes) of RAM; the architecture permits extending this to
4 PiB (252 or 4,503,599,627,370,496 bytes) in the future (limited by the page table
entry format). In legacy mode, Physical Address Extension (PAE) is included, as
it is on most current 32-bit x86 processors, but is extended to allow access to a
maximum of 4 PiB (252 or 68,719,476,736 bytes).

• Instruction pointer relative data access: Instructions can now reference data
relative to the instruction pointer (RIP register). This makes position independent
code, as is often used in shared libraries and code loaded at run time, more
efficient.

• SSE instructions: The original AMD64 architecture adopted Intel's SSE and
SSE2 as core instructions. SSE3 instructions were added in April 2005. SSE2 is
an alternative to the x87 instruction set's IEEE 80-bit precision with the choice of
either IEEE 32-bit or 64-bit floating-point mathematics.

• No-Execute bit: The "NX" bit (bit 63 of the page table entry) allows the
operating system to specify which pages of virtual address space can contain
executable code and which cannot.

• Removal of older features: A number of "system programming" features of the

x86 architecture are not used in modern operating systems and are not available
on AMD64 in long (64-bit and compatibility) mode.

AMD64 IMPLEMENTATIONS:
The following processors implement the AMD64 architecture:

• AMD Athlon 64
• AMD Athlon 64 X2
• AMD Athlon 64 FX
• AMD Athlon II (followed by 'X2', 'X3', or 'X4' to indicate the number of cores)
• AMD Opteron
• AMD Turion 64
• AMD Turion 64 X2
• AMD Sempron ("Palermo" E6 stepping and all "Manila" models)
• AMD Phenom (followed by 'X3' or 'X4' to indicate the number of cores)
• AMD Phenom II (followed by 'X2', 'X3', 'X4' or 'X6' to indicate the number of
cores)

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INTEL 64:
Intel 64 is Intel's implementation of x86-64. It is used in newer versions of Pentium 4,
Pentium D, Pentium Extreme Edition, Celeron D, Xeon and Pentium Dual-Core
processors, the Atom 230, 330, D510, and N450 and in all versions of the Core 2, Core
i7, Core i5 and Core i3 processors.

History of Intel 64

Historically, AMD has developed and produced processors patterned after Intel's original
designs, but with x86-64, roles were reversed: Intel found itself in the position of
adopting the architecture which AMD had created as an extension to Intel's own x86
processor line.

Intel's project was originally codenamed Yamhill (after the Yamhill River in Oregon's
Willamette Valley). After several years of denying its existence, Intel announced at the
February 2004 IDF that the project was indeed underway. Intel's chairman at the time,
Craig Barrett, admitted that this was one of their worst kept secrets.

Recent implementations

• Intel 64's BSF and BSR instructions act differently when the source is 0 and the
operand size is 32 bits. The processor sets the zero flag and leaves the upper
32 bits of the destination undefined.

• AMD64 requires a different microcode update format and control MSRs while
Intel 64 implements microcode update unchanged from their 32-bit only
processors.

• Intel 64 lacks some model-specific registers that are considered architectural to

AMD64. These include SYSCFG, TOP_MEM, and TOP_MEM2.

• Intel 64 allows SYSCALL and SYSRET only in IA-32e mode (not in

compatibility mode). It allows SYSENTER and SYSEXIT in both modes.
• AMD64 lacks SYSENTER and SYSEXIT in both sub-modes of long mode.

• Near branches with the 66H (operand size) prefix behave differently. Intel 64
clears only the top 32 bits, while AMD64 clears the top 48 bits.

• More recent AMD64 processors support 1GB pages in addition to 4kB and 2MB.

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In 1998 Fujitsu developed the first SPARC64 processor. Called SPARC64 GP it was
used in the G7000F family of servers.

In 2002, SPARC64 V, with improved reliability technology inherited from Fujitsu

mainframe development, was used in PRIMEPOWER. PRIMEPOWER with SPARC64
V was sold world-wide and grew to become a respected global platform.

In 2007, all SPARC Enterprise models use the latest SPARC V9 architecture dual cores
processors. SPARC64 VI for M4000 model and above and UltraSPARC T1 for
T1000/T2000. Models incorporating the dual core processor SPARC64 VI inherit all the
high reliability and availability technologies of SPARC64 V.

In 2008, SPARC Enterprise mid-range and high end models incorporated Quad cores
processors SPARC64 VII, together with SPARC64 VI.

FEATURES:
The SPARC processor usually contains as many as 128 general purpose registers. At any
point, only 32 of them are immediately visible to software - 8 are global registers (one of
which, g0, is hard-wired to zero, so only 7 of them are usable as registers) and the other
24 are from the stack of registers. These 24 registers form what is called a register
window, and at function call/return, this window is moved up and down the register
stack. Each window has 8 local registers and shares 8 registers with each of the adjacent
windows. The shared registers are used for passing function parameters and returning
values, and the local registers are used for retaining local values across function calls.

History:
There have been three major revisions of the architecture. The first published revision
was the 32-bit SPARC Version 7 (V7) in 1986. SPARC Version 8 (V8), an enhanced
SPARC architecture definition, was released in 1990 by the SPARC Architecture
Committee consisting of Amdahl Corporation, Fujitsu, ICL, LSI Logic, Matsushita,
Phillips, Ross Technology, Sun and Texas Instruments. SPARC V8 was standardized as
IEEE 1754-1994, an IEEE standard for a 32-bit microprocessor architecture.

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SPARC Version 9, the 64-bit SPARC architecture, was released by SPARC International
in 1993. 2002 the SPARC Joint Programming Specification 1 (JPS1) was released by
Fujitsu and Sun, describing processor functions which were identically implemented in
the CPUs of both companies ("Commonality").

Operating system support:

SPARC machines have generally used Sun's SunOS, Solaris Operating System or
OpenSolaris, but other operating systems such as NEXTSTEP, RTEMS, FreeBSD,
OpenBSD, NetBSD, and Linux have also been used.

In 1993, Intergraph announced a port of Windows NT to the SPARC architecture, but it

was later cancelled.

Open source implementations

Three fully open source implementations of the SPARC architecture exist.

• LEON, a 32-bit, single-thread SPARC Version 8 implementation, designed

especially for space use. Source code is written in VHDL, and licensed under the
GPL.
• OpenSPARC T1, released in 2006, a 64-bit, 32-thread implementation
conforming to the UltraSPARC Architecture 2005 and to SPARC Version 9
(Level 1). Source code is written in Verilog, and licensed under many licenses.
Most OpenSPARC T1 source code is licensed under the GPL.
• S1, a 64-bit Wishbone compliant CPU core based on the OpenSPARC T1 design.
It is a single UltraSPARC v9 core capable of 4 way SMT.
• OpenSPARC T2, released in 2008, a 64-bit, 64-thread implementation
conforming to the UltraSPARC Architecture 2007 and to SPARC Version 9
(Level 1). licenses. Binary programs are licensed under a binary Software License
Agreement.

Supercomputers

As of June 2009, only one supercomputer using SPARC microprocessors is included in

the world's top 500 fastest supercomputers according to the TOP500 list.

SPARC ENTERPRISE:
The SPARC Enterprise series is a range of UNIX server computers co-developed by
Sun Microsystems and Fujitsu introduced in 2007. They are marketed and sold by Sun
Microsystems, Fujitsu, and Fujitsu Siemens Computers under the common brand of
SPARC Enterprise, superseding Sun's Sun Fire and Fujitsu's PRIMEPOWER server
product lines.

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Reference:

• Pbc articles and glossaries

• Wikepedia
• Intel® Software Network, 64 bits"
• TurboIRC.COM
• Optimization of 64-bit programs
• Seven Steps of Migrating a Program to a 64-bit System