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62
Digital Electronics-II 63
SECTION-B
As this circuit uses only two resistor R and 2R and connected in such a manner
that it form a ladder that is why this type of circuit called R/2R ladder D/A
convertor.
The working of the circuit is explain by giving High signal to one of the data
Input and other data input are at Low level.
66 NORTH Solved Question Papers
2R||2R
RAeq = 2R R R = 2 R 2R R 2R R
2R
= 2 R 2R R 2R
Now the circuit shown in figure a reduces as shown in figure.
i.e. Data input to network is 0100. By applying these data signal the circuit
shown in fig 8 become as shown in figure.
RAeq = 2 R 2R R
RAeq= R + R = 2R
Now the circuit shown in figure reduces as shown in figure.
To find out current flowing through feed back resistance Rf the circuit up to B
of figure is simplified using Thevenins theorem as shown in figure.
Vth = RAeq I
5
I =
4R
68 NORTH Solved Question Papers
5
Vth = 2R 2.5V
4R
Rth = 2 R 2R R
By applying thevenin equivalent to figure the circuit become as shown in
figure.
From the circuit as shown in figure, we can calculate output voltage easily. The
current flowing through the feedback resistance Rf is
0 2.5 2.5
I = A
2R 2R
and output voltage of the circuit is
25
VOutput = R f = 2.5V As Rf = 2R
2R
Hence for signal 0100 the analog voltage is –2.5V as the output voltage become
half when the input data signal reduces to next lower significance bit similarly for
data input 0010. The output voltage is = – 1.25 and for data input 0001 the output
voltage is = – 0.625V
Q.5. Explain arithmetic unit of ALU ?
Ans. One of an arithmetic circuit that gives the operations shown above is
shown in Fig. The full-adder circuit represents one state of the parallel-adder. The
two selection lines S1 and S0 control the data path between the B terminal and one
input of the full-adder circuit. When S1S0 = 00, the controlled input of the full-adder
is always 0. When S1S0 = 01, the input receives the value of Bp When S1S0 = 10, the
Digital Electronics-II 69
input receives the complement value of B1. With S1S0 = 11, the input is always equal
to 1. These conditions can be verified by driving the truth table of the selection logic.
The FPGAs are developed in 1984 by the Xilinx Corporation of America. These
FPGA devices are composed of a number of configurable logic blocks (CLBs). The
diagram of a FPGA device is shown above.
The above diagram shows a FPGA device which contains 64 CLBs arranged in a
8 8 matrix. There are four inputs (A, B, C, D) are applied to each CLB which can
implement a logic function up to four variables. So, each CLB consists of four inputs
& a clock input & two outputs P & Q. The above diagram also contains a 58 number
of input/output blocks. Each IOB consists of a single input & three state output.
These IOBs are configured with flip flops & can be accessed by the CLB for non
input/output functions. The input/output blocks provides us the interface between
the internal logic circuit & the external pins of the device. So, in a summarized
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manner, we can say that FPGA is a programmable logic device which contains a very
large number of equivalent gates on a single IC chip.
SECTION-C
Note : Attempt all questions. (510=50)
Q.8. Describe the IC for ALU in detail.
Ans. I.C. for ALU : There are several complex ICs available in the TTL and
CMOS families that can perform one or more types of operations.
IC 74181 is a basic ALU in TM 7400 series. It is capable of adding, subtracting,
incrementing, decrementing and performing shift operations and logical operations.
The ICs 74LS381 and 74HC381 are called arithmetic logic Units/function
generators. They can perform eight different binary arithmetic and logic operations
on two 4-bit Inputs.
The block diagram of IC 74181 is shown in figure. which is used to perform
different arithmetic and logical operations.
Fig.
Circuit Diagram Of 74181 : The logical diagram of I.C. 74181 is shown in
figure. This I.C belongs TTL series family operated by + 5 supply. This I.C. is
capable to perform 16 different operation, depending upon the select line S0 , S1 , S2 ,
S3. The perform Arithmetic or logical function depend upon the mode control (M). If
M is at high level then performs logic operation and if M is at low level then it
perform arithmetic operation. This I.C. accept 4 bit two data bit namely A3 , A2 , A1 ,
A0 and B3 B2 B1 B and give 4 bit data output F3 , F2, F1 , F0. There is another two
terminal namedC1n (carrey input) and Cn + 4 (carry output) used by cascading ALU
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I.C. Carrey input (Cin) also effect the operation of Arithmetic and logic function.
Functional table of ALU with operation of carrey input shown in table as.
Table 1 : Function table at I.C. 74181
Active High Data
M=H
M=L
Select Input Logic
Arithmetic Functions
Functions
S3 S2 S1 S0 Cn = H (no carry) Cn = L (with carry)
L L L L F= A F=A F = A Plus 1
L L L H F = AB F=A+B F = (A + B) Plus 1
L L H L F = AB F=A+ B F = A B Plus 1
H L H H F = AB F = AB Minus 1 F = AB
H H L L F=1 F = A Plus A F = A Plus A Plus 1
H H L H F=A+ B F = (A + B) Plus A F = (A + B) Plus A Plus 1
H H H L F=A+B F = A B Plus A F = A B Plus A Plus 1
n
6 2
So, no. of required flip flops = 3.
State diagram of the mod-6 counter is given by
A B C JA KA JB KB JC KC
0 0 0 0 1 0 0 1 0
0 0 1 0 0 1 0 0 1
0 1 0 0 0 0 0 1 0
0 1 1 1 0 0 1 0 1
1 0 0 0 0 0 0 1 0
1 0 1 0 0 1 0 0 1
J A = BC
AB
C 00 01 11 10
0 1 0 0 0
0 2 06 4
1 0 0 0 0
1 3 7 5
KA A .
AB
C 00 01 11 10
0 0 0 0 0
1 1 0 0 1
JB C
AB 00 01 11 10
C
0 0 0 0 0
1 0 1 0 0
KB C
AB 00 01 11 10
C
0 1 1 0 1
1 0 0 0 0
JC 1
Digital Electronics-II 77
AB 00 01 11 10
C
0 0 0 0 0
1 1 1 0 1
KC 1
shift register. The CCD memories are simple & low cost devices. The CCD memories
are used where the serially accessed memory is required.
The figure shows a block diagram of ACCD memory.
The FPGAs are developed in 1984 by the Xilinx Corporation of America. These
FPGA devices are composed of a number of configurable logic blocks (CLBs). The
diagram of a FPGA device is shown above.
The above diagram shows a FPGA device which contains 64 CLBs arranged in a
8 8 matrix. There are four inputs (A, B, C, D) are applied to each CLB which can
implement a logic function up to four variables. So, each CLB consists of four inputs
& a clock input & two outputs P & Q. The above diagram also contains a 58 number
of input/output blocks. Each IOB consists of a single input & three state output.
These IOBs are configured with flip flops & can be accessed by the CLB for non
input/output functions. The input/output blocks provides us the interface between
the internal logic circuit & the external pins of the device. So, in a summarized
manner, we can say that FPGA is a programmable logic device which contains a very
large number of equivalent gates on a single IC chip.
80 NORTH Solved Question Papers
In basic TTL inverter circuit the transistor T1 is the input coupling capacitor T2
is called phase shifter and transistor T3 and T4 make the output circuit. The
arrangement of transistor T3 and T4 make the totem pole configuration.
The totem pole configuration is same as Push Pull Output ; however, it
is the terminology commonly used when referring to a TTL device. The
major difference between it and Push Pull arrangement is the amount of
current that it can sink or source. The totem pole output is going to
sink/source less current than a Push Pull output. The other major
difference is the output voltage between the two. The totem pole have a 5V
dc signal only whereas Push Pull will follow the input voltage.
Operation of TTL Inverter : When the input is high, the base emitter
junction of transistor T1 is reversed biased and base collector junction is forward
biased. This allow the flow of current from R1 to base of transistor T2, make it in to
saturation. Due to the conduction of transistor T2 the transistor T4 come in to cut off
state and transistor T3 come in to saturation state. As the output is taken at the
collector of T3 so the output of the circuit is nearly to saturation voltage i.e. at
ground level. It means that for high input the output is low.
Similarly for low input signal, the base emitter junction of transistor T1 is in
forward bias whereas collector base junction is in reverse bias state hence current
will flow from resistance R1 to input terminal no current will flow to the base of
transistor T2, So it is in off state. Hence collector at transistor Q2 is at high state and
emitter at low state. This will turned ON the transistor T4 and turned off transistor
T3. Due to the off state of T3 all the supply voltage appeared at the output i.e.
output become high.
Hence the operation of inverter circuit is verified also truth table is
implemented as :
Input Output
Low High
High Low